Merge branch 'bugfix/adc2_single_read0_with_wifi_on' into 'master'

ADC: support ADC2 single read while WifI is on

Closes IDFCI-353 and IDF-3454

See merge request espressif/esp-idf!14152

components/driver/adc_common.c

@@ -593,6 +593,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     //avoid collision with other tasks
     adc2_init();   // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
     SARADC2_ENTER();
+
+#if SOC_ADC_ARBITER_SUPPORTED
+    adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
+    adc_hal_arbiter_config(&config);
+#endif
+
 #ifdef CONFIG_ADC_DISABLE_DAC
     adc2_dac_disable(channel);      //disable other peripherals
 #endif

components/driver/esp32c3/adc.c

@@ -538,6 +538,9 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
 
     SAR_ADC2_LOCK_ACQUIRE();
 
+    adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
+    adc_hal_arbiter_config(&config);
+
     adc_atten_t atten = s_atten2_single[channel];
     uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten);
     adc_hal_set_calibration_param(ADC_NUM_2, cal_val);

components/driver/test/test_adc2_with_wifi.c

@@ -17,32 +17,46 @@
 #include "test_utils.h"
 #include "driver/i2s.h"
 #include "driver/gpio.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "driver/gpio.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)
+
-#include "driver/dac.h"
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32S3)
 
 static const char* TAG = "test_adc2";
 
-#ifdef CONFIG_IDF_TARGET_ESP32
-    #define ADC_TEST_WIDTH         ADC_WIDTH_BIT_12
-    #define ADC_TEST_RESOLUTION    (4096)
-    #define ADC_TEST_DAC_RANGE     (256)
-    #define ADC_TEST_CH1           ADC2_CHANNEL_8
-    #define ADC_TEST_CH2           ADC2_CHANNEL_9
-    #define ADC_TEST_ERROR         (600)
-    #define ADC1_CHANNEL_4_IO      (32)
-    #define SAMPLE_RATE            (36000)
-    #define SAMPLE_BITS            (16)
-#elif defined CONFIG_IDF_TARGET_ESP32S2
-    #define ADC_TEST_WIDTH         ADC_WIDTH_BIT_13   //ESP32S2 only support 13 bit width
-    #define ADC_TEST_RESOLUTION    (8192)
-    #define ADC_TEST_DAC_RANGE     (210)
-    #define ADC_TEST_CH1           ADC2_CHANNEL_6
-    #define ADC_TEST_CH2           ADC2_CHANNEL_7
-    #define ADC_TEST_ERROR         (1500)
-#endif
 #define DEFAULT_SSID "TEST_SSID"
-#define DEFAULT_PWD "TEST_PASS"
+#define DEFAULT_PWD  "TEST_PASS"
+
+#if CONFIG_IDF_TARGET_ESP32
+#define ADC2_CHAN1              ADC2_CHANNEL_9
+#define ADC_WIDTH               ADC_WIDTH_BIT_12
+#define ADC_HIGH                4095
+#define ADC_ERROR_THRES         20
+#elif CONFIG_IDF_TARGET_ESP32S2
+#define ADC2_CHAN1              ADC2_CHANNEL_7
+#define ADC_WIDTH               ADC_WIDTH_BIT_13
+#define ADC_HIGH                8191
+#define ADC_ERROR_THRES         100
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define ADC2_CHAN1              ADC2_CHANNEL_0
+#define ADC_WIDTH               ADC_WIDTH_BIT_12
+#define ADC_HIGH                4095
+#define ADC_ERROR_THRES         100
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define ADC2_CHAN1              ADC2_CHANNEL_0
+#define ADC_WIDTH               ADC_WIDTH_BIT_12
+#define ADC_HIGH                4095
+#define ADC_ERROR_THRES         100
+#endif
+
+#define ADC_LOW                 0
+#define TEST_NUM                8
+
+#define MINUS_UNTIL_ZERO(a, b) ( ((a) > (b)) ? ((a)-(b)): 0)
+#define TIME_REMAIN(start, now, timeout) ((start) >= (now) ? MINUS_UNTIL_ZERO((timeout), (now)-(start)) : -1)
+
 
 static void wifi_event_handler(void* arg, esp_event_base_t event_base,
                                 int32_t event_id, void* event_data)
@@ -99,19 +113,9 @@ static int event_deinit(void)
 
 TEST_CASE("adc2 work with wifi","[adc]")
 {
-    int     read_raw;
-    int     target_value;
-
     test_case_uses_tcpip();
 
-    //adc and dac init
+    //---------------------------------WiFi init-----------------------------------//
-    TEST_ESP_OK( dac_output_enable( DAC_CHANNEL_1 ));
-    TEST_ESP_OK( dac_output_enable( DAC_CHANNEL_2 ));
-    TEST_ESP_OK( dac_output_voltage( DAC_CHANNEL_1, 30 ));
-    TEST_ESP_OK( dac_output_voltage( DAC_CHANNEL_2, 60 ));
-    TEST_ESP_OK( adc2_config_channel_atten( ADC_TEST_CH1, ADC_ATTEN_0db ));
-    TEST_ESP_OK( adc2_config_channel_atten( ADC_TEST_CH2, ADC_ATTEN_0db ));
-    //init wifi
     printf("nvs init\n");
     esp_err_t r = nvs_flash_init();
     if (r == ESP_ERR_NVS_NO_FREE_PAGES || r == ESP_ERR_NVS_NEW_VERSION_FOUND) {
@@ -135,52 +139,87 @@ TEST_CASE("adc2 work with wifi","[adc]")
     TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA));
     TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config));
 
-    //test read value
+    //---------------------------------ADC init-----------------------------------//
-    TEST_ESP_OK( adc2_get_raw( ADC_TEST_CH1, ADC_TEST_WIDTH, &read_raw ));
+    int read_raw;
-    target_value = 30*ADC_TEST_RESOLUTION*3/ADC_TEST_DAC_RANGE; //3 = 3.3/1.1
+    int target_value;
-    printf("dac set: %d, adc read: %d (target_value: %d)\n", 30, read_raw, target_value );
+    gpio_num_t test_adc_io;
-    TEST_ASSERT_INT_WITHIN( ADC_TEST_ERROR, target_value, read_raw );
+    bool test_list[TEST_NUM] ={1, 1, 0, 0, 1, 0, 1, 0};
-    TEST_ESP_OK( adc2_get_raw( ADC_TEST_CH2, ADC_TEST_WIDTH, &read_raw ));
+
-    target_value = 60*ADC_TEST_RESOLUTION*3/ADC_TEST_DAC_RANGE;
+    adc2_pad_get_io_num(ADC2_CHAN1, &test_adc_io);
-    printf("dac set: %d, adc read: %d (target_value: %d)\n", 60, read_raw, target_value );
+    TEST_ESP_OK(adc2_config_channel_atten(ADC2_CHAN1, ADC_ATTEN_0db));
-    TEST_ASSERT_INT_WITHIN( ADC_TEST_ERROR, target_value, read_raw );
+    printf("test_adc_io is %d\n", test_adc_io);
+
+    //---------------------------------GPIO init-----------------------------------//
+    gpio_config_t gpio_cfg = {
+        .pin_bit_mask = BIT64(test_adc_io),
+        .mode = GPIO_MODE_OUTPUT,
+        //for powersave reasons, the GPIO should not be floating, select pullup
+        .pull_up_en = true,
+        .pull_down_en = false,
+        .intr_type = GPIO_INTR_DISABLE,
+    };
+    gpio_config(&gpio_cfg);
+
+    for (int i = 0; i < TEST_NUM; i++) {
+        TEST_ESP_OK(gpio_set_level(test_adc_io, test_list[i]));
+        target_value = test_list[i] ? ADC_HIGH : ADC_LOW;
+
+        /* ADC2 single read before WIFI start */
+        TEST_ESP_OK(adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw));
+        printf("Before WiFi starts, ADC read: %d (target_value: %d)\n", read_raw, target_value);
+        TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw);
+
+        /* ADC2 single read when WIFI is on */
+        TEST_ESP_OK(esp_wifi_start());
+    #if CONFIG_IDF_TARGET_ESP32
+        TEST_ASSERT_EQUAL(adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw), ESP_ERR_TIMEOUT);
+    #elif SOC_ADC_ARBITER_SUPPORTED
+        esp_err_t ret;
+        int32_t start = xTaskGetTickCount();
+        int32_t now;
+        int32_t remain_wait_ms = 0;
+        int32_t timeout = pdMS_TO_TICKS(10);
+
+        do {
+            now = xTaskGetTickCount();
+            remain_wait_ms = pdTICKS_TO_MS(TIME_REMAIN(start, now, timeout));
+
+            ret = adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw);
+            if (ret == ESP_OK) {
+                printf("When WiFi is ON, ADC read: %d (target_value: %d)\n", read_raw, target_value);
+                TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw);
+                break;
+            } else if (ret == ESP_ERR_INVALID_STATE) {
+                continue;
+            } else {
+                TEST_ESP_OK(ret);
+            }
+        } while (remain_wait_ms);
+    #endif
+
+        /* ADC2 single read after WIFI is off */
+        TEST_ESP_OK(esp_wifi_stop());
+        TEST_ESP_OK(adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw));
+        printf("After WiFi is OFF, ADC read: %d (target_value: %d)\n", read_raw, target_value);
+        TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw);
+    }
 
-    //now start wifi
-    printf("wifi start...\n");
-    TEST_ESP_OK(esp_wifi_start());
-    //test reading during wifi on
-#ifdef CONFIG_IDF_TARGET_ESP32
-    TEST_ASSERT_EQUAL( adc2_get_raw( ADC_TEST_CH1, ADC_TEST_WIDTH, &read_raw ), ESP_ERR_TIMEOUT );
-    TEST_ASSERT_EQUAL( adc2_get_raw( ADC_TEST_CH2, ADC_TEST_WIDTH, &read_raw ), ESP_ERR_TIMEOUT );
-#elif defined CONFIG_IDF_TARGET_ESP32S2
-    TEST_ASSERT_EQUAL( adc2_get_raw( ADC_TEST_CH1, ADC_TEST_WIDTH, &read_raw ), ESP_OK );
-    TEST_ASSERT_EQUAL( adc2_get_raw( ADC_TEST_CH2, ADC_TEST_WIDTH, &read_raw ), ESP_OK );
-#endif
-    //wifi stop again
-    printf("wifi stop...\n");
-    TEST_ESP_OK( esp_wifi_stop() );
     TEST_ESP_OK(esp_wifi_deinit());
     event_deinit();
     nvs_flash_deinit();
 
-    //test read value
-    TEST_ESP_OK( adc2_get_raw( ADC_TEST_CH1, ADC_TEST_WIDTH, &read_raw ));
-    target_value = 30*ADC_TEST_RESOLUTION*3/ADC_TEST_DAC_RANGE; //3 = 3.3/1.1
-    printf("dac set: %d, adc read: %d (target_value: %d)\n", 30, read_raw, target_value );
-    TEST_ASSERT_INT_WITHIN( ADC_TEST_ERROR, target_value, read_raw );
-    TEST_ESP_OK( adc2_get_raw( ADC_TEST_CH2, ADC_TEST_WIDTH, &read_raw ));
-    target_value = 60*ADC_TEST_RESOLUTION*3/ADC_TEST_DAC_RANGE;
-    printf("dac set: %d, adc read: %d (target_value: %d)\n", 60, read_raw, target_value );
-    TEST_ASSERT_INT_WITHIN( ADC_TEST_ERROR, target_value, read_raw );
-
-    printf("test passed...\n");
-
     TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop.");
 }
 
-#endif
+#endif  //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32S3)
+
 
 #ifdef CONFIG_IDF_TARGET_ESP32
+
+#define ADC1_CHANNEL_4_IO      (32)
+#define SAMPLE_RATE            (36000)
+#define SAMPLE_BITS            (16)
+
 static void i2s_adc_init(void)
 {
     i2s_config_t i2s_config = {

components/hal/adc_hal.c

@@ -44,6 +44,14 @@ void adc_hal_init(void)
     adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
 }
 
+#if SOC_ADC_ARBITER_SUPPORTED
+void adc_hal_arbiter_config(adc_arbiter_t *config)
+{
+    adc_ll_set_arbiter_work_mode(config->mode);
+    adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
+}
+#endif
+
 /*---------------------------------------------------------------
                     ADC calibration setting
 ---------------------------------------------------------------*/
@@ -339,6 +347,7 @@ static void adc_hal_onetime_start(void)
     adc_ll_onetime_start(false);
     esp_rom_delay_us(delay);
     adc_ll_onetime_start(true);
+
     //No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
 }
 

components/hal/esp32c3/adc_hal.c

@@ -142,24 +142,3 @@ void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable)
     s_monitor_enabled[mon_idx] = enable;
     update_monitor(mon_idx);
 }
-
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to `adc_arbiter_t`.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config)
-{
-    adc_ll_set_arbiter_work_mode(config->mode);
-    adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
-}

components/hal/esp32c3/include/hal/adc_hal.h

@@ -97,23 +97,6 @@ void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t mon_idx, adc_digi_monito
  */
 void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable);
 
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to `adc_arbiter_t`.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config);
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s2/adc_hal.c

@@ -122,24 +122,3 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
     adc_ll_digi_monitor_set_mode(adc_n, config->mode);
     adc_ll_digi_monitor_set_thres(adc_n, config->threshold);
 }
-
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to ``adc_arbiter_t``.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config)
-{
-    adc_ll_set_arbiter_work_mode(config->mode);
-    adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
-}

components/hal/esp32s2/include/hal/adc_hal.h

@@ -197,23 +197,6 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
  */
 #define adc_hal_rtc_reset() adc_ll_rtc_reset()
 
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to ``adc_arbiter_t``.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config);
-
 #ifdef __cplusplus
 }
 #endif

components/hal/include/hal/adc_hal.h

@@ -114,6 +114,22 @@ void adc_hal_init(void);
 #define adc_hal_amp_disable() adc_ll_amp_disable()
 #endif
 
+#if SOC_ADC_ARBITER_SUPPORTED
+//No ADC2 controller arbiter on ESP32
+/**
+ * Config ADC2 module arbiter.
+ * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
+ * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
+ *
+ * @note Only ADC2 support arbiter.
+ * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
+ * @note Default priority: Wi-Fi > RTC > Digital;
+ *
+ * @param config Refer to ``adc_arbiter_t``.
+ */
+void adc_hal_arbiter_config(adc_arbiter_t *config);
+#endif  //#if SOC_ADC_ARBITER_SUPPORTED
+
 /*---------------------------------------------------------------
                     PWDET(Power detect) controller setting
 ---------------------------------------------------------------*/

components/soc/esp32c3/include/soc/soc_caps.h

@@ -44,6 +44,7 @@
 //F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
 #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+#define SOC_ADC_ARBITER_SUPPORTED               1
 
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (1)

components/soc/esp32s2/include/soc/soc_caps.h

@@ -77,6 +77,7 @@
  */
 #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
 #define SOC_ADC_SUPPORT_RTC_CTRL        1
+#define SOC_ADC_ARBITER_SUPPORTED       1
 
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
 #define SOC_BROWNOUT_RESET_SUPPORTED 1

components/soc/esp32s3/include/soc/soc_caps.h

@@ -34,6 +34,7 @@
 #define SOC_ADC_MAX_CHANNEL_NUM         (10)
 #define SOC_ADC_MAX_BITWIDTH            (12)
 #define SOC_ADC_SUPPORT_RTC_CTRL        (1)
+#define SOC_ADC_ARBITER_SUPPORTED       (1)
 
 
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/