diff --git a/components/bootloader_support/src/bootloader_clock.c b/components/bootloader_support/src/bootloader_clock.c
index 0ba723f897..e5e3a6c559 100644
--- a/components/bootloader_support/src/bootloader_clock.c
+++ b/components/bootloader_support/src/bootloader_clock.c
@@ -38,7 +38,7 @@ void bootloader_clock_configure()
      */
     uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
     if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
-            DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == 2) {
+            DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
         cpu_freq = RTC_CPU_FREQ_240M;
     }
 
diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h
index 6c23dfe639..9cc3320b39 100644
--- a/components/soc/esp32/include/soc/dport_reg.h
+++ b/components/soc/esp32/include/soc/dport_reg.h
@@ -179,6 +179,9 @@
 #define DPORT_CPUPERIOD_SEL_M  ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
 #define DPORT_CPUPERIOD_SEL_V  0x3
 #define DPORT_CPUPERIOD_SEL_S  0
+#define DPORT_CPUPERIOD_SEL_80		0
+#define DPORT_CPUPERIOD_SEL_160		1
+#define DPORT_CPUPERIOD_SEL_240		2
 
 #define DPORT_PRO_CACHE_CTRL_REG          (DR_REG_DPORT_BASE + 0x040)
 /* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */
diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c
index 5fe05464c4..329ea169c4 100644
--- a/components/soc/esp32/rtc_clk.c
+++ b/components/soc/esp32/rtc_clk.c
@@ -425,15 +425,15 @@ static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq)
 
     if (cpu_freq == RTC_CPU_FREQ_80M) {
         REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
-        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0);
+        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL_80);
         freq = 80;
     } else if (cpu_freq == RTC_CPU_FREQ_160M) {
         REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
-        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 1);
+        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL_160);
         freq = 160;
     } else if (cpu_freq == RTC_CPU_FREQ_240M) {
         REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
-        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 2);
+        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL_240);
         freq = 240;
     }
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
@@ -500,15 +500,15 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
                 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
         rtc_clk_bbpll_set(xtal_freq, cpu_freq);
         if (cpu_freq == RTC_CPU_FREQ_80M) {
-            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
+            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, DPORT_CPUPERIOD_SEL_80);
             ets_update_cpu_frequency(80);
             s_cur_pll = RTC_PLL_320M;
         } else if (cpu_freq == RTC_CPU_FREQ_160M) {
-            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
+            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, DPORT_CPUPERIOD_SEL_160);
             ets_update_cpu_frequency(160);
             s_cur_pll = RTC_PLL_320M;
         } else if (cpu_freq == RTC_CPU_FREQ_240M) {
-            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
+            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, DPORT_CPUPERIOD_SEL_240);
             ets_update_cpu_frequency(240);
             s_cur_pll = RTC_PLL_480M;
         }
@@ -536,11 +536,11 @@ rtc_cpu_freq_t rtc_clk_cpu_freq_get()
         }
         case RTC_CNTL_SOC_CLK_SEL_PLL: {
             uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
-            if (cpuperiod_sel == 0) {
+            if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
                 return RTC_CPU_FREQ_80M;
-            } else if (cpuperiod_sel == 1) {
+            } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
                 return RTC_CPU_FREQ_160M;
-            } else if (cpuperiod_sel == 2) {
+            } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
                 return RTC_CPU_FREQ_240M;
             } else {
                 assert(false && "unsupported frequency");