diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk.c b/components/esp_hw_support/port/esp32h4/rtc_clk.c index 586e000ea1..dc76bf8376 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h4/rtc_clk.c @@ -16,6 +16,7 @@ #include "esp_hw_log.h" #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" +#include "hal/gpio_ll.h" #include "hal/regi2c_ctrl_ll.h" #include "soc/io_mux_reg.h" #include "soc/lp_aon_reg.h" @@ -50,14 +51,14 @@ void rtc_clk_32k_enable(bool enable) void rtc_clk_32k_enable_external(void) { // EXT_OSC_SLOW_GPIO_NUM == GPIO_NUM_0 - PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG); + gpio_ll_input_enable(&GPIO, GPIO_NUM_0); REG_SET_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM)); clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL); } void rtc_clk_32k_disable_external(void) { - PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG); + gpio_ll_input_disable(&GPIO, GPIO_NUM_0); REG_CLR_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM)); clk_ll_xtal32k_disable(); } @@ -155,7 +156,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) regi2c_ctrl_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ - while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + while (!regi2c_ctrl_ll_bbpll_calibration_is_done()); /* BBPLL CALIBRATION STOP */ regi2c_ctrl_ll_bbpll_calibration_stop(); diff --git a/components/esp_rom/esp32h4/include/esp32h4/rom/gpio.h b/components/esp_rom/esp32h4/include/esp32h4/rom/gpio.h index eb647fb3f1..a4e36af30a 100644 --- a/components/esp_rom/esp32h4/include/esp32h4/rom/gpio.h +++ b/components/esp_rom/esp32h4/include/esp32h4/rom/gpio.h @@ -10,8 +10,6 @@ #include #include "soc/gpio_reg.h" -//TODO: [ESP32H4] IDF-12390 inherit from verification branch, need check - #ifdef __cplusplus extern "C" { #endif @@ -27,9 +25,6 @@ extern "C" { #define GPIO_REG_READ(reg) READ_PERI_REG(reg) #define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) -#define GPIO_FUNC_ZERO 0 -#define GPIO_FUNC_GPIO 1 - #define GPIO_OUTPUT_SET(gpio_no, bit_value) gpio_set_output_level(gpio_no, bit_value) #define GPIO_DIS_OUTPUT(gpio_no) gpio_output_disable(gpio_no) #define GPIO_INPUT_GET(gpio_no) gpio_get_input_level(gpio_no) @@ -55,8 +50,8 @@ uint32_t gpio_get_input_level(uint32_t gpio_num); * @brief set gpio input to a signal, one gpio can input to several signals. * * @param uint32_t gpio_num : gpio number - * gpio == GPIO_NUM_IN_FORCE_0, input 0 to signal - * gpio == GPIO_NUM_IN_FORCE_1, input 1 to signal + * gpio == GPIO_MATRIX_CONST_ZERO_INPUT, input 0 to signal + * gpio == GPIO_MATRIX_CONST_ONE_INPUT, input 1 to signal * * @param uint32_t signal_idx : signal index. * diff --git a/components/hal/esp32h4/include/hal/gpio_ll.h b/components/hal/esp32h4/include/hal/gpio_ll.h index 6add0f6d4b..01a8346f8d 100644 --- a/components/hal/esp32h4/include/hal/gpio_ll.h +++ b/components/hal/esp32h4/include/hal/gpio_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE + * The LL layer for ESP32-H4 GPIO register operations * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md ******************************************************************************/ -// The LL layer for ESP32-H4 GPIO register operations - #pragma once #include @@ -22,25 +20,21 @@ #include "soc/lp_aon_struct.h" #include "soc/pmu_struct.h" #include "soc/io_mux_struct.h" -#include "soc/usb_serial_jtag_reg.h" +#include "soc/usb_serial_jtag_struct.h" #include "soc/pcr_struct.h" #include "soc/clk_tree_defs.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" -//TODO: [ESP32H4] IDF-12390 inherited from verification branch, need check - #ifdef __cplusplus extern "C" { #endif // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) - #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) - #define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE /** @@ -52,10 +46,12 @@ extern "C" { */ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, gpio_io_config_t *io_config) { + uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32); + uint32_t bit_mask = 1 << bit_shift; io_config->pu = IO_MUX.gpio[gpio_num].fun_wpu; io_config->pd = IO_MUX.gpio[gpio_num].fun_wpd; io_config->ie = IO_MUX.gpio[gpio_num].fun_ie; - io_config->oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num; + io_config->oe = (((gpio_num < 32) ? hw->enable.val : hw->enable1.val) & bit_mask) >> bit_shift; io_config->oe_ctrl_by_periph = !(hw->funcn_out_sel_cfg[gpio_num].oe_sel); io_config->oe_inv = hw->funcn_out_sel_cfg[gpio_num].oe_inv_sel; io_config->od = hw->pinn[gpio_num].pinn_pad_driver; @@ -73,7 +69,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, gpio */ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) { - REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); + IO_MUX.gpio[gpio_num].fun_wpu = 1; } /** @@ -85,7 +81,16 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + // Note that esp32h4 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin + // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. + // TODO: read the specific efuse with efuse_ll.h + if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { + USB_SERIAL_JTAG.serial_jtag_conf0.serial_jtag_pad_pull_override = 1; + USB_SERIAL_JTAG.serial_jtag_conf0.serial_jtag_dp_pullup = 0; + } + IO_MUX.gpio[gpio_num].fun_wpu = 0; } /** @@ -96,7 +101,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) { - REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); + IO_MUX.gpio[gpio_num].fun_wpd = 1; } /** @@ -108,16 +113,7 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value - // USB DP pin is default to PU enabled - // Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin - // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. - // TODO: read the specific efuse with efuse_ll.h - // if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { - // SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); - // CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); - // } - REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); + IO_MUX.gpio[gpio_num].fun_wpd = 0; } /** @@ -218,7 +214,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].fun_ie = 0; } /** @@ -229,7 +225,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].fun_ie = 1; } /** @@ -240,7 +236,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].filter_en = 1; } /** @@ -251,7 +247,7 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].filter_en = 0; } /** @@ -268,9 +264,6 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) } else { hw->enable1_w1tc.enable1_w1tc = (0x1 << (gpio_num - 32)); } - // Ensure no other output signal is routed via GPIO matrix to this pin - REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), - SIG_GPIO_OUT_IDX); } /** @@ -320,11 +313,10 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: [ESP32H4] - // gpio_func_out_sel_cfg_reg_t reg = { - // .out_sel = SIG_GPIO_OUT_IDX, - // }; - // hw->func_out_sel_cfg[gpio_num].val = reg.val; + gpio_funcn_out_sel_cfg_reg_t reg = { + .out_sel = SIG_GPIO_OUT_IDX, + }; + hw->funcn_out_sel_cfg[gpio_num].val = reg.val; } /** @@ -339,15 +331,15 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t { if (level) { if (gpio_num < 32) { - hw->out_w1ts.out_w1ts = (1 << gpio_num); + hw->out_w1ts.val = (1 << gpio_num); } else { - hw->out1_w1ts.out1_w1ts = (1 << (gpio_num - 32)); + hw->out1_w1ts.val = (1 << (gpio_num - 32)); } } else { if (gpio_num < 32) { - hw->out_w1tc.out_w1tc = (1 << gpio_num); + hw->out_w1tc.val = (1 << gpio_num); } else { - hw->out1_w1tc.out1_w1tc = (1 << (gpio_num - 32)); + hw->out1_w1tc.val = (1 << (gpio_num - 32)); } } } @@ -405,7 +397,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength) { - SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S); + IO_MUX.gpio[gpio_num].fun_drv = strength; } /** @@ -417,7 +409,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength) { - *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S); + *strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv); } /** @@ -428,7 +420,11 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) { - LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num]; + if (gpio_num < 32) { + LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num]; + } else { + LP_AON.gpio_hold1.gpio_hold1 |= GPIO_HOLD_MASK[gpio_num]; + } } /** @@ -439,7 +435,11 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) { - LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num]; + if (gpio_num < 32) { + LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num]; + } else { + LP_AON.gpio_hold1.gpio_hold1 &= ~GPIO_HOLD_MASK[gpio_num]; + } } /** @@ -457,7 +457,11 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) { - return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num)); + if (gpio_num < 32) { + return !!(LP_AON.gpio_hold0.gpio_hold0 & GPIO_HOLD_MASK[gpio_num]); + } else { + return !!(LP_AON.gpio_hold1.gpio_hold1 & GPIO_HOLD_MASK[gpio_num]); + } } /** @@ -483,11 +487,11 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal __attribute__((always_inline)) static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { - // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function - // if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { - // CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); - // } - PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); + // Disable USB Serial JTAG if USB pins needs to select an IOMUX function + if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { + USB_SERIAL_JTAG.serial_jtag_conf0.serial_jtag_usb_pad_enable = 0; + } + IO_MUX.gpio[gpio_num].mcu_sel = func; } /** @@ -513,10 +517,13 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) { switch (src) { case SOC_MOD_CLK_XTAL: - PCR.iomux_clk_conf.iomux_func_clk_sel = 3; + PCR.iomux_clk_conf.iomux_func_clk_sel = 0; + break; + case SOC_MOD_CLK_RC_FAST: + PCR.iomux_clk_conf.iomux_func_clk_sel = 1; break; case SOC_MOD_CLK_PLL_F48M: - PCR.iomux_clk_conf.iomux_func_clk_sel = 1; + PCR.iomux_clk_conf.iomux_func_clk_sel = 2; break; default: // Unsupported IO_MUX clock source @@ -536,30 +543,32 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) */ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx) { - uint32_t val = REG_GET_BIT(GPIO_FUNC0_IN_SEL_CFG_REG + in_sig_idx * 4, GPIO_SIG0_IN_SEL); - return (val ? val : -1); + gpio_func_in_sel_cfg_reg_t reg = { + .val = hw->func_in_sel_cfg[in_sig_idx].val, + }; + return (reg.sig_in_sel ? reg.func_in_sel : -1); } /** - * @brief Force hold digital io pad. + * @brief Force hold all digital(VDDPST2) and lp(VDDPST1) io pads. * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. */ static inline void gpio_ll_force_hold_all(void) { - // WT flag, it gets self-cleared after the configuration is done - // TODO: [ESP32H4] IDF- - abort(); + // WT flags, they get self-cleared after the configuration is done + PMU.imm.pad_hold_all.tie_high_hp_pad_hold_all = 1; + PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1; } /** - * @brief Force unhold digital io pad. + * @brief Force unhold all digital(VDDPST2) and lp(VDDPST1) io pads. * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. */ static inline void gpio_ll_force_unhold_all(void) { - // WT flag, it gets self-cleared after the configuration is done - // TODO: [ESP32H4] IDF- - abort(); + // WT flags, they get self-cleared after the configuration is done + PMU.imm.pad_hold_all.tie_low_hp_pad_hold_all = 1; + PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1; } /** @@ -571,7 +580,7 @@ static inline void gpio_ll_force_unhold_all(void) __attribute__((always_inline)) static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].slp_sel = 1; } /** @@ -584,7 +593,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].slp_sel = 0; } /** @@ -596,7 +605,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_wpu = 0; } /** @@ -608,7 +617,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_wpu = 1; } /** @@ -620,7 +629,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_wpd = 1; } /** @@ -632,7 +641,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_wpd = 0; } /** @@ -644,7 +653,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_ie = 0; } /** @@ -656,7 +665,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num __attribute__((always_inline)) static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_ie = 1; } /** @@ -668,7 +677,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_oe = 0; } /** @@ -680,7 +689,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu __attribute__((always_inline)) static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IO_MUX.gpio[gpio_num].mcu_oe = 1; } #ifdef __cplusplus diff --git a/components/soc/esp32h4/gpio_periph.c b/components/soc/esp32h4/gpio_periph.c index e69de29bb2..29ad93e599 100644 --- a/components/soc/esp32h4/gpio_periph.c +++ b/components/soc/esp32h4/gpio_periph.c @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_periph.h" + +const uint32_t GPIO_HOLD_MASK[] = { + BIT(0), //GPIO0 //LP_AON_GPIO_HOLD0_REG + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(6), //GPIO6 + BIT(7), //GPIO7 + BIT(8), //GPIO8 + BIT(9), //GPIO9 + BIT(10), //GPIO10 + BIT(11), //GPIO11 + BIT(12), //GPIO12 + BIT(13), //GPIO13 + BIT(14), //GPIO14 + BIT(15), //GPIO15 + BIT(16), //GPIO16 + BIT(17), //GPIO17 + BIT(18), //GPIO18 + BIT(19), //GPIO19 + BIT(20), //GPIO20 + BIT(21), //GPIO21 + BIT(22), //GPIO22 + BIT(23), //GPIO23 + BIT(24), //GPIO24 + BIT(25), //GPIO25 + BIT(26), //GPIO26 + BIT(27), //GPIO27 + BIT(28), //GPIO28 + BIT(29), //GPIO29 + BIT(30), //GPIO30 + BIT(31), //GPIO31 + BIT(0), //GPIO32 //LP_AON_GPIO_HOLD1_REG + BIT(1), //GPIO33 + BIT(2), //GPIO34 + BIT(3), //GPIO35 + BIT(4), //GPIO36 + BIT(5), //GPIO37 + BIT(6), //GPIO38 + BIT(7), //GPIO39 +}; + +_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index bb5f06f3c7..245989cf7b 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -183,14 +183,6 @@ config SOC_GPIO_PIN_COUNT int default 40 -config SOC_GPIO_SUPPORT_RTC_INDEPENDENT - bool - default y - -config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP - bool - default y - config SOC_GPIO_IN_RANGE_MAX int default 39 @@ -199,14 +191,6 @@ config SOC_GPIO_OUT_RANGE_MAX int default 39 -config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK - int - default 0 - -config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK - hex - default 0x000000FFFFFFFFC0 - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32h4/include/soc/adc_channel.h b/components/soc/esp32h4/include/soc/adc_channel.h index 95b431d090..69060742f2 100644 --- a/components/soc/esp32h4/include/soc/adc_channel.h +++ b/components/soc/esp32h4/include/soc/adc_channel.h @@ -5,3 +5,18 @@ */ #pragma once + +#define ADC1_GPIO28_CHANNEL 0 +#define ADC1_CHANNEL_0_GPIO_NUM 28 + +#define ADC1_GPIO29_CHANNEL 1 +#define ADC1_CHANNEL_1_GPIO_NUM 29 + +#define ADC1_GPIO30_CHANNEL 2 +#define ADC1_CHANNEL_2_GPIO_NUM 30 + +#define ADC1_GPIO31_CHANNEL 3 +#define ADC1_CHANNEL_3_GPIO_NUM 31 + +#define ADC1_GPIO32_CHANNEL 4 +#define ADC1_CHANNEL_4_GPIO_NUM 32 diff --git a/components/soc/esp32h4/include/soc/gpio_pins.h b/components/soc/esp32h4/include/soc/gpio_pins.h index 42ac6c1c0d..44a3d6442f 100644 --- a/components/soc/esp32h4/include/soc/gpio_pins.h +++ b/components/soc/esp32h4/include/soc/gpio_pins.h @@ -10,10 +10,9 @@ extern "C" { #endif -// TODO: [ESP32H4] IDF-12390 inherit from verify code, need check - -#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) -#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C) +#define GPIO_MATRIX_CONST_ONE_INPUT (0x40) +#define GPIO_MATRIX_INVALID (0x50) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x60) #ifdef __cplusplus } diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 54813851d2..45cc24756f 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -194,8 +194,13 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-H4 has 1 GPIO peripheral -#define SOC_GPIO_PORT 1U -#define SOC_GPIO_PIN_COUNT 40 +#define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 40 +#define SOC_GPIO_IN_RANGE_MAX 39 +#define SOC_GPIO_OUT_RANGE_MAX 39 +#define SOC_GPIO_VALID_GPIO_MASK ((1ULL< *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. + +The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions. + +.. list-table:: + :header-rows: 1 + :widths: 8 12 12 20 + + * - GPIO + - Analog Function + - LP GPIO + - Comments + + * - GPIO0 + - + - LP_GPIO0 + - + + * - GPIO1 + - + - LP_GPIO1 + - + + * - GPIO2 + - + - LP_GPIO2 + - + + * - GPIO3 + - + - LP_GPIO3 + - + + * - GPIO4 + - + - LP_GPIO4 + - + + * - GPIO5 + - + - LP_GPIO5 + - + + * - GPIO6 + - + - + - SPI0/1 + + * - GPIO7 + - + - + - SPI0/1 + + * - GPIO8 + - + - + - SPI0/1 + + * - GPIO9 + - + - + - SPI0/1 + + * - GPIO10 + - + - + - SPI0/1 + + * - GPIO11 + - + - + - SPI0/1 + + * - GPIO12 + - + - + - SPI0/1 + + * - GPIO13 + - + - + - USB-JTAG + + * - GPIO14 + - + - + - USB-JTAG + + * - GPIO15 + - + - + - + + * - GPIO16 + - + - + - + + * - GPIO17 + - + - + - Strapping pin + + * - GPIO18 + - + - + - + + * - GPIO19 + - + - + - + + * - GPIO20 + - + - + - + + * - GPIO21 + - + - + - + + * - GPIO22 + - + - + - + + * - GPIO23 + - + - + - + + * - GPIO24 + - + - + - + + * - GPIO25 + - + - + - + + * - GPIO26 + - + - + - + + * - GPIO27 + - + - + - + + * - GPIO28 + - ADC1_CH0 + - + - + + * - GPIO29 + - ADC1_CH1 + - + - + + * - GPIO30 + - ADC1_CH2 + - + - + + * - GPIO31 + - ADC1_CH3 + - + - + + * - GPIO32 + - ADC1_CH4 + - + - + + * - GPIO33 + - + - + - + + * - GPIO34 + - + - + - + + * - GPIO35 + - + - + - + + * - GPIO36 + - + - + - Strapping pin + + * - GPIO37 + - + - + - Strapping pin + + * - GPIO38 + - + - + - + + * - GPIO39 + - + - + - .. note:: - To be updated + - Strapping pin: GPIO17, GPIO36, and GPIO37 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__. + - SPI0/1: GPIO6 ~ GPIO12 are usually used for SPI flash and PSRAM. These pins are not recommended for other uses. + - USB-JTAG: GPIO13 and GPIO14 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled. --- diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc index 433eb247c0..0942357c23 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc +++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc @@ -23,8 +23,8 @@ - 注释 * - GPIO0 - - LP_GPIO0 - + - LP_GPIO0 - * - GPIO1 diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32h4.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32h4.inc index 3796a2600b..83fb3d17d4 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio/esp32h4.inc +++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32h4.inc @@ -9,10 +9,223 @@ .. gpio-summary - To be updated +{IDF_TARGET_NAME} 芯片具有 40 个物理 GPIO 管脚（GPIO0 ~ GPIO39）。每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。 + +下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。 + +.. list-table:: + :header-rows: 1 + :widths: 8 12 12 20 + + * - GPIO + - 模拟功能 + - LP GPIO + - 注释 + + * - GPIO0 + - + - LP_GPIO0 + - + + * - GPIO1 + - + - LP_GPIO1 + - + + * - GPIO2 + - + - LP_GPIO2 + - + + * - GPIO3 + - + - LP_GPIO3 + - + + * - GPIO4 + - + - LP_GPIO4 + - + + * - GPIO5 + - + - LP_GPIO5 + - + + * - GPIO6 + - + - + - SPI0/1 + + * - GPIO7 + - + - + - SPI0/1 + + * - GPIO8 + - + - + - SPI0/1 + + * - GPIO9 + - + - + - SPI0/1 + + * - GPIO10 + - + - + - SPI0/1 + + * - GPIO11 + - + - + - SPI0/1 + + * - GPIO12 + - + - + - SPI0/1 + + * - GPIO13 + - + - + - USB-JTAG + + * - GPIO14 + - + - + - USB-JTAG + + * - GPIO15 + - + - + - + + * - GPIO16 + - + - + - + + * - GPIO17 + - + - + - Strapping 管脚 + + * - GPIO18 + - + - + - + + * - GPIO19 + - + - + - + + * - GPIO20 + - + - + - + + * - GPIO21 + - + - + - + + * - GPIO22 + - + - + - + + * - GPIO23 + - + - + - + + * - GPIO24 + - + - + - + + * - GPIO25 + - + - + - + + * - GPIO26 + - + - + - + + * - GPIO27 + - + - + - + + * - GPIO28 + - ADC1_CH0 + - + - + + * - GPIO29 + - ADC1_CH1 + - + - + + * - GPIO30 + - ADC1_CH2 + - + - + + * - GPIO31 + - ADC1_CH3 + - + - + + * - GPIO32 + - ADC1_CH4 + - + - + + * - GPIO33 + - + - + - + + * - GPIO34 + - + - + - + + * - GPIO35 + - + - + - + + * - GPIO36 + - + - + - Strapping 管脚 + + * - GPIO37 + - + - + - Strapping 管脚 + + * - GPIO38 + - + - + - + + * - GPIO39 + - + - + - .. note:: - To be updated + - Strapping 管脚：GPIO17、GPIO36 和 GPIO37 是 Strapping 管脚。更多信息请参考 `{IDF_TARGET_NAME} 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。 + - SPI0/1：GPIO6 ~ GPIO12 通常用于 SPI flash 和 PSRAM，不推荐用于其他用途。 + - USB-JTAG：GPIO13 和 GPIO14 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。 ---