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feat(esp_tee): Protect the ECC peripheral from REE access

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This commit is contained in:
Laukik Hase
2025-04-11 11:41:09 +05:30
parent fc4802c0d6
commit 4a4d63d36e
16 changed files with 90 additions and 24 deletions
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components/esp_tee/subproject/main/core/esp_secure_services.c
+21
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@@ -29,6 +29,7 @@
#include "esp_hmac.h"
#include "esp_ds.h"
#include "esp_crypto_periph_clk.h"
#include "ecc_impl.h"
#include "esp_tee.h"
#include "esp_tee_memory_utils.h"
@@ -444,6 +445,26 @@ void _ss_esp_crypto_mpi_enable_periph_clk(bool enable)
esp_crypto_mpi_enable_periph_clk(enable);
}
/* ---------------------------------------------- ECC ------------------------------------------------- */
int _ss_esp_ecc_point_multiply(const ecc_point_t *point, const uint8_t *scalar, ecc_point_t *result, bool verify_first)
{
bool valid_addr = (esp_tee_ptr_in_ree((void *)result)) &&
esp_tee_ptr_in_ree((void *)((char *)result + sizeof(ecc_point_t)));
if (!valid_addr) {
return -1;
}
ESP_FAULT_ASSERT(valid_addr);
return esp_ecc_point_multiply(point, scalar, result, verify_first);
}
int _ss_esp_ecc_point_verify(const ecc_point_t *point)
{
return esp_ecc_point_verify(point);
}
/* ---------------------------------------------- OTA ------------------------------------------------- */
int _ss_esp_tee_ota_begin(void)
components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in
+2
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@@ -177,6 +177,7 @@ SECTIONS
* | SHA | text | Flash |
* | HMAC | text | Flash |
* | DS | text | Flash |
* | ECC | text | Flash |
* | BROWNOUT | text | Flash |
* | EFUSE | text | Flash |
* | LPTIMER | text | Flash |
@@ -196,6 +197,7 @@ SECTIONS
*libhal.a:sha_hal.c*(.literal .text .literal.* .text.*)
*libhal.a:hmac_hal.c*(.literal .text .literal.* .text.*)
*libhal.a:ds_hal.c*(.literal .text .literal.* .text.*)
*libhal.a:ecc_hal.c*(.literal .text .literal.* .text.*)
*libhal.a:apm_hal.c*(.literal .text .literal.* .text.*)
*libhal.a:brownout_hal.c*(.literal .text .literal.* .text.*)
*libhal.a:spi_flash_hal.c*(.literal .text .literal.* .text.*)
components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c
+5 -5
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@@ -107,7 +107,7 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = {
.filter_enable = 1,
},
/* Region 6/7: Peripherals [H/W Lock - HMAC] (RW) */
/* Protected: AES, SHA, DS, HMAC */
/* Protected: AES, SHA, ECC, DS, HMAC */
{
.regn_num = 6,
.regn_start_addr = DR_REG_ATOMIC_BASE,
@@ -118,12 +118,12 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = {
{
.regn_num = 7,
.regn_start_addr = DR_REG_RSA_BASE,
.regn_end_addr = (DR_REG_DS_BASE - 0x4),
.regn_end_addr = (DR_REG_ECC_MULT_BASE - 0x4),
.regn_pms = 0x6,
.filter_enable = 1,
},
/* Region 8/9/10: Peripherals [DS - TEE Controller & APM] (RW) */
/* Protected: AES, SHA, DS, HMAC PCR, APM, TEE Controller */
/* Region 8/9/10: Peripherals [IO_MUX - TEE Controller & APM] (RW) */
/* Protected: AES, SHA, ECC, DS and HMAC PCRs, APM, TEE Controller */
{
.regn_num = 8,
.regn_start_addr = DR_REG_IO_MUX_BASE,
@@ -134,7 +134,7 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = {
{
.regn_num = 9,
.regn_start_addr = PCR_RSA_CONF_REG,
.regn_end_addr = (PCR_DS_CONF_REG - 0x4),
.regn_end_addr = (PCR_ECC_CONF_REG - 0x4),
.regn_pms = 0x6,
.filter_enable = 1,
},
components/esp_tee/subproject/main/soc/esp32c6/esp_tee_secure_sys_cfg.c
+3
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@@ -16,6 +16,7 @@
#include "hal/sha_ll.h"
#include "hal/hmac_ll.h"
#include "hal/ds_ll.h"
#include "hal/ecc_ll.h"
#include "esp_tee.h"
#include "esp_tee_intr.h"
@@ -95,12 +96,14 @@ void esp_tee_soc_secure_sys_init(void)
esp_tee_protect_intr_src(ETS_EFUSE_INTR_SOURCE); // eFuse
esp_tee_protect_intr_src(ETS_AES_INTR_SOURCE); // AES
esp_tee_protect_intr_src(ETS_SHA_INTR_SOURCE); // SHA
esp_tee_protect_intr_src(ETS_ECC_INTR_SOURCE); // ECC
/* Disable protected crypto peripheral clocks; they will be toggled as needed when the peripheral is in use */
aes_ll_enable_bus_clock(false);
sha_ll_enable_bus_clock(false);
hmac_ll_enable_bus_clock(false);
ds_ll_enable_bus_clock(false);
ecc_ll_enable_bus_clock(false);
}
IRAM_ATTR inline void esp_tee_switch_to_ree(uint32_t ree_entry_addr)