diff --git a/components/heap/port/esp32c6/memory_layout.c b/components/heap/port/esp32c6/memory_layout.c
index e69de29bb2..ff8efbfc64 100644
--- a/components/heap/port/esp32c6/memory_layout.c
+++ b/components/heap/port/esp32c6/memory_layout.c
@@ -0,0 +1,86 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "esp_attr.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "heap_memory_layout.h"
+#include "esp_heap_caps.h"
+
+/**
+ * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
+ * Each type of memory map consists of one or more regions in the address space.
+ * Each type contains an array of prioritized capabilities.
+ * Types with later entries are only taken if earlier ones can't fulfill the memory request.
+ *
+ * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
+ * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
+ * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
+ * - Most other malloc caps only fit in one region anyway.
+ *
+ */
+const soc_memory_type_desc_t soc_memory_types[] = {
+    // Type 0: DRAM
+    { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
+    // Type 1: DRAM used for startup stacks
+    { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT,  MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
+    // Type 2: DRAM which has an alias on the I-port
+    { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
+    // Type 3: IRAM
+    { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
+    // Type 4: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM
+    { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
+};
+
+#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
+#define SOC_MEMORY_TYPE_DEFAULT 0
+#else
+#define SOC_MEMORY_TYPE_DEFAULT 2
+#endif
+
+const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
+
+/**
+ * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
+ *
+ * @note Because of requirements in the coalescing code which merges adjacent regions,
+ *       this list should always be sorted from low to high by start address.
+ *
+ */
+const soc_memory_region_t soc_memory_regions[] = {
+    { 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //Block 4,  can be remapped to ROM, can be used as trace memory
+    { 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //Block 5,  can be remapped to ROM, can be used as trace memory
+    { 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //Block 6,  can be remapped to ROM, can be used as trace memory
+    { 0x40860000, 0x20000, 1, 0x40860000}, //Block 9,  can be used as trace memory
+#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
+    { 0x50000000, 0x4000,  4, 0}, //Fast RTC memory
+#endif
+
+};
+
+const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
+
+
+extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
+
+/**
+ * Reserved memory regions.
+ * These are removed from the soc_memory_regions array when heaps are created.
+ *
+ */
+
+// Static data region. DRAM used by data+bss and possibly rodata
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
+
+// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
+
+#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
+// TODO: IDF-6019 check reserved lp mem region
+SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
+#endif
diff --git a/components/heap/port/memory_layout_utils.c b/components/heap/port/memory_layout_utils.c
index bf4c4bc9a4..1f934b50fe 100644
--- a/components/heap/port/memory_layout_utils.c
+++ b/components/heap/port/memory_layout_utils.c
@@ -8,22 +8,21 @@
 #include "sdkconfig.h"
 #include "esp_log.h"
 #include "soc/soc_memory_layout.h"
+#include "esp_rom_caps.h"
 
+#if ESP_ROM_HAS_LAYOUT_TABLE
 #ifdef CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/rom_layout.h"
-#define ROM_HAS_LAYOUT_TABLE 1
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/rom_layout.h"
-#define ROM_HAS_LAYOUT_TABLE 1
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/rom_layout.h"
-#define ROM_HAS_LAYOUT_TABLE 1
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/rom_layout.h"
-#define ROM_HAS_LAYOUT_TABLE 1
-#else
-#define ROM_HAS_LAYOUT_TABLE 0
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/rom_layout.h"
 #endif
+#endif // ESP_ROM_HAS_LAYOUT_TABLE
 
 static const char *TAG = "memory_layout";
 
@@ -38,7 +37,7 @@ static size_t s_get_num_reserved_regions(void)
 {
     size_t result = ( &soc_reserved_memory_region_end
              - &soc_reserved_memory_region_start );
-#if ROM_HAS_LAYOUT_TABLE
+#if ESP_ROM_HAS_LAYOUT_TABLE
     return result + 1; // ROM table means one entry needs to be added at runtime
 #else
     return result;
@@ -66,7 +65,7 @@ static int s_compare_reserved_regions(const void *a, const void *b)
 */
 static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t count)
 {
-#if ROM_HAS_LAYOUT_TABLE
+#if ESP_ROM_HAS_LAYOUT_TABLE
     /* Get the ROM layout to find which part of DRAM is reserved */
     const ets_rom_layout_t *layout = ets_rom_layout_p;
     reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start;