espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-05 05:34:32 +02:00
Code Issues Packages Projects Releases Wiki Activity

change(hal): move regdma related API from lp_aon_ll to pau_ll

Browse Source
This commit is contained in:
wuzhenghui
2025-06-18 21:57:03 +08:00
parent aeba99290f
commit 4a887a7b5a
9 changed files with 158 additions and 153 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
components/hal/esp32c5/include/hal/lp_aon_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -85,54 +85,6 @@ static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
} }
} }
/**
* @brief Set the maximum number of linked lists supported by REGDMA
* @param count: the maximum number of regdma link
*/
static inline void lp_aon_ll_set_regdma_link_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, branch_link_length_aon, count);
}
/**
* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
* @param count: the maximum number of loop
*/
static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_work_tout_thres_aon, count);
}
/**
* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
* registers and gets stuck on the bus, a timeout will be triggered.
* @param count: the maximum number of time
*/
static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_backup_tout_thres_aon, count);
}
/**
* @brief Set the regdma_link_addr
* @param addr: the addr of regdma_link
*/
static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, link_addr_aon, addr);
}
static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_wait_tout_thres_aon, count);
}
static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, read_interval_aon, interval);
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

51
components/hal/esp32c5/include/hal/pau_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -137,6 +137,55 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
dev->int_clr.error_int_clr = 1; dev->int_clr.error_int_clr = 1;
} }
/**
* @brief Set the maximum number of linked lists supported by REGDMA
* @param count: the maximum number of regdma link
*/
static inline void pau_ll_set_regdma_link_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, branch_link_length_aon, count);
}
/**
* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
* @param count: the maximum number of loop
*/
static inline void pau_ll_set_regdma_link_loop_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_work_tout_thres_aon, count);
}
/**
* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
* registers and gets stuck on the bus, a timeout will be triggered.
* @param count: the maximum number of time
*/
static inline void pau_ll_set_regdma_link_reg_access_tout_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_backup_tout_thres_aon, count);
}
/**
* @brief Set the regdma_link_addr
* @param addr: the addr of regdma_link
*/
static inline void pau_ll_set_regdma_link_addr(uint32_t addr)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, link_addr_aon, addr);
}
static inline void pau_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_wait_tout_thres_aon, count);
}
static inline void pau_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, read_interval_aon, interval);
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

14
components/hal/esp32c5/pau_hal.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,7 +12,7 @@
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
{ {
lp_aon_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); pau_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]);
} }
void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore) void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
@@ -59,20 +59,20 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count)
{ {
HAL_ASSERT(count > 0); HAL_ASSERT(count > 0);
lp_aon_ll_set_regdma_link_count(count - 1); pau_ll_set_regdma_link_count(count - 1);
} }
#endif #endif
void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time)
{ {
HAL_ASSERT(loop_num > 0 && time > 0); HAL_ASSERT(loop_num > 0 && time > 0);
lp_aon_ll_set_regdma_link_loop_threshold(loop_num); pau_ll_set_regdma_link_loop_threshold(loop_num);
lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time); pau_ll_set_regdma_link_reg_access_tout_threshold(time);
} }
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{ {
HAL_ASSERT(count > 0 && interval > 0); HAL_ASSERT(count > 0 && interval > 0);
lp_aon_ll_set_regdma_link_wait_retry_count(count); pau_ll_set_regdma_link_wait_retry_count(count);
lp_aon_ll_set_regdma_link_wait_read_interval(interval); pau_ll_set_regdma_link_wait_read_interval(interval);
} }

48
components/hal/esp32h21/include/hal/lp_aon_ll.h
View File

@@ -85,54 +85,6 @@ static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
} }
} }
/**
* @brief Set the maximum number of linked lists supported by REGDMA
* @param count: the maximum number of regdma link
*/
static inline void lp_aon_ll_set_regdma_link_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count);
}
/**
* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
* @param count: the maximum number of loop
*/
static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count);
}
/**
* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
* registers and gets stuck on the bus, a timeout will be triggered.
* @param count: the maximum number of time
*/
static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count);
}
/**
* @brief Set the regdma_link_addr
* @param addr: the addr of regdma_link
*/
static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr);
}
static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count);
}
static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval);
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

48
components/hal/esp32h21/include/hal/pau_ll.h
View File

@@ -137,6 +137,54 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
dev->int_clr.error_int_clr = 1; dev->int_clr.error_int_clr = 1;
} }
/**
* @brief Set the maximum number of linked lists supported by REGDMA
* @param count: the maximum number of regdma link
*/
static inline void pau_ll_set_regdma_link_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count);
}
/**
* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
* @param count: the maximum number of loop
*/
static inline void pau_ll_set_regdma_link_loop_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count);
}
/**
* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
* registers and gets stuck on the bus, a timeout will be triggered.
* @param count: the maximum number of time
*/
static inline void pau_ll_set_regdma_link_reg_access_tout_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count);
}
/**
* @brief Set the regdma_link_addr
* @param addr: the addr of regdma_link
*/
static inline void pau_ll_set_regdma_link_addr(uint32_t addr)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr);
}
static inline void pau_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count);
}
static inline void pau_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval);
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

12
components/hal/esp32h21/pau_hal.c
View File

@@ -16,7 +16,7 @@
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
{ {
lp_aon_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); pau_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]);
} }
void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore) void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
@@ -63,20 +63,20 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count)
{ {
HAL_ASSERT(count > 0); HAL_ASSERT(count > 0);
lp_aon_ll_set_regdma_link_count(count - 1); pau_ll_set_regdma_link_count(count - 1);
} }
#endif #endif
void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time)
{ {
HAL_ASSERT(loop_num > 0 && time > 0); HAL_ASSERT(loop_num > 0 && time > 0);
lp_aon_ll_set_regdma_link_loop_threshold(loop_num); pau_ll_set_regdma_link_loop_threshold(loop_num);
lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time); pau_ll_set_regdma_link_reg_access_tout_threshold(time);
} }
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{ {
HAL_ASSERT(count > 0 && interval > 0); HAL_ASSERT(count > 0 && interval > 0);
lp_aon_ll_set_regdma_link_wait_retry_count(count); pau_ll_set_regdma_link_wait_retry_count(count);
lp_aon_ll_set_regdma_link_wait_read_interval(interval); pau_ll_set_regdma_link_wait_read_interval(interval);
} }

37
components/hal/esp32h4/include/hal/lp_aon_ll.h
View File

@@ -96,46 +96,11 @@ static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
* @brief Set the maximum number of linked lists supported by REGDMA * @brief Set the maximum number of linked lists supported by REGDMA
* @param count: the maximum number of regdma link * @param count: the maximum number of regdma link
*/ */
static inline void lp_aon_ll_set_regdma_link_count(int count) static inline void pau_ll_set_regdma_link_count(int count)
{ {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count);
} }
static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr);
}
/**
* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
* @param count: the maximum number of loop
*/
static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count);
}
/**
* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
* registers and gets stuck on the bus, a timeout will be triggered.
* @param count: the maximum number of time
*/
static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count);
}
static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count);
}
static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval);
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

39
components/hal/esp32h4/include/hal/pau_ll.h
View File

@@ -188,6 +188,45 @@ static inline bool pau_ll_is_busy(pau_dev_t *dev)
return dev->regdma_conf.paudma_busy; return dev->regdma_conf.paudma_busy;
} }
/**
* @brief Set the regdma_link_addr
* @param addr: the addr of regdma_link
*/
static inline void pau_ll_set_regdma_link_addr(uint32_t addr)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr);
}
/**
* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
* @param count: the maximum number of loop
*/
static inline void pau_ll_set_regdma_link_loop_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count);
}
/**
* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
* registers and gets stuck on the bus, a timeout will be triggered.
* @param count: the maximum number of time
*/
static inline void pau_ll_set_regdma_link_reg_access_tout_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count);
}
static inline void pau_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count);
}
static inline void pau_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval);
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

12
components/hal/esp32h4/pau_hal.c
View File

@@ -14,7 +14,7 @@
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
{ {
lp_aon_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); pau_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]);
} }
void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore) void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore)
@@ -44,20 +44,20 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count)
{ {
HAL_ASSERT(count > 0); HAL_ASSERT(count > 0);
lp_aon_ll_set_regdma_link_count(count - 1); pau_ll_set_regdma_link_count(count - 1);
} }
#endif #endif
void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time)
{ {
HAL_ASSERT(loop_num > 0 && time > 0); HAL_ASSERT(loop_num > 0 && time > 0);
lp_aon_ll_set_regdma_link_loop_threshold(loop_num); pau_ll_set_regdma_link_loop_threshold(loop_num);
lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time); pau_ll_set_regdma_link_reg_access_tout_threshold(time);
} }
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{ {
HAL_ASSERT(count > 0 && interval > 0); HAL_ASSERT(count > 0 && interval > 0);
lp_aon_ll_set_regdma_link_wait_retry_count(count); pau_ll_set_regdma_link_wait_retry_count(count);
lp_aon_ll_set_regdma_link_wait_read_interval(interval); pau_ll_set_regdma_link_wait_read_interval(interval);
} }