From 4bd36e65761abd6f0142cf93391141d59859de8e Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 28 Dec 2022 19:33:22 +0800 Subject: [PATCH] clk_tree: Update clock tree programming guide for esp32c6 --- .../soc/esp32c6/include/soc/clk_tree_defs.h | 6 +++--- docs/docs_not_updated/esp32c6.txt | 1 - .../en/api-reference/peripherals/clk_tree.rst | 20 +++++++++++-------- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/components/soc/esp32c6/include/soc/clk_tree_defs.h b/components/soc/esp32c6/include/soc/clk_tree_defs.h index 9b4318d5cb..16243140eb 100644 --- a/components/soc/esp32c6/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c6/include/soc/clk_tree_defs.h @@ -37,8 +37,8 @@ extern "C" { * * 6) External Slow Clock (optional): OSC_SLOW * - * A clock signal generated by an external circuit with frequency ~32kHz can be connected to GPIO0 - * to be the clock source for the RTC_SLOW_CLK. + * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the + * RTC_SLOW_CLK. * * OSC_SLOW_CLK can also be calibrated to get its exact frequency. */ @@ -95,7 +95,7 @@ typedef enum { */ typedef enum { SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ - SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; diff --git a/docs/docs_not_updated/esp32c6.txt b/docs/docs_not_updated/esp32c6.txt index d14c16ea8f..b5dcc961ce 100644 --- a/docs/docs_not_updated/esp32c6.txt +++ b/docs/docs_not_updated/esp32c6.txt @@ -98,7 +98,6 @@ api-reference/peripherals/dac api-reference/peripherals/touch_element api-reference/peripherals/secure_element api-reference/peripherals/sdio_slave -api-reference/peripherals/clk_tree api-reference/peripherals/touch_pad api-reference/peripherals/adc_calibration api-reference/peripherals/ds diff --git a/docs/en/api-reference/peripherals/clk_tree.rst b/docs/en/api-reference/peripherals/clk_tree.rst index d7ba9b4e16..e555879ae4 100644 --- a/docs/en/api-reference/peripherals/clk_tree.rst +++ b/docs/en/api-reference/peripherals/clk_tree.rst @@ -1,11 +1,11 @@ Clock Tree ========== -{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32="8", esp32s2="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32h4="8"} +{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32="8", esp32s2="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8"} -{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32="8.5", esp32s2="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32h4="8.5"} +{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32="8.5", esp32s2="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8.5"} -{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32s2="40", esp32c3="40", esp32s3="40", esp32c2="40", esp32h4="32"} +{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h4="32"} {IDF_TARGET_RC_SLOW_VAGUE_FREQ: default="136", esp32="150", esp32s2="90"} @@ -31,13 +31,17 @@ Root clocks generate reliable clock signals. These clock signals then pass throu This RC oscillator generates a ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz clock signal output as the RC_FAST_CLK. - .. only:: not esp32h4 + .. only:: SOC_CLK_RC_FAST_D256_SUPPORTED The ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK. The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK. + + .. only:: not SOC_CLK_RC_FAST_D256_SUPPORTED and SOC_CLK_RC_FAST_SUPPORT_CALIBRATION - .. only:: esp32h4 + The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + + .. only:: not SOC_CLK_RC_FAST_SUPPORT_CALIBRATION The exact frequency of RC_FAST_CLK cannot be computed in runtime through calibration, but it is still possible to get its frequency through an oscillscope or a logic analyzer by routing the clock signal to a GPIO pin. @@ -47,7 +51,7 @@ Root clocks generate reliable clock signals. These clock signals then pass throu This RC oscillator generates a ~{IDF_TARGET_RC_SLOW_VAGUE_FREQ}kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock can be computed in runtime through calibration. - .. only:: not esp32c2 + .. only:: SOC_CLK_XTAL32K_SUPPORTED - External 32kHz Crystal - optional (XTAL32K) @@ -61,13 +65,13 @@ Root clocks generate reliable clock signals. These clock signals then pass throu XTAL32K_CLK can also be calibrated to get its exact frequency. - .. only:: esp32c2 + .. only:: SOC_CLK_OSC_SLOW_SUPPORTED - External Slow Clock - optional (OSC_SLOW) A clock signal generated by an external circuit can be connected to pin0 to be the clock source for the RTC_SLOW_CLK. This clock can also be calibrated to get its exact frequency. - .. only:: esp32h4 + .. only:: SOC_CLK_RC32K_SUPPORTED - Internal 32kHz RC Oscillator (RC32K)