From 3b371d2d64b55730f05b1a7df6de98992a9b243c Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 5 Jan 2022 15:44:02 +0800 Subject: [PATCH 1/6] ci: check unstable soc headers wont be leaked by public api --- .gitlab/ci/pre_check.yml | 3 +- docs/doxygen/Doxyfile_esp32h2 | 4 ++ tools/ci/check_soc_headers_leak.py | 112 +++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 docs/doxygen/Doxyfile_esp32h2 create mode 100644 tools/ci/check_soc_headers_leak.py diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml index d0121ac7cf..e6e2e22fd9 100644 --- a/.gitlab/ci/pre_check.yml +++ b/.gitlab/ci/pre_check.yml @@ -113,13 +113,14 @@ check_public_headers: script: - python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32-elf- -check_soc_struct_headers: +check_soc_component: extends: - .pre_check_base_template - .rules:build tags: - build script: + - python tools/ci/check_soc_headers_leak.py - find ${IDF_PATH}/components/soc/*/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py check_esp_err_to_name: diff --git a/docs/doxygen/Doxyfile_esp32h2 b/docs/doxygen/Doxyfile_esp32h2 new file mode 100644 index 0000000000..77e8851191 --- /dev/null +++ b/docs/doxygen/Doxyfile_esp32h2 @@ -0,0 +1,4 @@ +INPUT += \ + $(PROJECT_PATH)/components/driver/esp32h2/include/driver/temp_sensor.h \ + $(PROJECT_PATH)/components/esp_hw_support/include/soc/esp32h2/esp_ds.h \ + $(PROJECT_PATH)/components/esp_hw_support/include/soc/esp32h2/esp_hmac.h diff --git a/tools/ci/check_soc_headers_leak.py b/tools/ci/check_soc_headers_leak.py new file mode 100644 index 0000000000..62625913b5 --- /dev/null +++ b/tools/ci/check_soc_headers_leak.py @@ -0,0 +1,112 @@ +# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 + +# This check script is used to ensure the public APIs won't expose the unstable soc files like register files +# public API header files are those taken by doxygen and have full documented docs + +import fnmatch +import os +import re +import sys +import typing +from string import Template + +# The following header files in soc component is treated as stable, so is allowed to be used in any public header files +allowed_soc_headers = ( + 'soc/soc_caps.h', + 'soc/reset_reasons.h', + 'soc/reg_base.h', + 'soc/efuse_periph.h', # 'soc/efuse_periph.h' should not be allowed , remove it from the list in IDF-1256 +) + +include_header_pattern = re.compile(r'[\s]*#[\s]*include ["<](.*)[">].*') +doxyfile_target_pattern = re.compile(r'Doxyfile_(.*)') + + +class PublicAPIVisits: + def __init__(self, doxyfile_path: str, idf_path: str, target: str) -> None: + self.doxyfile_path = doxyfile_path + self._target = target + self._idf_path = idf_path + + def __iter__(self) -> typing.Generator: + with open(self.doxyfile_path, 'r', encoding='utf8') as f: + for line in f: + line = line.strip() + if line.startswith('$(PROJECT_PATH)'): + # $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/uart_channel.h \ + # -> ${PROJECT_PATH}/components/soc/${IDF_TARGET}/include/soc/uart_channel.h + line = line.replace('(', '{').replace(')', '}').rstrip('\\ ') + file_path = Template(line).substitute( + PROJECT_PATH=self._idf_path, IDF_TARGET=self._target + ) + yield file_path + + +def check_soc_not_in( + idf_path: str, + target: str, + doxyfile_path: str, + violation_dict: typing.Dict[str, set], +) -> None: + for file_path in PublicAPIVisits( + os.path.join(idf_path, doxyfile_path), idf_path, target + ): + with open(file_path, 'r', encoding='utf8') as f: + for line in f: + match_data = re.match(include_header_pattern, line) + if match_data: + header = match_data.group(1) + if header.startswith('soc') and header not in allowed_soc_headers: + if file_path not in violation_dict: + violation_dict[file_path] = set() + violation_dict[file_path].add(header) + + +def main() -> None: + idf_path = os.environ.get('IDF_PATH', None) + if idf_path is None: + print('IDF_PATH must be set before running this script', file=sys.stderr) + sys.exit(1) + + # list all doxyfiles + doxyfiles = fnmatch.filter( + os.listdir(os.path.join(idf_path, 'docs/doxygen')), 'Doxyfile*' + ) + print(f'Found Doxyfiles:{doxyfiles}') + + # targets are judged from Doxyfile name + targets = [] + for file in doxyfiles: + res = doxyfile_target_pattern.match(file) + if res: + targets.append(res.group(1)) + if not targets: + print('No targets found', file=sys.stderr) + sys.exit(1) + + soc_violation_dict: typing.Dict[str, set] = {} + for target in targets: + check_soc_not_in( + idf_path, + target, + os.path.join(idf_path, 'docs/doxygen/Doxyfile'), + soc_violation_dict, + ) + check_soc_not_in( + idf_path, + target, + os.path.join(idf_path, f'docs/doxygen/Doxyfile_{target}'), + soc_violation_dict, + ) + + if len(soc_violation_dict) > 0: + for file_path, headers_set in soc_violation_dict.items(): + print(f'{file_path} includes non-public soc header file: {headers_set}') + sys.exit(1) + else: + print('No violation found') + + +if __name__ == '__main__': + main() From d8f2eaf94e8b20850b3bb0d831ebda2a5647b912 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 5 Jan 2022 15:49:54 +0800 Subject: [PATCH 2/6] gpio: remove legacy rtc_io description for esp32 --- components/driver/Kconfig | 14 ----- components/soc/esp32/rtc_io_periph.c | 65 ++-------------------- components/soc/include/soc/rtc_io_periph.h | 53 ++---------------- docs/en/migration-guides/peripherals.rst | 5 ++ tools/ci/check_copyright_ignore.txt | 2 - 5 files changed, 16 insertions(+), 123 deletions(-) diff --git a/components/driver/Kconfig b/components/driver/Kconfig index 68c421a698..432a0e5cd7 100644 --- a/components/driver/Kconfig +++ b/components/driver/Kconfig @@ -156,20 +156,6 @@ menu "Driver configurations" endmenu # UART Configuration - menu "RTCIO configuration" - visible if IDF_TARGET_ESP32 - - config RTCIO_SUPPORT_RTC_GPIO_DESC - bool "Support array `rtc_gpio_desc` for ESP32" - depends on IDF_TARGET_ESP32 - default n - help - The the array `rtc_gpio_desc` will don't compile by default. - If this option is selected, the array `rtc_gpio_desc` can be compile. - If user use this array, please enable this configuration. - - endmenu # RTCIO Configuration - menu "GPIO Configuration" visible if IDF_TARGET_ESP32 diff --git a/components/soc/esp32/rtc_io_periph.c b/components/soc/esp32/rtc_io_periph.c index 9f8a864b9d..4f4cd77b10 100644 --- a/components/soc/esp32/rtc_io_periph.c +++ b/components/soc/esp32/rtc_io_periph.c @@ -1,16 +1,8 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/rtc_io_periph.h" @@ -79,50 +71,3 @@ const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = { {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, 0, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_CHANNEL_16_GPIO_NUM},//14 {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, 0, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_CHANNEL_17_GPIO_NUM},//27 }; - -#ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC -//Reg,Mux,Fun,IE,Up,Down,Rtc_number -const rtc_gpio_desc_t rtc_gpio_desc[SOC_GPIO_PIN_COUNT] = { - {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_HOLD_M, RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_GPIO0_CHANNEL}, //0 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //1 - {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_HOLD_M, RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_GPIO2_CHANNEL}, //2 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //3 - {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_HOLD_M, RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_GPIO4_CHANNEL}, //4 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //5 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //6 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //7 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //8 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //9 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //10 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //11 - {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_HOLD_M, RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_GPIO12_CHANNEL}, //12 - {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_HOLD_M, RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_GPIO13_CHANNEL}, //13 - {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_GPIO14_CHANNEL}, //14 - {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_HOLD_M, RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_GPIO15_CHANNEL}, //15 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //16 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //17 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //18 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //19 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //20 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //21 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //22 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //23 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //24 - {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_GPIO25_CHANNEL}, //25 - {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_HOLD_M, RTC_CNTL_PDAC2_HOLD_FORCE_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_GPIO26_CHANNEL}, //26 - {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_GPIO27_CHANNEL}, //27 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //28 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //29 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //30 - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1}, //31 - {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_GPIO32_CHANNEL}, //32 - {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_GPIO33_CHANNEL}, //33 - {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO34_CHANNEL}, //34 - {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC2_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO35_CHANNEL}, //35 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO36_CHANNEL}, //36 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE2_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO37_CHANNEL}, //37 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE3_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_GPIO38_CHANNEL}, //38 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE4_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_GPIO39_CHANNEL}, //39 -}; - -#endif //CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC diff --git a/components/soc/include/soc/rtc_io_periph.h b/components/soc/include/soc/rtc_io_periph.h index 618b64cd8f..106d879dfb 100644 --- a/components/soc/include/soc/rtc_io_periph.h +++ b/components/soc/include/soc/rtc_io_periph.h @@ -1,19 +1,12 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once + #include "soc/soc.h" //include soc related (generated) definitions #include "soc/soc_caps.h" @@ -79,40 +72,6 @@ extern const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT]; */ extern const int rtc_io_num_map[SOC_GPIO_PIN_COUNT]; -#ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC -/** - * @brief Pin function information for a single GPIO pad's RTC functions. - * - * This is an internal function of the driver, and is not usually useful - * for external use. - */ -typedef struct { - uint32_t reg; /*!< Register of RTC pad, or 0 if not an RTC GPIO */ - uint32_t mux; /*!< Bit mask for selecting digital pad or RTC pad */ - uint32_t func; /*!< Shift of pad function (FUN_SEL) field */ - uint32_t ie; /*!< Mask of input enable */ - uint32_t pullup; /*!< Mask of pullup enable */ - uint32_t pulldown; /*!< Mask of pulldown enable */ - uint32_t slpsel; /*!< If slpsel bit is set, slpie will be used as pad input enabled signal in sleep mode */ - uint32_t slpie; /*!< Mask of input enable in sleep mode */ - uint32_t hold; /*!< Mask of hold enable */ - uint32_t hold_force;/*!< Mask of hold_force bit for RTC IO in RTC_CNTL_HOLD_FORCE_REG */ - uint32_t drv_v; /*!< Mask of drive capability */ - uint32_t drv_s; /*!< Offset of drive capability */ - int rtc_num; /*!< RTC IO number, or -1 if not an RTC GPIO */ -} rtc_gpio_desc_t; - -/** - * @brief Provides access to a constant table of RTC I/O pin - * function information. - * - * This is an internal function of the driver, and is not usually useful - * for external use. - */ -extern const rtc_gpio_desc_t rtc_gpio_desc[SOC_GPIO_PIN_COUNT]; - -#endif // CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC - #endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #ifdef __cplusplus diff --git a/docs/en/migration-guides/peripherals.rst b/docs/en/migration-guides/peripherals.rst index cac6a09a9a..46a93bb8cb 100644 --- a/docs/en/migration-guides/peripherals.rst +++ b/docs/en/migration-guides/peripherals.rst @@ -21,3 +21,8 @@ ADC --- Previous `driver/adc2_wifi_private.h` has been moved to `esp_private/adc2_wifi.h`. + +GPIO +---- + +The previous Kconfig option `RTCIO_SUPPORT_RTC_GPIO_DESC` has been removed, thus the ``rtc_gpio_desc`` array is unavailable. Please use ``rtc_io_desc`` array instead. diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index be4283d126..8c0efd375c 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1652,7 +1652,6 @@ components/soc/esp32/ledc_periph.c components/soc/esp32/mcpwm_periph.c components/soc/esp32/pcnt_periph.c components/soc/esp32/rmt_periph.c -components/soc/esp32/rtc_io_periph.c components/soc/esp32/sdio_slave_periph.c components/soc/esp32/sdmmc_periph.c components/soc/esp32/sigmadelta_periph.c @@ -2018,7 +2017,6 @@ components/soc/include/soc/mcpwm_periph.h components/soc/include/soc/pcnt_periph.h components/soc/include/soc/rmt_periph.h components/soc/include/soc/rtc_cntl_periph.h -components/soc/include/soc/rtc_io_periph.h components/soc/include/soc/rtc_periph.h components/soc/include/soc/sdio_slave_periph.h components/soc/include/soc/sdmmc_periph.h From 8cdcb4e2910d0e55b0da7c6e7684fd1f79341723 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 5 Jan 2022 16:11:19 +0800 Subject: [PATCH 3/6] rmt: move RMT item definition from soc to driver --- components/driver/include/driver/rmt.h | 18 ++++- components/driver/rmt.c | 6 +- components/hal/esp32/include/hal/rmt_ll.h | 27 +++---- components/hal/esp32c3/include/hal/rmt_ll.h | 8 +- components/hal/esp32h2/include/hal/rmt_ll.h | 9 ++- components/hal/esp32s2/include/hal/rmt_ll.h | 9 ++- components/hal/esp32s3/include/hal/rmt_ll.h | 9 ++- components/hal/include/hal/rmt_hal.h | 37 +++------ components/hal/rmt_hal.c | 36 ++------- components/soc/esp32/include/soc/rmt_struct.h | 72 +++++------------ .../soc/esp32c3/include/soc/rmt_struct.h | 80 ++++++------------- .../soc/esp32h2/include/soc/rmt_struct.h | 64 +++++---------- .../soc/esp32s2/include/soc/rmt_struct.h | 78 ++++++------------ .../soc/esp32s3/include/soc/rmt_struct.h | 52 +++--------- tools/ci/check_copyright_ignore.txt | 7 -- .../test_utils/ref_clock_impl_rmt_pcnt.c | 3 +- 16 files changed, 182 insertions(+), 333 deletions(-) diff --git a/components/driver/include/driver/rmt.h b/components/driver/include/driver/rmt.h index bc07954a08..a8339e6ae0 100644 --- a/components/driver/include/driver/rmt.h +++ b/components/driver/include/driver/rmt.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,7 +17,6 @@ extern "C" { #include "driver/gpio.h" #include "freertos/FreeRTOS.h" #include "freertos/ringbuf.h" -#include "soc/rmt_struct.h" #include "hal/rmt_types.h" #define RMT_CHANNEL_FLAGS_AWARE_DFS (1 << 0) /*!< Channel can work during APB clock scaling */ @@ -33,6 +32,21 @@ extern "C" { */ #define RMT_MEM_ITEM_NUM SOC_RMT_MEM_WORDS_PER_CHANNEL +/** + * @brief Definition of RMT item + */ +typedef struct { + union { + struct { + uint32_t duration0 : 15; /*!< Duration of level0 */ + uint32_t level0 : 1; /*!< Level of the first part */ + uint32_t duration1 : 15; /*!< Duration of level1 */ + uint32_t level1 : 1; /*!< Level of the second part */ + }; + uint32_t val; /*!< Equivelent unsigned value for the RMT item */ + }; +} rmt_item32_t; + /** * @brief Data struct of RMT TX configure parameters */ diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 920a21c15d..ad3df9f587 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -742,7 +742,7 @@ static int IRAM_ATTR rmt_rx_get_mem_len_in_isr(rmt_channel_t channel) static void IRAM_ATTR rmt_driver_isr_default(void *arg) { uint32_t status = 0; - rmt_item32_t volatile *addr = NULL; + rmt_item32_t *addr = NULL; uint8_t channel = 0; rmt_hal_context_t *hal = (rmt_hal_context_t *)arg; portBASE_TYPE HPTaskAwoken = pdFALSE; @@ -829,7 +829,7 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) int item_len = rmt_rx_get_mem_len_in_isr(channel); rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_SW); if (p_rmt->rx_buf) { - addr = RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32; + addr = (rmt_item32_t *)RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32; #if SOC_RMT_SUPPORT_RX_PINGPONG if (item_len > p_rmt->rx_item_start_idx) { item_len = item_len - p_rmt->rx_item_start_idx; diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h index dfd8199d5b..a017b2685a 100644 --- a/components/hal/esp32/include/hal/rmt_ll.h +++ b/components/hal/esp32/include/hal/rmt_ll.h @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include @@ -22,6 +14,13 @@ extern "C" { #endif +typedef struct rmt_mem_t { + struct { + uint32_t data32[64]; + } chan[8]; +} rmt_mem_t; +extern rmt_mem_t RMTMEM; + #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) @@ -87,7 +86,7 @@ static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) { - RMTMEM.chan[channel].data32[0].val = 0; + RMTMEM.chan[channel].data32[0] = 0; dev->conf_ch[channel].conf1.tx_start = 0; dev->conf_ch[channel].conf1.mem_rd_rst = 1; dev->conf_ch[channel].conf1.mem_rd_rst = 0; diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h index 662e63f784..0cec7df6fc 100644 --- a/components/hal/esp32c3/include/hal/rmt_ll.h +++ b/components/hal/esp32c3/include/hal/rmt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,12 @@ extern "C" { #endif +typedef struct rmt_mem_t { + struct { + uint32_t data32[48]; + } chan[4]; +} rmt_mem_t; +extern rmt_mem_t RMTMEM; #define RMT_LL_MAX_LOOP_COUNT (1023)/*!< Max loop count that hardware is supported */ diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h index 0403741429..f287050e95 100644 --- a/components/hal/esp32h2/include/hal/rmt_ll.h +++ b/components/hal/esp32h2/include/hal/rmt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,13 @@ extern "C" { #endif +typedef struct rmt_mem_t { + struct { + uint32_t data32[48]; + } chan[4]; +} rmt_mem_t; +extern rmt_mem_t RMTMEM; + #define RMT_LL_MAX_LOOP_COUNT (1023)/*!< Max loop count that hardware is supported */ #define RMT_LL_HW_BASE (&RMT) diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h index ba73eaa2b7..5b3a8fc2b5 100644 --- a/components/hal/esp32s2/include/hal/rmt_ll.h +++ b/components/hal/esp32s2/include/hal/rmt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,13 @@ extern "C" { #endif +typedef struct rmt_mem_t { + struct { + uint32_t data32[64]; + } chan[4]; +} rmt_mem_t; +extern rmt_mem_t RMTMEM; + #define RMT_LL_MAX_LOOP_COUNT (1023)/*!< Max loop count that hardware is supported */ #define RMT_LL_HW_BASE (&RMT) diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h index 2e6ddd563a..af6242bb2a 100644 --- a/components/hal/esp32s3/include/hal/rmt_ll.h +++ b/components/hal/esp32s3/include/hal/rmt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,13 @@ extern "C" { #endif +typedef struct rmt_mem_t { + struct { + uint32_t data32[48]; + } chan[8]; +} rmt_mem_t; +extern rmt_mem_t RMTMEM; + #define RMT_LL_MAX_LOOP_COUNT (1023)/*!< Max loop count that hardware is supported */ #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) diff --git a/components/hal/include/hal/rmt_hal.h b/components/hal/include/hal/rmt_hal.h index 49b3f4c670..327bd6fd9c 100644 --- a/components/hal/include/hal/rmt_hal.h +++ b/components/hal/include/hal/rmt_hal.h @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #ifdef __cplusplus @@ -18,16 +10,17 @@ extern "C" { #endif #include -#include "soc/soc_caps.h" -#include "soc/rmt_struct.h" + +typedef struct rmt_dev_t *rmt_soc_handle_t; // RMT SOC layer handle +typedef struct rmt_mem_t *rmt_mem_handle_t; // RMT memory handle /** * @brief HAL context type of RMT driver * */ typedef struct { - rmt_dev_t *regs; /*!< RMT Register base address */ - rmt_mem_t *mem; /*!< RMT Memory base address */ + rmt_soc_handle_t regs; /*!< RMT Register base address */ + rmt_mem_handle_t mem; /*!< RMT Memory base address */ } rmt_hal_context_t; #define RMT_MEM_OWNER_SW (0) /*!< RMT Memory ownership belongs to software side */ @@ -97,16 +90,6 @@ void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint3 */ void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us); -/** - * @brief Receive a frame from RMT channel - * - * @param hal: RMT HAL context - * @param channel: RMT channel number - * @param buf: buffer to store received RMT frame - * @return number of items that get received - */ -uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf); - #ifdef __cplusplus } #endif diff --git a/components/hal/rmt_hal.c b/components/hal/rmt_hal.c index bdb6942690..5acf37d12a 100644 --- a/components/hal/rmt_hal.c +++ b/components/hal/rmt_hal.c @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "hal/rmt_hal.h" #include "hal/rmt_ll.h" #include "soc/soc_caps.h" @@ -68,21 +60,3 @@ void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_ uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us); rmt_ll_rx_set_idle_thres(hal->regs, channel, thres); } - -uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf) -{ - uint32_t len = 0; - rmt_ll_rx_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW); - for (len = 0; len < SOC_RMT_MEM_WORDS_PER_CHANNEL; len++) { - buf[len].val = hal->mem->chan[channel].data32[len].val; - if (!(buf[len].val & 0x7FFF)) { - break; - } else if (!(buf[len].val & 0x7FFF0000)) { - len++; - break; - } - } - rmt_ll_rx_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW); - rmt_ll_rx_reset_pointer(hal->regs, channel); - return len; -} diff --git a/components/soc/esp32/include/soc/rmt_struct.h b/components/soc/esp32/include/soc/rmt_struct.h index fd1815a498..85b7d47e01 100644 --- a/components/soc/esp32/include/soc/rmt_struct.h +++ b/components/soc/esp32/include/soc/rmt_struct.h @@ -1,18 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RMT_STRUCT_H_ -#define _SOC_RMT_STRUCT_H_ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once #include @@ -20,11 +11,11 @@ extern "C" { #endif -typedef volatile struct rmt_dev_s { - uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access. +typedef struct rmt_dev_t { + volatile uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access. Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/ - struct { + volatile struct { union { struct { uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ @@ -57,9 +48,9 @@ typedef volatile struct rmt_dev_s { uint32_t val; } conf1; } conf_ch[8]; - uint32_t status_ch[8]; /*The status for channel0-7*/ - uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/ - union { + volatile uint32_t status_ch[8]; /*The status for channel0-7*/ + volatile uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/ + volatile union { struct { uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ @@ -96,7 +87,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_raw; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ @@ -133,7 +124,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_st; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ @@ -170,7 +161,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_ena; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ @@ -207,21 +198,21 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_clr; - union { + volatile union { struct { uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ - uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ + uint32_t high: 16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ }; uint32_t val; } carrier_duty_ch[8]; - union { + volatile union { struct { uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ uint32_t reserved9: 23; }; uint32_t val; } tx_lim_ch[8]; - union { + volatile union { struct { uint32_t fifo_mask: 1; /*Set this bit to enable RMTMEM and disable apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/ uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ @@ -231,32 +222,11 @@ typedef volatile struct rmt_dev_s { } apb_conf; uint32_t reserved_f4; uint32_t reserved_f8; - uint32_t date; /*This is the version register.*/ + volatile uint32_t date; /*This is the version register.*/ } rmt_dev_t; + extern rmt_dev_t RMT; -typedef struct rmt_item32_s { - union { - struct { - uint32_t duration0 :15; - uint32_t level0 :1; - uint32_t duration1 :15; - uint32_t level1 :1; - }; - uint32_t val; - }; -} rmt_item32_t; - -//Allow access to RMT memory using RMTMEM.chan[0].data32[8] -typedef volatile struct rmt_mem_s { - struct { - rmt_item32_t data32[64]; - } chan[8]; -} rmt_mem_t; -extern rmt_mem_t RMTMEM; - #ifdef __cplusplus } #endif - -#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/soc/esp32c3/include/soc/rmt_struct.h b/components/soc/esp32c3/include/soc/rmt_struct.h index b9b7533b3d..14550622f7 100644 --- a/components/soc/esp32c3/include/soc/rmt_struct.h +++ b/components/soc/esp32c3/include/soc/rmt_struct.h @@ -1,18 +1,9 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RMT_STRUCT_H_ -#define _SOC_RMT_STRUCT_H_ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once #include @@ -20,9 +11,9 @@ extern "C" { #endif -typedef volatile struct rmt_dev_s { - uint32_t data_ch[4]; /**/ - union { +typedef struct rmt_dev_t { + volatile uint32_t data_ch[4]; + volatile union { struct { uint32_t tx_start: 1; uint32_t mem_rd_rst: 1; @@ -44,7 +35,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_conf[2]; - struct { + volatile struct { union { struct { uint32_t div_cnt: 8; @@ -73,7 +64,7 @@ typedef volatile struct rmt_dev_s { uint32_t val; } conf1; } rx_conf[2]; - union { + volatile union { struct { uint32_t mem_raddr_ex: 9; uint32_t state: 3; @@ -85,7 +76,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_status[2]; - union { + volatile union { struct { uint32_t mem_waddr_ex: 9; uint32_t reserved9: 3; @@ -99,7 +90,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } rx_status[2]; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -119,7 +110,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_raw; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -139,7 +130,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_st; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -159,7 +150,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_ena; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -179,21 +170,21 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_clr; - union { + volatile union { struct { uint32_t low: 16; uint32_t high: 16; }; uint32_t val; } tx_carrier[2]; - union { + volatile union { struct { uint32_t low_thres: 16; uint32_t high_thres: 16; }; uint32_t val; } rx_carrier[2]; - union { + volatile union { struct { uint32_t limit: 9; uint32_t tx_loop_num: 10; @@ -203,14 +194,14 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_lim[2]; - union { + volatile union { struct { uint32_t rx_lim: 9; uint32_t reserved9: 23; }; uint32_t val; } rx_lim[2]; - union { + volatile union { struct { uint32_t fifo_mask: 1; uint32_t mem_clk_force_on: 1; @@ -226,7 +217,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } sys_conf; - union { + volatile union { struct { uint32_t ch0: 1; uint32_t ch1: 1; @@ -235,7 +226,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_sim; - union { + volatile union { struct { uint32_t ch0: 1; uint32_t ch1: 1; @@ -267,7 +258,7 @@ typedef volatile struct rmt_dev_s { uint32_t reserved_c0; uint32_t reserved_c4; uint32_t reserved_c8; - union { + volatile union { struct { uint32_t date: 28; uint32_t reserved28: 4; @@ -278,29 +269,6 @@ typedef volatile struct rmt_dev_s { extern rmt_dev_t RMT; -typedef struct { - union { - struct { - uint32_t duration0 : 15; - uint32_t level0 : 1; - uint32_t duration1 : 15; - uint32_t level1 : 1; - }; - uint32_t val; - }; -} rmt_item32_t; - -//Allow access to RMT memory using RMTMEM.chan[0].data32[8] -typedef volatile struct rmt_mem_s { - struct { - rmt_item32_t data32[48]; - } chan[4]; -} rmt_mem_t; - -extern rmt_mem_t RMTMEM; - #ifdef __cplusplus } #endif - -#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/rmt_struct.h b/components/soc/esp32h2/include/soc/rmt_struct.h index 9eb6cfafd5..14550622f7 100644 --- a/components/soc/esp32h2/include/soc/rmt_struct.h +++ b/components/soc/esp32h2/include/soc/rmt_struct.h @@ -1,10 +1,9 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_RMT_STRUCT_H_ -#define _SOC_RMT_STRUCT_H_ +#pragma once #include @@ -12,9 +11,9 @@ extern "C" { #endif -typedef volatile struct rmt_dev_s { - uint32_t data_ch[4]; /**/ - union { +typedef struct rmt_dev_t { + volatile uint32_t data_ch[4]; + volatile union { struct { uint32_t tx_start: 1; uint32_t mem_rd_rst: 1; @@ -36,7 +35,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_conf[2]; - struct { + volatile struct { union { struct { uint32_t div_cnt: 8; @@ -65,7 +64,7 @@ typedef volatile struct rmt_dev_s { uint32_t val; } conf1; } rx_conf[2]; - union { + volatile union { struct { uint32_t mem_raddr_ex: 9; uint32_t state: 3; @@ -77,7 +76,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_status[2]; - union { + volatile union { struct { uint32_t mem_waddr_ex: 9; uint32_t reserved9: 3; @@ -91,7 +90,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } rx_status[2]; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -111,7 +110,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_raw; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -131,7 +130,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_st; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -151,7 +150,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_ena; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch1_tx_end: 1; @@ -171,21 +170,21 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_clr; - union { + volatile union { struct { uint32_t low: 16; uint32_t high: 16; }; uint32_t val; } tx_carrier[2]; - union { + volatile union { struct { uint32_t low_thres: 16; uint32_t high_thres: 16; }; uint32_t val; } rx_carrier[2]; - union { + volatile union { struct { uint32_t limit: 9; uint32_t tx_loop_num: 10; @@ -195,14 +194,14 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_lim[2]; - union { + volatile union { struct { uint32_t rx_lim: 9; uint32_t reserved9: 23; }; uint32_t val; } rx_lim[2]; - union { + volatile union { struct { uint32_t fifo_mask: 1; uint32_t mem_clk_force_on: 1; @@ -218,7 +217,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } sys_conf; - union { + volatile union { struct { uint32_t ch0: 1; uint32_t ch1: 1; @@ -227,7 +226,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_sim; - union { + volatile union { struct { uint32_t ch0: 1; uint32_t ch1: 1; @@ -259,7 +258,7 @@ typedef volatile struct rmt_dev_s { uint32_t reserved_c0; uint32_t reserved_c4; uint32_t reserved_c8; - union { + volatile union { struct { uint32_t date: 28; uint32_t reserved28: 4; @@ -270,29 +269,6 @@ typedef volatile struct rmt_dev_s { extern rmt_dev_t RMT; -typedef struct { - union { - struct { - uint32_t duration0 : 15; - uint32_t level0 : 1; - uint32_t duration1 : 15; - uint32_t level1 : 1; - }; - uint32_t val; - }; -} rmt_item32_t; - -//Allow access to RMT memory using RMTMEM.chan[0].data32[8] -typedef volatile struct rmt_mem_s { - struct { - rmt_item32_t data32[48]; - } chan[4]; -} rmt_mem_t; - -extern rmt_mem_t RMTMEM; - #ifdef __cplusplus } #endif - -#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/soc/esp32s2/include/soc/rmt_struct.h b/components/soc/esp32s2/include/soc/rmt_struct.h index 5e43004093..e70dc7d925 100644 --- a/components/soc/esp32s2/include/soc/rmt_struct.h +++ b/components/soc/esp32s2/include/soc/rmt_struct.h @@ -1,18 +1,9 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RMT_STRUCT_H_ -#define _SOC_RMT_STRUCT_H_ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once #include @@ -20,9 +11,9 @@ extern "C" { #endif -typedef volatile struct rmt_dev_s { - uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */ - struct { +typedef struct rmt_dev_t { + volatile uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */ + volatile struct { union { struct { uint32_t div_cnt: 8; @@ -56,7 +47,7 @@ typedef volatile struct rmt_dev_s { uint32_t val; } conf1; } conf_ch[4]; - union { + volatile union { struct { uint32_t mem_waddr_ex: 9; uint32_t reserved9: 1; @@ -72,7 +63,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } status_ch[4]; - union { + volatile union { struct { uint32_t waddr: 9; uint32_t reserved9: 1; @@ -81,7 +72,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } apb_mem_addr_ch[4]; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch0_rx_end: 1; @@ -111,7 +102,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_raw; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch0_rx_end: 1; @@ -141,7 +132,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_st; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch0_rx_end: 1; @@ -171,7 +162,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_ena; - union { + volatile union { struct { uint32_t ch0_tx_end: 1; uint32_t ch0_rx_end: 1; @@ -201,14 +192,14 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } int_clr; - union { + volatile union { struct { uint32_t low: 16; uint32_t high: 16; }; uint32_t val; } carrier_duty_ch[4]; - union { + volatile union { struct { uint32_t limit: 9; uint32_t tx_loop_num: 10; @@ -219,7 +210,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_lim_ch[4]; - union { + volatile union { struct { uint32_t fifo_mask: 1; uint32_t mem_tx_wrap_en: 1; @@ -231,7 +222,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } apb_conf; - union { + volatile union { struct { uint32_t ch0: 1; uint32_t ch1: 1; @@ -242,7 +233,7 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } tx_sim; - union { + volatile union { struct { uint32_t ch0: 1; uint32_t ch1: 1; @@ -252,10 +243,10 @@ typedef volatile struct rmt_dev_s { }; uint32_t val; } ref_cnt_rst; - union { + volatile union { struct { uint32_t carrier_low_thres_ch: 16; - uint32_t carrier_high_thres_ch:16; + uint32_t carrier_high_thres_ch: 16; }; uint32_t val; } ch_rx_carrier_rm[4]; @@ -283,32 +274,11 @@ typedef volatile struct rmt_dev_s { uint32_t reserved_f0; uint32_t reserved_f4; uint32_t reserved_f8; - uint32_t date; /* Version Control Register */ + volatile uint32_t date; } rmt_dev_t; + extern rmt_dev_t RMT; -typedef struct { - union { - struct { - uint32_t duration0 :15; - uint32_t level0 :1; - uint32_t duration1 :15; - uint32_t level1 :1; - }; - uint32_t val; - }; -} rmt_item32_t; - -//Allow access to RMT memory using RMTMEM.chan[0].data32[8] -typedef volatile struct rmt_mem_s { - struct { - rmt_item32_t data32[64]; - } chan[4]; -} rmt_mem_t; -extern rmt_mem_t RMTMEM; - #ifdef __cplusplus } #endif - -#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/esp32s3/include/soc/rmt_struct.h index 275bfebce6..189b8b34bd 100644 --- a/components/soc/esp32s3/include/soc/rmt_struct.h +++ b/components/soc/esp32s3/include/soc/rmt_struct.h @@ -1,16 +1,7 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -123,7 +114,11 @@ typedef union { * synchronization bit for CHANNELn */ uint32_t conf_update_n: 1; - uint32_t reserved_25: 7; + /** dma_access_en_n : WT; bitpos: [25]; default: 0; + * DMA access control bit for CHANNELn + */ + uint32_t dma_access_en_n: 1; + uint32_t reserved_26: 6; }; uint32_t val; } rmt_chnconf0_reg_t; @@ -143,7 +138,10 @@ typedef struct { * than this register value, received process is finished. */ uint32_t idle_thres_m: 15; - uint32_t reserved_23: 1; + /** dma_access_en_m : WT; bitpos: [23]; default: 0; + * DMA access control bit for CHANNELm + */ + uint32_t dma_access_en_m: 1; /** mem_size_m : R/W; bitpos: [27:24]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNELm. */ @@ -1064,7 +1062,7 @@ typedef union { } rmt_date_reg_t; -typedef struct { +typedef struct rmt_dev_t { volatile rmt_chndata_reg_t chndata[4]; volatile rmt_chmdata_reg_t chmdata[4]; volatile rmt_chnconf0_reg_t chnconf0[4]; @@ -1089,31 +1087,7 @@ typedef struct { _Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); #endif -typedef struct { - union { - struct { - uint32_t duration0 : 15; - uint32_t level0 : 1; - uint32_t duration1 : 15; - uint32_t level1 : 1; - }; - uint32_t val; - }; -} rmt_item32_t; - -typedef struct { - struct { - volatile rmt_item32_t data32[48]; - } chan[8]; -} rmt_mem_t; - -#ifndef __cplusplus -_Static_assert(sizeof(rmt_item32_t) == 0x04, "Invalid size of rmt_item32_t structure"); -_Static_assert(sizeof(rmt_mem_t) == 0x04 * 8 * 48, "Invalid size of rmt_mem_t structure"); -#endif - extern rmt_dev_t RMT; -extern rmt_mem_t RMTMEM; #ifdef __cplusplus } diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 8c0efd375c..6bd985ace1 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -973,7 +973,6 @@ components/hal/esp32/include/hal/i2s_ll.h components/hal/esp32/include/hal/interrupt_controller_ll.h components/hal/esp32/include/hal/mpu_ll.h components/hal/esp32/include/hal/pcnt_ll.h -components/hal/esp32/include/hal/rmt_ll.h components/hal/esp32/include/hal/rtc_cntl_ll.h components/hal/esp32/include/hal/rtc_io_ll.h components/hal/esp32/include/hal/rwdt_ll.h @@ -1129,7 +1128,6 @@ components/hal/include/hal/mpu_hal.h components/hal/include/hal/mpu_types.h components/hal/include/hal/pcnt_hal.h components/hal/include/hal/pcnt_types.h -components/hal/include/hal/rmt_hal.h components/hal/include/hal/rmt_types.h components/hal/include/hal/rtc_io_types.h components/hal/include/hal/sdio_slave_hal.h @@ -1166,7 +1164,6 @@ components/hal/platform_port/include/hal/assert.h components/hal/platform_port/include/hal/check.h components/hal/platform_port/include/hal/log.h components/hal/platform_port/include/hal/misc.h -components/hal/rmt_hal.c components/hal/rtc_io_hal.c components/hal/sdio_slave_hal.c components/hal/sha_hal.c @@ -1615,7 +1612,6 @@ components/soc/esp32/include/soc/pcnt_struct.h components/soc/esp32/include/soc/pid.h components/soc/esp32/include/soc/reset_reasons.h components/soc/esp32/include/soc/rmt_reg.h -components/soc/esp32/include/soc/rmt_struct.h components/soc/esp32/include/soc/rtc_cntl_reg.h components/soc/esp32/include/soc/rtc_cntl_struct.h components/soc/esp32/include/soc/rtc_i2c_reg.h @@ -1696,7 +1692,6 @@ components/soc/esp32c3/include/soc/nrx_reg.h components/soc/esp32c3/include/soc/periph_defs.h components/soc/esp32c3/include/soc/reset_reasons.h components/soc/esp32c3/include/soc/rmt_reg.h -components/soc/esp32c3/include/soc/rmt_struct.h components/soc/esp32c3/include/soc/rtc_cntl_reg.h components/soc/esp32c3/include/soc/rtc_cntl_struct.h components/soc/esp32c3/include/soc/rtc_i2c_reg.h @@ -1832,7 +1827,6 @@ components/soc/esp32s2/include/soc/pcnt_reg.h components/soc/esp32s2/include/soc/pcnt_struct.h components/soc/esp32s2/include/soc/reset_reasons.h components/soc/esp32s2/include/soc/rmt_reg.h -components/soc/esp32s2/include/soc/rmt_struct.h components/soc/esp32s2/include/soc/rtc_cntl_reg.h components/soc/esp32s2/include/soc/rtc_cntl_struct.h components/soc/esp32s2/include/soc/rtc_i2c_reg.h @@ -1938,7 +1932,6 @@ components/soc/esp32s3/include/soc/peri_backup_reg.h components/soc/esp32s3/include/soc/peri_backup_struct.h components/soc/esp32s3/include/soc/reset_reasons.h components/soc/esp32s3/include/soc/rmt_reg.h -components/soc/esp32s3/include/soc/rmt_struct.h components/soc/esp32s3/include/soc/rtc_gpio_channel.h components/soc/esp32s3/include/soc/rtc_i2c_reg.h components/soc/esp32s3/include/soc/rtc_i2c_struct.h diff --git a/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c b/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c index b1cde08800..ea32a2af8a 100644 --- a/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c +++ b/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,7 @@ #include "freertos/FreeRTOS.h" #include "esp_intr_alloc.h" #include "esp_private/periph_ctrl.h" +#include "driver/rmt.h" #include "soc/gpio_sig_map.h" #include "soc/gpio_periph.h" #include "soc/soc_caps.h" From 24acdf23ee6af374067183c5c0493b289b1c3ae3 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 5 Jan 2022 16:14:03 +0800 Subject: [PATCH 4/6] soc: move peripheral base address into reg_base.h --- components/soc/CMakeLists.txt | 1 - .../soc/esp32/include/soc/periph_defs.h | 7 +- components/soc/esp32/include/soc/reg_base.h | 59 +++++++++++ components/soc/esp32/include/soc/soc.h | 77 ++------------ .../soc/esp32c3/include/soc/periph_defs.h | 18 +--- components/soc/esp32c3/include/soc/reg_base.h | 48 +++++++++ components/soc/esp32c3/include/soc/soc.h | 56 +--------- components/soc/esp32h2/include/soc/reg_base.h | 74 +++++++++++++ components/soc/esp32h2/include/soc/soc.h | 84 +-------------- .../soc/esp32s2/include/soc/periph_defs.h | 8 +- components/soc/esp32s2/include/soc/reg_base.h | 63 +++++++++++ components/soc/esp32s2/include/soc/soc.h | 87 ++------------- components/soc/esp32s3/include/soc/reg_base.h | 64 +++++++++++ components/soc/esp32s3/include/soc/soc.h | 100 ++---------------- components/soc/esp8684/include/soc/reg_base.h | 42 ++++++++ components/soc/esp8684/include/soc/soc.h | 49 +-------- components/soc/soc_include_legacy_warn.c | 5 - tools/ci/check_copyright_ignore.txt | 4 - 18 files changed, 394 insertions(+), 452 deletions(-) create mode 100644 components/soc/esp32/include/soc/reg_base.h create mode 100644 components/soc/esp32c3/include/soc/reg_base.h create mode 100644 components/soc/esp32h2/include/soc/reg_base.h create mode 100644 components/soc/esp32s2/include/soc/reg_base.h create mode 100644 components/soc/esp32s3/include/soc/reg_base.h create mode 100644 components/soc/esp8684/include/soc/reg_base.h delete mode 100644 components/soc/soc_include_legacy_warn.c diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 461f45fd40..cd7e118e51 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -1,5 +1,4 @@ idf_component_register(SRCS "lldesc.c" - "soc_include_legacy_warn.c" INCLUDE_DIRS include LDFRAGMENTS "linker.lf") diff --git a/components/soc/esp32/include/soc/periph_defs.h b/components/soc/esp32/include/soc/periph_defs.h index d6e7f8cf00..da81a70d59 100644 --- a/components/soc/esp32/include/soc/periph_defs.h +++ b/components/soc/esp32/include/soc/periph_defs.h @@ -1,11 +1,10 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_PERIPH_DEFS_H_ -#define _SOC_PERIPH_DEFS_H_ +#pragma once #ifdef __cplusplus extern "C" { @@ -53,5 +52,3 @@ typedef enum { #ifdef __cplusplus } #endif - -#endif /* _SOC_PERIPH_DEFS_H_ */ diff --git a/components/soc/esp32/include/soc/reg_base.h b/components/soc/esp32/include/soc/reg_base.h new file mode 100644 index 0000000000..7205809a95 --- /dev/null +++ b/components/soc/esp32/include/soc/reg_base.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_DPORT_BASE 0x3ff00000 +#define DR_REG_AES_BASE 0x3ff01000 +#define DR_REG_RSA_BASE 0x3ff02000 +#define DR_REG_SHA_BASE 0x3ff03000 +#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 +#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 +#define DR_REG_DPORT_END 0x3ff13FFC +#define DR_REG_UART_BASE 0x3ff40000 +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 +#define DR_REG_GPIO_SD_BASE 0x3ff44f00 +#define DR_REG_FE2_BASE 0x3ff45000 +#define DR_REG_FE_BASE 0x3ff46000 +#define DR_REG_FRC_TIMER_BASE 0x3ff47000 +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SENS_BASE 0x3ff48800 +#define DR_REG_RTC_I2C_BASE 0x3ff48C00 +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_HINF_BASE 0x3ff4B000 +#define DR_REG_UHCI1_BASE 0x3ff4C000 +#define DR_REG_I2S_BASE 0x3ff4F000 +#define DR_REG_UART1_BASE 0x3ff50000 +#define DR_REG_BT_BASE 0x3ff51000 +#define DR_REG_I2C_EXT_BASE 0x3ff53000 +#define DR_REG_UHCI0_BASE 0x3ff54000 +#define DR_REG_SLCHOST_BASE 0x3ff55000 +#define DR_REG_RMT_BASE 0x3ff56000 +#define DR_REG_PCNT_BASE 0x3ff57000 +#define DR_REG_SLC_BASE 0x3ff58000 +#define DR_REG_LEDC_BASE 0x3ff59000 +#define DR_REG_EFUSE_BASE 0x3ff5A000 +#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_NRX_BASE 0x3ff5CC00 +#define DR_REG_BB_BASE 0x3ff5D000 +#define DR_REG_PWM0_BASE 0x3ff5E000 +#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 +#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 +#define DR_REG_SPI2_BASE 0x3ff64000 +#define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_SYSCON_BASE 0x3ff66000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3ff67000 +#define DR_REG_SDMMC_BASE 0x3ff68000 +#define DR_REG_EMAC_BASE 0x3ff69000 +#define DR_REG_CAN_BASE 0x3ff6B000 +#define DR_REG_PWM1_BASE 0x3ff6C000 +#define DR_REG_I2S1_BASE 0x3ff6D000 +#define DR_REG_UART2_BASE 0x3ff6E000 +#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index f9e3e87593..ffa1043176 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -1,16 +1,8 @@ -// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -19,7 +11,8 @@ #include "esp_assert.h" #endif -#include +#include "esp_bit_defs.h" +#include "reg_base.h" #define PRO_CPU_NUM (0) #define APP_CPU_NUM (1) @@ -27,62 +20,6 @@ #define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space - -#define DR_REG_DPORT_BASE 0x3ff00000 -#define DR_REG_AES_BASE 0x3ff01000 -#define DR_REG_RSA_BASE 0x3ff02000 -#define DR_REG_SHA_BASE 0x3ff03000 -#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 -#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 -#define DR_REG_DPORT_END 0x3ff13FFC -#define DR_REG_UART_BASE 0x3ff40000 -#define DR_REG_SPI1_BASE 0x3ff42000 -#define DR_REG_SPI0_BASE 0x3ff43000 -#define DR_REG_GPIO_BASE 0x3ff44000 -#define DR_REG_GPIO_SD_BASE 0x3ff44f00 -#define DR_REG_FE2_BASE 0x3ff45000 -#define DR_REG_FE_BASE 0x3ff46000 -#define DR_REG_FRC_TIMER_BASE 0x3ff47000 -#define DR_REG_RTCCNTL_BASE 0x3ff48000 -#define DR_REG_RTCIO_BASE 0x3ff48400 -#define DR_REG_SENS_BASE 0x3ff48800 -#define DR_REG_RTC_I2C_BASE 0x3ff48C00 -#define DR_REG_IO_MUX_BASE 0x3ff49000 -#define DR_REG_HINF_BASE 0x3ff4B000 -#define DR_REG_UHCI1_BASE 0x3ff4C000 -#define DR_REG_I2S_BASE 0x3ff4F000 -#define DR_REG_UART1_BASE 0x3ff50000 -#define DR_REG_BT_BASE 0x3ff51000 -#define DR_REG_I2C_EXT_BASE 0x3ff53000 -#define DR_REG_UHCI0_BASE 0x3ff54000 -#define DR_REG_SLCHOST_BASE 0x3ff55000 -#define DR_REG_RMT_BASE 0x3ff56000 -#define DR_REG_PCNT_BASE 0x3ff57000 -#define DR_REG_SLC_BASE 0x3ff58000 -#define DR_REG_LEDC_BASE 0x3ff59000 -#define DR_REG_EFUSE_BASE 0x3ff5A000 -#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 -#define DR_REG_NRX_BASE 0x3ff5CC00 -#define DR_REG_BB_BASE 0x3ff5D000 -#define DR_REG_PWM0_BASE 0x3ff5E000 -#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 -#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 -#define DR_REG_RTCMEM0_BASE 0x3ff61000 -#define DR_REG_RTCMEM1_BASE 0x3ff62000 -#define DR_REG_RTCMEM2_BASE 0x3ff63000 -#define DR_REG_SPI2_BASE 0x3ff64000 -#define DR_REG_SPI3_BASE 0x3ff65000 -#define DR_REG_SYSCON_BASE 0x3ff66000 -#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x3ff67000 -#define DR_REG_SDMMC_BASE 0x3ff68000 -#define DR_REG_EMAC_BASE 0x3ff69000 -#define DR_REG_CAN_BASE 0x3ff6B000 -#define DR_REG_PWM1_BASE 0x3ff6C000 -#define DR_REG_I2S1_BASE 0x3ff6D000 -#define DR_REG_UART2_BASE 0x3ff6E000 -#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE - //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32c3/include/soc/periph_defs.h b/components/soc/esp32c3/include/soc/periph_defs.h index 73c9935273..5fa1af8bf8 100644 --- a/components/soc/esp32c3/include/soc/periph_defs.h +++ b/components/soc/esp32c3/include/soc/periph_defs.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32c3/include/soc/reg_base.h b/components/soc/esp32c3/include/soc/reg_base.h new file mode 100644 index 0000000000..ba44a7b2de --- /dev/null +++ b/components/soc/esp32c3/include/soc/reg_base.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_EXTMEM_BASE 0x600c4000 +#define DR_REG_MMU_TABLE 0x600c5000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_GDMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_DPORT_END 0x600d3FFC +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_RTC_I2C_BASE 0x6000e000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_I2S0_BASE 0x6002D000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 +#define DR_REG_AES_XTS_BASE 0x600CC000 diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index bd2d552514..365d6b7452 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,54 +9,12 @@ #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif -#define PRO_CPU_NUM (0) +#include "esp_bit_defs.h" +#include "reg_base.h" -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 -#define DR_REG_MMU_TABLE 0x600c5000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_GDMA_BASE 0x6003f000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -#define DR_REG_DPORT_END 0x600d3FFC -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_RTC_I2C_BASE 0x6000e000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x60008800 -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_I2S0_BASE 0x6002D000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 -#define DR_REG_AES_XTS_BASE 0x600CC000 +#define PRO_CPU_NUM (0) #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) @@ -71,12 +29,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ //write value to register diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h new file mode 100644 index 0000000000..95ce211072 --- /dev/null +++ b/components/soc/esp32h2/include/soc/reg_base.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_EXTMEM_BASE 0x600c4000 +#define DR_REG_MMU_TABLE 0x600c5000 + +#define DR_REG_ITAG_TABLE 0x600c6000 +#define DR_REG_DTAG_TABLE 0x600c8000 +#define DR_REG_ECC_MULT_BASE 0x60039000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_GDMA_BASE 0x6003f000 + +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_GPIO_SD_BASE 0x60004f00 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_FRC_TIMER_BASE 0x60007000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_RTCIO_BASE 0x60008400 +#define DR_REG_SENS_BASE 0x60008800 +#define DR_REG_RTC_I2C_BASE 0x60008C00 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_HINF_BASE 0x6002B000 +#define DR_REG_UHCI1_BASE 0x6000C000 +#define DR_REG_I2S_BASE 0x6000F000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_BT_BASE 0x60011000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_SLCHOST_BASE 0x60019000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_SLC_BASE 0x6002D000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x6001A000 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_PWM_BASE 0x6001E000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 +#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SPI3_BASE 0x60025000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_I2C1_EXT_BASE 0x60027000 +#define DR_REG_SDMMC_BASE 0x60028000 +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_PWM1_BASE 0x6002C000 +#define DR_REG_I2S1_BASE 0x6002D000 +#define DR_REG_UART2_BASE 0x6002E000 +#define DR_REG_PWM2_BASE 0x6002F000 +#define DR_REG_PWM3_BASE 0x60030000 +#define DR_REG_SPI4_BASE 0x60037000 +#define DR_REG_USB_WRAP_BASE 0x60039000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_LCD_CAM_BASE 0x60041000 +#define DR_REG_AES_XTS_BASE 0x600CC000 +#define DR_REG_USB_DEVICE_BASE 0x60043000 +#define DR_REG_CLKRST_BASE 0x6004B000 diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 69a3fa0b9f..970853d758 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,83 +9,13 @@ #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 -#define DR_REG_MMU_TABLE 0x600c5000 - -#define DR_REG_ITAG_TABLE 0x600c6000 -#define DR_REG_DTAG_TABLE 0x600c8000 -#define DR_REG_ECC_MULT_BASE 0x60039000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_GDMA_BASE 0x6003f000 - -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -// #define DR_REG_DPORT_END 0x600d3FFC -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_FRC_TIMER_BASE 0x60007000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 -#define DR_REG_SENS_BASE 0x60008800 -#define DR_REG_RTC_I2C_BASE 0x60008C00 -#define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_HINF_BASE 0x6002B000 -#define DR_REG_UHCI1_BASE 0x6000C000 -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_BT_BASE 0x60011000 -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 -#define DR_REG_SLCHOST_BASE 0x60019000 -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_SLC_BASE 0x6002D000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x6001A000 -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 -#define DR_REG_PWM_BASE 0x6001E000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYS_TIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SPI3_BASE 0x60025000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_I2C1_EXT_BASE 0x60027000 -#define DR_REG_SDMMC_BASE 0x60028000 -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_PWM1_BASE 0x6002C000 -#define DR_REG_I2S1_BASE 0x6002D000 -#define DR_REG_UART2_BASE 0x6002E000 -#define DR_REG_PWM2_BASE 0x6002F000 -#define DR_REG_PWM3_BASE 0x60030000 -#define DR_REG_SPI4_BASE 0x60037000 -#define DR_REG_USB_WRAP_BASE 0x60039000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_LCD_CAM_BASE 0x60041000 -#define DR_REG_AES_XTS_BASE 0x600CC000 -#define DR_REG_USB_DEVICE_BASE 0x60043000 -#define DR_REG_CLKRST_BASE 0x6004B000 - - #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) @@ -99,12 +29,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ //write value to register diff --git a/components/soc/esp32s2/include/soc/periph_defs.h b/components/soc/esp32s2/include/soc/periph_defs.h index 56d19dd110..8d85bd0ab5 100644 --- a/components/soc/esp32s2/include/soc/periph_defs.h +++ b/components/soc/esp32s2/include/soc/periph_defs.h @@ -1,11 +1,10 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_PERIPH_DEFS_H_ -#define _SOC_PERIPH_DEFS_H_ +#pragma once #ifdef __cplusplus extern "C" { @@ -143,11 +142,8 @@ typedef enum { ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ - } periph_interrput_t; #ifdef __cplusplus } #endif - -#endif /* _SOC_PERIPH_DEFS_H_ */ diff --git a/components/soc/esp32s2/include/soc/reg_base.h b/components/soc/esp32s2/include/soc/reg_base.h new file mode 100644 index 0000000000..fae80bec8b --- /dev/null +++ b/components/soc/esp32s2/include/soc/reg_base.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x3f4c0000 +#define DR_REG_SENSITIVE_BASE 0x3f4c1000 +#define DR_REG_INTERRUPT_BASE 0x3f4c2000 +#define DR_REG_DMA_COPY_BASE 0x3f4c3000 +#define DR_REG_EXTMEM_BASE 0x61800000 +#define DR_REG_MMU_TABLE 0x61801000 +#define DR_REG_ITAG_TABLE 0x61802000 +#define DR_REG_DTAG_TABLE 0x61803000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 +#define DR_REG_INTRUSION_BASE 0x3f4d0000 +#define DR_REG_DPORT_END 0x3f4d3FFC +#define DR_REG_UART_BASE 0x3f400000 +#define DR_REG_SPI1_BASE 0x3f402000 +#define DR_REG_SPI0_BASE 0x3f403000 +#define DR_REG_GPIO_BASE 0x3f404000 +#define DR_REG_GPIO_SD_BASE 0x3f404f00 +#define DR_REG_FE2_BASE 0x3f405000 +#define DR_REG_FE_BASE 0x3f406000 +#define DR_REG_FRC_TIMER_BASE 0x3f407000 +#define DR_REG_RTCCNTL_BASE 0x3f408000 +#define DR_REG_RTCIO_BASE 0x3f408400 +#define DR_REG_SENS_BASE 0x3f408800 +#define DR_REG_RTC_I2C_BASE 0x3f408C00 +#define DR_REG_IO_MUX_BASE 0x3f409000 +#define DR_REG_HINF_BASE 0x3f40B000 +#define DR_REG_I2S_BASE 0x3f40F000 +#define DR_REG_UART1_BASE 0x3f410000 +#define DR_REG_I2C_EXT_BASE 0x3f413000 +#define DR_REG_UHCI0_BASE 0x3f414000 +#define DR_REG_SLCHOST_BASE 0x3f415000 +#define DR_REG_RMT_BASE 0x3f416000 +#define DR_REG_PCNT_BASE 0x3f417000 +#define DR_REG_SLC_BASE 0x3f418000 +#define DR_REG_LEDC_BASE 0x3f419000 +#define DR_REG_CP_BASE 0x3f4c3000 +#define DR_REG_EFUSE_BASE 0x3f41A000 +#define DR_REG_NRX_BASE 0x3f41CC00 +#define DR_REG_BB_BASE 0x3f41D000 +#define DR_REG_TIMERGROUP0_BASE 0x3f41F000 +#define DR_REG_TIMERGROUP1_BASE 0x3f420000 +#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000 +#define DR_REG_SYSTIMER_BASE 0x3f423000 +#define DR_REG_SPI2_BASE 0x3f424000 +#define DR_REG_SPI3_BASE 0x3f425000 +#define DR_REG_SYSCON_BASE 0x3f426000 +#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3f427000 +#define DR_REG_SPI4_BASE 0x3f437000 +#define DR_REG_USB_WRAP_BASE 0x3f439000 +#define DR_REG_APB_SARADC_BASE 0x3f440000 +#define DR_REG_USB_BASE 0x60080000 diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index ae4cf0103a..d06c820cf5 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -1,88 +1,23 @@ -// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space -#define DR_REG_SYSTEM_BASE 0x3f4c0000 -#define DR_REG_SENSITIVE_BASE 0x3f4c1000 -#define DR_REG_INTERRUPT_BASE 0x3f4c2000 -#define DR_REG_DMA_COPY_BASE 0x3f4c3000 -#define DR_REG_EXTMEM_BASE 0x61800000 -#define DR_REG_MMU_TABLE 0x61801000 -#define DR_REG_ITAG_TABLE 0x61802000 -#define DR_REG_DTAG_TABLE 0x61803000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 -#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 -#define DR_REG_INTRUSION_BASE 0x3f4d0000 -#define DR_REG_DPORT_END 0x3f4d3FFC -#define DR_REG_UART_BASE 0x3f400000 -#define DR_REG_SPI1_BASE 0x3f402000 -#define DR_REG_SPI0_BASE 0x3f403000 -#define DR_REG_GPIO_BASE 0x3f404000 -#define DR_REG_GPIO_SD_BASE 0x3f404f00 -#define DR_REG_FE2_BASE 0x3f405000 -#define DR_REG_FE_BASE 0x3f406000 -#define DR_REG_FRC_TIMER_BASE 0x3f407000 -#define DR_REG_RTCCNTL_BASE 0x3f408000 -#define DR_REG_RTCIO_BASE 0x3f408400 -#define DR_REG_SENS_BASE 0x3f408800 -#define DR_REG_RTC_I2C_BASE 0x3f408C00 -#define DR_REG_IO_MUX_BASE 0x3f409000 -#define DR_REG_HINF_BASE 0x3f40B000 -#define DR_REG_I2S_BASE 0x3f40F000 -#define DR_REG_UART1_BASE 0x3f410000 -#define DR_REG_I2C_EXT_BASE 0x3f413000 -#define DR_REG_UHCI0_BASE 0x3f414000 -#define DR_REG_SLCHOST_BASE 0x3f415000 -#define DR_REG_RMT_BASE 0x3f416000 -#define DR_REG_PCNT_BASE 0x3f417000 -#define DR_REG_SLC_BASE 0x3f418000 -#define DR_REG_LEDC_BASE 0x3f419000 -#define DR_REG_CP_BASE 0x3f4c3000 -#define DR_REG_EFUSE_BASE 0x3f41A000 -#define DR_REG_NRX_BASE 0x3f41CC00 -#define DR_REG_BB_BASE 0x3f41D000 -#define DR_REG_TIMERGROUP0_BASE 0x3f41F000 -#define DR_REG_TIMERGROUP1_BASE 0x3f420000 -#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000 -#define DR_REG_SYSTIMER_BASE 0x3f423000 -#define DR_REG_SPI2_BASE 0x3f424000 -#define DR_REG_SPI3_BASE 0x3f425000 -#define DR_REG_SYSCON_BASE 0x3f426000 -#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x3f427000 -#define DR_REG_SPI4_BASE 0x3f437000 -#define DR_REG_USB_WRAP_BASE 0x3f439000 -#define DR_REG_APB_SARADC_BASE 0x3f440000 -#define DR_REG_USB_BASE 0x60080000 - #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) @@ -100,12 +35,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) diff --git a/components/soc/esp32s3/include/soc/reg_base.h b/components/soc/esp32s3/include/soc/reg_base.h new file mode 100644 index 0000000000..c0fcb9c2a0 --- /dev/null +++ b/components/soc/esp32s3/include/soc/reg_base.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_GPIO_SD_BASE 0x60004f00 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_EFUSE_BASE 0x60007000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_RTCIO_BASE 0x60008400 +#define DR_REG_SENS_BASE 0x60008800 +#define DR_REG_RTC_I2C_BASE 0x60008C00 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_HINF_BASE 0x6000B000 +#define DR_REG_UHCI1_BASE 0x6000C000 +#define DR_REG_I2S_BASE 0x6000F000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_BT_BASE 0x60011000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_SLCHOST_BASE 0x60015000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_PCNT_BASE 0x60017000 +#define DR_REG_SLC_BASE 0x60018000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_PWM0_BASE 0x6001E000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SPI3_BASE 0x60025000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x60027000 +#define DR_REG_SDMMC_BASE 0x60028000 +#define DR_REG_PERI_BACKUP_BASE 0x6002A000 +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_PWM1_BASE 0x6002C000 +#define DR_REG_I2S1_BASE 0x6002D000 +#define DR_REG_UART2_BASE 0x6002E000 +#define DR_REG_USB_DEVICE_BASE 0x60038000 +#define DR_REG_USB_WRAP_BASE 0x60039000 +#define DR_REG_AES_BASE 0x6003A000 +#define DR_REG_SHA_BASE 0x6003B000 +#define DR_REG_RSA_BASE 0x6003C000 +#define DR_REG_HMAC_BASE 0x6003E000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 +#define DR_REG_GDMA_BASE 0x6003F000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_LCD_CAM_BASE 0x60041000 +#define DR_REG_SYSTEM_BASE 0x600C0000 +#define DR_REG_SENSITIVE_BASE 0x600C1000 +#define DR_REG_INTERRUPT_BASE 0x600C2000 +#define DR_REG_EXTMEM_BASE 0x600C4000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 +#define DR_REG_WORLD_CNTL_BASE 0x600D0000 diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 001f5fe853..69b524a1a0 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -1,114 +1,30 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) #define APP_CPU_NUM (1) #define PRO_CPUID (0xcdcd) #define APP_CPUID (0xabab) -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 - -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 - -#define DR_REG_EFUSE_BASE 0x60007000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 -#define DR_REG_SENS_BASE 0x60008800 -#define DR_REG_RTC_I2C_BASE 0x60008C00 -#define DR_REG_IO_MUX_BASE 0x60009000 - -#define DR_REG_HINF_BASE 0x6000B000 -#define DR_REG_UHCI1_BASE 0x6000C000 - -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 - -#define DR_REG_BT_BASE 0x60011000 - -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 - -#define DR_REG_SLCHOST_BASE 0x60015000 - -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_PCNT_BASE 0x60017000 - -#define DR_REG_SLC_BASE 0x60018000 - -#define DR_REG_LEDC_BASE 0x60019000 - -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 - -#define DR_REG_PWM0_BASE 0x6001E000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SPI3_BASE 0x60025000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x60027000 -#define DR_REG_SDMMC_BASE 0x60028000 - -#define DR_REG_PERI_BACKUP_BASE 0x6002A000 - -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_PWM1_BASE 0x6002C000 -#define DR_REG_I2S1_BASE 0x6002D000 -#define DR_REG_UART2_BASE 0x6002E000 - -#define DR_REG_USB_DEVICE_BASE 0x60038000 -#define DR_REG_USB_WRAP_BASE 0x60039000 -#define DR_REG_AES_BASE 0x6003A000 -#define DR_REG_SHA_BASE 0x6003B000 -#define DR_REG_RSA_BASE 0x6003C000 -#define DR_REG_HMAC_BASE 0x6003E000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 -#define DR_REG_GDMA_BASE 0x6003F000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_LCD_CAM_BASE 0x60041000 - -#define DR_REG_SYSTEM_BASE 0x600C0000 -#define DR_REG_SENSITIVE_BASE 0x600C1000 -#define DR_REG_INTERRUPT_BASE 0x600C2000 - /* Cache configuration */ -#define DR_REG_EXTMEM_BASE 0x600C4000 #define DR_REG_MMU_TABLE 0x600C5000 #define DR_REG_ITAG_TABLE 0x600C6000 #define DR_REG_DTAG_TABLE 0x600C8000 - #define DR_REG_EXT_MEM_ENC 0x600CC000 - -#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 -#define DR_REG_WORLD_CNTL_BASE 0x600D0000 #define DR_REG_DPORT_END 0x600D3FFC diff --git a/components/soc/esp8684/include/soc/reg_base.h b/components/soc/esp8684/include/soc/reg_base.h new file mode 100644 index 0000000000..dede05420a --- /dev/null +++ b/components/soc/esp8684/include/soc/reg_base.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG +#define DR_REG_MMU_TABLE 0x600c5000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_GDMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_DPORT_END 0x600d3FFC +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_RTC_I2C_BASE 0x6000e000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_WDEVLE_BASE 0x60045000 +#define DR_REG_ETM_BIT_BASE 0x6004B000 +#define DR_REG_BLE_TIMER_BASE 0x6004B800 +#define DR_REG_BLE_SEC_BASE 0x6004C000 +#define DR_REG_COEX_BIT_BASE 0x6004C400 +#define DR_REG_I2C_MST_BASE 0x6004E800 diff --git a/components/soc/esp8684/include/soc/soc.h b/components/soc/esp8684/include/soc/soc.h index 1a28265110..b67e82aa71 100644 --- a/components/soc/esp8684/include/soc/soc.h +++ b/components/soc/esp8684/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,47 +9,12 @@ #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG -#define DR_REG_MMU_TABLE 0x600c5000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_GDMA_BASE 0x6003f000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -#define DR_REG_DPORT_END 0x600d3FFC -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_RTC_I2C_BASE 0x6000e000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x60008800 -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_WDEVLE_BASE 0x60045000 -#define DR_REG_ETM_BIT_BASE 0x6004B000 -#define DR_REG_BLE_TIMER_BASE 0x6004B800 -#define DR_REG_BLE_SEC_BASE 0x6004C000 -#define DR_REG_COEX_BIT_BASE 0x6004C400 -#define DR_REG_I2C_MST_BASE 0x6004E800 #define DR_REG_RTC_BLE_TIMER_BASE( i ) ( \ ( (i) == 0 ) ? ( 0x6004E000 ) : \ @@ -71,12 +36,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ //write value to register diff --git a/components/soc/soc_include_legacy_warn.c b/components/soc/soc_include_legacy_warn.c deleted file mode 100644 index 375ba11654..0000000000 --- a/components/soc/soc_include_legacy_warn.c +++ /dev/null @@ -1,5 +0,0 @@ -#include "sdkconfig.h" - -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#warning Legacy including is enabled. This will be deprecated in the future. You can disable this option in the menuconfig. If there are some including errors, please try to include: "soc/soc.h", "soc/soc_memory_layout.h", "driver/gpio.h", or "esp_sleep.h". -#endif diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 6bd985ace1..db5b6e4de5 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1626,7 +1626,6 @@ components/soc/esp32/include/soc/sens_reg.h components/soc/esp32/include/soc/sens_struct.h components/soc/esp32/include/soc/slc_reg.h components/soc/esp32/include/soc/slc_struct.h -components/soc/esp32/include/soc/soc.h components/soc/esp32/include/soc/soc_pins.h components/soc/esp32/include/soc/soc_ulp.h components/soc/esp32/include/soc/spi_pins.h @@ -1689,7 +1688,6 @@ components/soc/esp32c3/include/soc/interrupt_reg.h components/soc/esp32c3/include/soc/ledc_reg.h components/soc/esp32c3/include/soc/mmu.h components/soc/esp32c3/include/soc/nrx_reg.h -components/soc/esp32c3/include/soc/periph_defs.h components/soc/esp32c3/include/soc/reset_reasons.h components/soc/esp32c3/include/soc/rmt_reg.h components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -1839,7 +1837,6 @@ components/soc/esp32s2/include/soc/sdmmc_pins.h components/soc/esp32s2/include/soc/sens_reg.h components/soc/esp32s2/include/soc/sens_struct.h components/soc/esp32s2/include/soc/sensitive_reg.h -components/soc/esp32s2/include/soc/soc.h components/soc/esp32s2/include/soc/soc_pins.h components/soc/esp32s2/include/soc/soc_ulp.h components/soc/esp32s2/include/soc/spi_mem_reg.h @@ -1945,7 +1942,6 @@ components/soc/esp32s3/include/soc/sdmmc_struct.h components/soc/esp32s3/include/soc/sens_reg.h components/soc/esp32s3/include/soc/sensitive_reg.h components/soc/esp32s3/include/soc/sensitive_struct.h -components/soc/esp32s3/include/soc/soc.h components/soc/esp32s3/include/soc/soc_ulp.h components/soc/esp32s3/include/soc/spi_mem_reg.h components/soc/esp32s3/include/soc/spi_mem_struct.h From 869bed1bb503edc9013f7e66d49f18549d562ad6 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 5 Jan 2022 16:17:12 +0800 Subject: [PATCH 5/6] soc: don't expose unstable soc header files in public api --- Kconfig | 19 ----------- components/bootloader/project_include.cmake | 4 --- .../bootloader/subproject/CMakeLists.txt | 5 +-- components/driver/include/driver/gpio.h | 33 +++---------------- components/driver/include/driver/i2s.h | 4 +-- components/driver/include/driver/ledc.h | 3 +- components/driver/include/driver/mcpwm.h | 3 +- components/driver/include/driver/rtc_io.h | 23 +++---------- components/driver/include/driver/sdio_slave.h | 7 ++-- components/driver/include/driver/sigmadelta.h | 16 ++++++--- components/driver/include/driver/spi_common.h | 10 ++---- .../include/driver/spi_common_internal.h | 4 ++- components/driver/include/driver/timer.h | 5 ++- components/driver/rtc_io.c | 20 ++++++++++- components/driver/test/test_sdio.c | 3 +- components/driver/test/test_timer.c | 4 +-- components/driver/twai.c | 3 +- .../port/esp32s2/spiram_psram.c | 3 +- .../port/esp32s3/opiram_psram.c | 3 +- components/esp_lcd/src/esp_lcd_panel_io_i80.c | 3 +- components/esp_pm/include/esp32/pm.h | 22 +++---------- components/esp_pm/include/esp32c3/pm.h | 20 +++-------- components/esp_pm/include/esp32h2/pm.h | 20 +++-------- components/esp_pm/include/esp32s2/pm.h | 20 +++-------- components/esp_pm/include/esp32s3/pm.h | 20 +++-------- components/esp_pm/include/esp8684/pm.h | 4 +-- components/esp_pm/pm_trace.c | 30 +++++++++-------- components/esp_pm/test/test_pm.c | 1 + .../esp_rom/include/esp32/rom/ets_sys.h | 22 +++---------- components/esp_rom/include/esp32/rom/gpio.h | 25 +++----------- .../esp_rom/include/esp32/rom/spi_flash.h | 6 +--- .../common/include/esp_modbus_master.h | 3 +- .../common/include/esp_modbus_slave.h | 3 +- .../riscv/include/freertos/portmacro.h | 3 -- .../xtensa/include/freertos/portmacro.h | 3 -- components/hal/include/hal/gpio_hal.h | 22 +++---------- components/hal/include/hal/gpio_types.h | 5 +-- components/hal/include/hal/rtc_hal.h | 3 +- components/hal/include/hal/sdio_slave_types.h | 20 ++++------- components/hal/include/hal/sigmadelta_types.h | 28 +++------------- .../hal/include/hal/touch_sensor_types.h | 8 ++--- components/heap/include/esp_heap_caps_init.h | 19 +++-------- components/heap/test/test_runtime_heap_reg.c | 3 +- components/log/CMakeLists.txt | 2 +- components/sdmmc/test/test_sd.c | 4 ++- components/sdmmc/test/test_sdio.c | 19 ++++------- components/tinyusb/additions/src/tinyusb.c | 5 +-- components/ulp/include/esp32/ulp.h | 20 ++++------- components/ulp/include/esp32s2/ulp.h | 20 ++++------- components/ulp/include/esp32s2/ulp_riscv.h | 19 +++-------- components/ulp/include/esp32s3/ulp.h | 20 ++++------- docs/en/migration-guides/system.rst | 6 ++++ .../main/uhci_uart_demo.c | 6 ++-- .../spi_slave/receiver/main/app_main.c | 21 ++---------- .../twai_alert_and_recovery_example_main.c | 1 + .../main/ext_flash_fatfs_example_main.c | 1 + tools/ci/check_copyright_ignore.txt | 15 --------- tools/mocks/soc/include/soc/gpio_pins.h | 9 +++++ 58 files changed, 213 insertions(+), 440 deletions(-) create mode 100644 tools/mocks/soc/include/soc/gpio_pins.h diff --git a/Kconfig b/Kconfig index 0ab2e745ee..97d90667e4 100644 --- a/Kconfig +++ b/Kconfig @@ -445,22 +445,3 @@ mainmenu "Espressif IoT Development Framework Configuration" menu "Component config" source "$COMPONENT_KCONFIGS_SOURCE_FILE" endmenu - - menu "Compatibility options" - config LEGACY_INCLUDE_COMMON_HEADERS - bool "Include headers across components as before IDF v4.0" - default n - help - Soc, esp32, and driver components, the most common - components. Some header of these components are included - implicitly by headers of other components before IDF v4.0. - It's not required for high-level components, but still - included through long header chain everywhere. - - This is harmful to the modularity. So it's changed in IDF - v4.0. - - You can still include these headers in a legacy way until it - is totally deprecated by enable this option. - - endmenu #Compatibility options diff --git a/components/bootloader/project_include.cmake b/components/bootloader/project_include.cmake index 2fd12e1dc2..8e52084d53 100644 --- a/components/bootloader/project_include.cmake +++ b/components/bootloader/project_include.cmake @@ -119,10 +119,6 @@ externalproject_add(bootloader -DEXTRA_COMPONENT_DIRS=${CMAKE_CURRENT_LIST_DIR} -DPROJECT_SOURCE_DIR=${PROJECT_SOURCE_DIR} ${sign_key_arg} ${ver_key_arg} - # LEGACY_INCLUDE_COMMON_HEADERS has to be passed in via cache variable since - # the bootloader common component requirements depends on this and - # config variables are not available before project() call. - -DLEGACY_INCLUDE_COMMON_HEADERS=${CONFIG_LEGACY_INCLUDE_COMMON_HEADERS} ${extra_cmake_args} INSTALL_COMMAND "" BUILD_ALWAYS 1 # no easy way around this... diff --git a/components/bootloader/subproject/CMakeLists.txt b/components/bootloader/subproject/CMakeLists.txt index f805f93eb9..0c542ee164 100644 --- a/components/bootloader/subproject/CMakeLists.txt +++ b/components/bootloader/subproject/CMakeLists.txt @@ -52,10 +52,7 @@ endforeach() set(BOOTLOADER_BUILD 1) include("${IDF_PATH}/tools/cmake/project.cmake") -set(common_req log esp_rom esp_common esp_hw_support hal newlib) -if(LEGACY_INCLUDE_COMMON_HEADERS) - list(APPEND common_req soc hal) -endif() +set(common_req log esp_rom esp_common esp_hw_support newlib) idf_build_set_property(__COMPONENT_REQUIRES_COMMON "${common_req}") idf_build_set_property(__OUTPUT_SDKCONFIG 0) project(bootloader) diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index 97e949486a..b03c89e5c5 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -1,47 +1,22 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "sdkconfig.h" #include "esp_err.h" -#include #include "esp_intr_alloc.h" #if !CONFIG_IDF_TARGET_LINUX -#include -#include #include "esp_attr.h" +#include "esp_types.h" #include "soc/soc_caps.h" -#include "soc/gpio_periph.h" #endif // !CONFIG_IDF_TARGET_LINUX #include "hal/gpio_types.h" - -// |================================= WARNING ====================================================== | -// | Including ROM header file in a PUBLIC API file will be REMOVED in the next major release (5.x). | -// | User should include "esp_rom_gpio.h" in their code if they have to use those ROM API. | -// |================================================================================================ | -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/gpio.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/gpio.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/gpio.h" -#elif CONFIG_IDF_TARGET_ESP32C3 -#include "esp32c3/rom/gpio.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/gpio.h" -#elif CONFIG_IDF_TARGET_ESP32H2 -#include "esp32h2/rom/gpio.h" -#elif CONFIG_IDF_TARGET_ESP8684 -#include "esp8684/rom/gpio.h" -#endif - -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#include "soc/rtc_io_reg.h" -#endif +#include "esp_rom_gpio.h" #ifdef __cplusplus extern "C" { diff --git a/components/driver/include/driver/i2s.h b/components/driver/include/driver/i2s.h index 1de790bdba..81ac4f2aea 100644 --- a/components/driver/include/driver/i2s.h +++ b/components/driver/include/driver/i2s.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +10,6 @@ #include "esp_err.h" #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" -#include "soc/i2s_periph.h" -#include "soc/rtc_periph.h" #include "soc/soc_caps.h" #include "hal/i2s_types.h" #include "esp_intr_alloc.h" diff --git a/components/driver/include/driver/ledc.h b/components/driver/include/driver/ledc.h index 89aeab25de..e70f6e25d7 100644 --- a/components/driver/include/driver/ledc.h +++ b/components/driver/include/driver/ledc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,7 +8,6 @@ #include "esp_err.h" #include "esp_intr_alloc.h" -#include "soc/soc.h" #include "hal/ledc_types.h" #include "driver/gpio.h" diff --git a/components/driver/include/driver/mcpwm.h b/components/driver/include/driver/mcpwm.h index 2a4e825f77..aa435a71a3 100644 --- a/components/driver/include/driver/mcpwm.h +++ b/components/driver/include/driver/mcpwm.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,6 @@ #include "soc/soc_caps.h" #if SOC_MCPWM_SUPPORTED #include "esp_err.h" -#include "soc/soc.h" #include "driver/gpio.h" #include "esp_intr_alloc.h" #include "hal/mcpwm_types.h" diff --git a/components/driver/include/driver/rtc_io.h b/components/driver/include/driver/rtc_io.h index cbf32c4fc0..ffa51d5846 100644 --- a/components/driver/include/driver/rtc_io.h +++ b/components/driver/include/driver/rtc_io.h @@ -1,16 +1,15 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _DRIVER_RTC_GPIO_H_ -#define _DRIVER_RTC_GPIO_H_ +#pragma once #include +#include #include "esp_err.h" #include "soc/soc_caps.h" -#include "soc/rtc_io_periph.h" #include "hal/rtc_io_types.h" #include "driver/gpio.h" @@ -25,14 +24,7 @@ extern "C" { * @param gpio_num GPIO number * @return true if GPIO is valid for RTC GPIO use. false otherwise. */ -static inline bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) -{ -#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED - return (gpio_num < GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0); -#else - return false; -#endif -} +bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num); #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio() @@ -45,10 +37,7 @@ static inline bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) * >=0: Index of rtcio. * -1 : The gpio is not rtcio. */ -static inline int rtc_io_number_get(gpio_num_t gpio_num) -{ - return rtc_io_num_map[gpio_num]; -} +int rtc_io_number_get(gpio_num_t gpio_num); /** * @brief Init a GPIO as RTC GPIO @@ -306,5 +295,3 @@ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num); #ifdef __cplusplus } #endif - -#endif diff --git a/components/driver/include/driver/sdio_slave.h b/components/driver/include/driver/sdio_slave.h index e124b5cc86..f9ec3f9c72 100644 --- a/components/driver/include/driver/sdio_slave.h +++ b/components/driver/include/driver/sdio_slave.h @@ -1,17 +1,14 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include "freertos/FreeRTOS.h" #include "esp_err.h" -#include "sys/queue.h" - +#include "freertos/FreeRTOS.h" // for TickType_t #include "hal/sdio_slave_types.h" -#include "soc/sdio_slave_periph.h" #ifdef __cplusplus extern "C" { diff --git a/components/driver/include/driver/sigmadelta.h b/components/driver/include/driver/sigmadelta.h index 17f86b308e..7f7c715953 100644 --- a/components/driver/include/driver/sigmadelta.h +++ b/components/driver/include/driver/sigmadelta.h @@ -1,14 +1,12 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include -#include "soc/soc_caps.h" -#include "soc/sigmadelta_periph.h" +#include "esp_types.h" #include "driver/gpio.h" #include "hal/sigmadelta_types.h" @@ -16,6 +14,16 @@ extern "C" { #endif +/** + * @brief Sigma-delta configure struct + */ +typedef struct { + sigmadelta_channel_t channel; /*!< Sigma-delta channel number */ + int8_t sigmadelta_duty; /*!< Sigma-delta duty, duty ranges from -128 to 127. */ + uint8_t sigmadelta_prescale; /*!< Sigma-delta prescale, prescale ranges from 0 to 255. */ + uint8_t sigmadelta_gpio; /*!< Sigma-delta output io number, refer to gpio.h for more details. */ +} sigmadelta_config_t; + /** * @brief Configure Sigma-delta channel * diff --git a/components/driver/include/driver/spi_common.h b/components/driver/include/driver/spi_common.h index 830b8efd8c..516e94d790 100644 --- a/components/driver/include/driver/spi_common.h +++ b/components/driver/include/driver/spi_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,13 +8,9 @@ #include #include -#include "esp_err.h" -#ifndef SPI_MOCK -#include "soc/lldesc.h" -#include "soc/spi_periph.h" -#endif -#include "hal/spi_types.h" #include "sdkconfig.h" +#include "esp_err.h" +#include "hal/spi_types.h" #ifdef __cplusplus extern "C" diff --git a/components/driver/include/driver/spi_common_internal.h b/components/driver/include/driver/spi_common_internal.h index 0704c7ddd8..baa12ad06d 100644 --- a/components/driver/include/driver/spi_common_internal.h +++ b/components/driver/include/driver/spi_common_internal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -52,6 +52,8 @@ typedef struct spi_bus_lock_dev_t* spi_bus_lock_dev_handle_t; /// Background operation control function typedef void (*bg_ctrl_func_t)(void*); +typedef struct lldesc_s lldesc_t; + /// Attributes of an SPI bus typedef struct { spi_bus_config_t bus_cfg; ///< Config used to initialize the bus diff --git a/components/driver/include/driver/timer.h b/components/driver/include/driver/timer.h index d2290c27f2..61cdcd2c50 100644 --- a/components/driver/include/driver/timer.h +++ b/components/driver/include/driver/timer.h @@ -1,16 +1,15 @@ /* - * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "esp_err.h" #include "esp_attr.h" -#include "soc/soc.h" #include "soc/soc_caps.h" -#include "soc/timer_periph.h" #include "esp_intr_alloc.h" #include "hal/timer_types.h" diff --git a/components/driver/rtc_io.c b/components/driver/rtc_io.c index 84515814a2..0920b0e729 100644 --- a/components/driver/rtc_io.c +++ b/components/driver/rtc_io.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "freertos/timers.h" #include "driver/rtc_io.h" #include "hal/rtc_io_hal.h" +#include "soc/soc_caps.h" static const char __attribute__((__unused__)) *RTCIO_TAG = "RTCIO"; @@ -220,3 +221,20 @@ esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num) } #endif // SOC_RTCIO_WAKE_SUPPORTED + +bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) +{ +#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED + return (gpio_num < GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0); +#else + return false; +#endif +} + +#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED +int rtc_io_number_get(gpio_num_t gpio_num) +{ + return rtc_io_num_map[gpio_num]; +} + +#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED diff --git a/components/driver/test/test_sdio.c b/components/driver/test/test_sdio.c index 49c6ae6ddb..a807645745 100644 --- a/components/driver/test/test_sdio.c +++ b/components/driver/test/test_sdio.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #if SOC_SDMMC_HOST_SUPPORTED && SOC_SDIO_SLAVE_SUPPORTED +#include "soc/sdio_slave_pins.h" #include "driver/sdio_slave.h" #include "driver/sdmmc_host.h" diff --git a/components/driver/test/test_timer.c b/components/driver/test/test_timer.c index c1eaeee4a9..08598fee92 100644 --- a/components/driver/test/test_timer.c +++ b/components/driver/test/test_timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -542,7 +542,7 @@ TEST_CASE("Timer divider", "[hw_timer]") vTaskDelay(1000 / portTICK_PERIOD_MS); all_timer_get_counter_value(set_timer_val, false, comp_time_val); for (int i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) { - TEST_ASSERT_INT_WITHIN(5000, APB_CLK_FREQ / 2, comp_time_val[i]); + TEST_ASSERT_INT_WITHIN(10000, APB_CLK_FREQ / 2, comp_time_val[i]); } all_timer_pause(); diff --git a/components/driver/twai.c b/components/driver/twai.c index 1e4f3ae1c3..74e6c796d2 100644 --- a/components/driver/twai.c +++ b/components/driver/twai.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,6 +21,7 @@ #include "driver/twai.h" #include "soc/soc_caps.h" #include "soc/twai_periph.h" +#include "soc/gpio_sig_map.h" #include "hal/twai_hal.h" #include "esp_rom_gpio.h" diff --git a/components/esp_hw_support/port/esp32s2/spiram_psram.c b/components/esp_hw_support/port/esp32s2/spiram_psram.c index 886e08b045..2b2c345478 100644 --- a/components/esp_hw_support/port/esp32s2/spiram_psram.c +++ b/components/esp_hw_support/port/esp32s2/spiram_psram.c @@ -3,7 +3,7 @@ */ /* - * SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2013-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,7 @@ #include "soc/dport_reg.h" #include "soc/efuse_periph.h" #include "soc/soc_caps.h" +#include "soc/spi_reg.h" #include "soc/io_mux_reg.h" #include "soc/syscon_reg.h" #include "soc/efuse_reg.h" diff --git a/components/esp_hw_support/port/esp32s3/opiram_psram.c b/components/esp_hw_support/port/esp32s3/opiram_psram.c index efcecdbc6b..1f05a386de 100644 --- a/components/esp_hw_support/port/esp32s3/opiram_psram.c +++ b/components/esp_hw_support/port/esp32s3/opiram_psram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,7 @@ #include "esp32s3/rom/opi_flash.h" #include "esp32s3/rom/gpio.h" #include "esp32s3/rom/cache.h" +#include "soc/gpio_periph.h" #include "soc/io_mux_reg.h" #include "soc/dport_reg.h" #include "soc/syscon_reg.h" diff --git a/components/esp_lcd/src/esp_lcd_panel_io_i80.c b/components/esp_lcd/src/esp_lcd_panel_io_i80.c index 6cd03c56a3..bc8c3b0fc2 100644 --- a/components/esp_lcd/src/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/src/esp_lcd_panel_io_i80.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,6 +23,7 @@ #include "esp_lcd_panel_io.h" #include "esp_rom_gpio.h" #include "soc/soc_caps.h" +#include "soc/rtc.h" // for `rtc_clk_xtal_freq_get()` #include "hal/dma_types.h" #include "hal/gpio_hal.h" #include "esp_private/gdma.h" diff --git a/components/esp_pm/include/esp32/pm.h b/components/esp_pm/include/esp32/pm.h index 8c3682cc7e..4933345f09 100644 --- a/components/esp_pm/include/esp32/pm.h +++ b/components/esp_pm/include/esp32/pm.h @@ -1,30 +1,18 @@ -// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include #include -#include "esp_err.h" - -#include "soc/rtc.h" #ifdef __cplusplus extern "C" { #endif - /** * @brief Power management config for ESP32 * diff --git a/components/esp_pm/include/esp32c3/pm.h b/components/esp_pm/include/esp32c3/pm.h index 7ceecd12c1..e2d125d89a 100644 --- a/components/esp_pm/include/esp32c3/pm.h +++ b/components/esp_pm/include/esp32c3/pm.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -18,8 +10,6 @@ #include #include "esp_err.h" -#include "soc/rtc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_pm/include/esp32h2/pm.h b/components/esp_pm/include/esp32h2/pm.h index ce09d8a2b6..89af67ac8f 100644 --- a/components/esp_pm/include/esp32h2/pm.h +++ b/components/esp_pm/include/esp32h2/pm.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -18,8 +10,6 @@ #include #include "esp_err.h" -#include "soc/rtc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_pm/include/esp32s2/pm.h b/components/esp_pm/include/esp32s2/pm.h index dac31e0c9c..8036326ff9 100644 --- a/components/esp_pm/include/esp32s2/pm.h +++ b/components/esp_pm/include/esp32s2/pm.h @@ -1,16 +1,8 @@ -// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -18,8 +10,6 @@ #include #include "esp_err.h" -#include "soc/rtc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_pm/include/esp32s3/pm.h b/components/esp_pm/include/esp32s3/pm.h index 0b29c66aba..51ec7aafb2 100644 --- a/components/esp_pm/include/esp32s3/pm.h +++ b/components/esp_pm/include/esp32s3/pm.h @@ -1,16 +1,8 @@ -// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -18,8 +10,6 @@ #include #include "esp_err.h" -#include "soc/rtc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_pm/include/esp8684/pm.h b/components/esp_pm/include/esp8684/pm.h index 1f3757c2c1..a671e5599a 100644 --- a/components/esp_pm/include/esp8684/pm.h +++ b/components/esp_pm/include/esp8684/pm.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +10,6 @@ #include #include "esp_err.h" -#include "soc/rtc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_pm/pm_trace.c b/components/esp_pm/pm_trace.c index f3b2d10e22..3100a257ca 100644 --- a/components/esp_pm/pm_trace.c +++ b/components/esp_pm/pm_trace.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,8 @@ #include "esp_private/pm_trace.h" #include "driver/gpio.h" +#include "soc/soc.h" +#include "soc/gpio_reg.h" /* GPIOs to use for tracing of esp_pm events. * Two entries in the array for each type, one for each CPU. @@ -14,25 +16,25 @@ */ static const int DRAM_ATTR s_trace_io[] = { #if !defined(CONFIG_IDF_TARGET_ESP32C3) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP8684) - BIT(4), BIT(5), // ESP_PM_TRACE_IDLE - BIT(16), BIT(17), // ESP_PM_TRACE_TICK - BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH - BIT(19), BIT(19), // ESP_PM_TRACE_CCOMPARE_UPDATE - BIT(25), BIT(26), // ESP_PM_TRACE_ISR_HOOK - BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP + BIT(4), BIT(5), // ESP_PM_TRACE_IDLE + BIT(16), BIT(17), // ESP_PM_TRACE_TICK + BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH + BIT(19), BIT(19), // ESP_PM_TRACE_CCOMPARE_UPDATE + BIT(25), BIT(26), // ESP_PM_TRACE_ISR_HOOK + BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP #else - BIT(2), BIT(3), // ESP_PM_TRACE_IDLE - BIT(4), BIT(5), // ESP_PM_TRACE_TICK - BIT(6), BIT(6), // ESP_PM_TRACE_FREQ_SWITCH - BIT(7), BIT(7), // ESP_PM_TRACE_CCOMPARE_UPDATE - BIT(8), BIT(9), // ESP_PM_TRACE_ISR_HOOK - BIT(18), BIT(18), // ESP_PM_TRACE_SLEEP + BIT(2), BIT(3), // ESP_PM_TRACE_IDLE + BIT(4), BIT(5), // ESP_PM_TRACE_TICK + BIT(6), BIT(6), // ESP_PM_TRACE_FREQ_SWITCH + BIT(7), BIT(7), // ESP_PM_TRACE_CCOMPARE_UPDATE + BIT(8), BIT(9), // ESP_PM_TRACE_ISR_HOOK + BIT(18), BIT(18), // ESP_PM_TRACE_SLEEP #endif }; void esp_pm_trace_init(void) { - for (size_t i = 0; i < sizeof(s_trace_io)/sizeof(s_trace_io[0]); ++i) { + for (size_t i = 0; i < sizeof(s_trace_io) / sizeof(s_trace_io[0]); ++i) { int io = __builtin_ffs(s_trace_io[i]); if (io == 0) { continue; diff --git a/components/esp_pm/test/test_pm.c b/components/esp_pm/test/test_pm.c index fd9774b334..2d7b58d57a 100644 --- a/components/esp_pm/test/test_pm.c +++ b/components/esp_pm/test/test_pm.c @@ -12,6 +12,7 @@ #include "esp_log.h" #include "driver/timer.h" #include "driver/rtc_io.h" +#include "soc/rtc.h" #include "soc/rtc_periph.h" #include "esp_rom_sys.h" #include "esp_private/esp_clk.h" diff --git a/components/esp_rom/include/esp32/rom/ets_sys.h b/components/esp_rom/include/esp32/rom/ets_sys.h index 3485f0d406..3760c84f65 100644 --- a/components/esp_rom/include/esp32/rom/ets_sys.h +++ b/components/esp_rom/include/esp32/rom/ets_sys.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_ETS_SYS_H_ #define _ROM_ETS_SYS_H_ @@ -21,10 +13,6 @@ #include "sdkconfig.h" -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#include "soc/soc.h" -#endif - #ifndef CONFIG_IDF_TARGET_ESP32 #error "This header should only be included when building for ESP32" #endif diff --git a/components/esp_rom/include/esp32/rom/gpio.h b/components/esp_rom/include/esp32/rom/gpio.h index ef6e3c512a..d018ecbf00 100644 --- a/components/esp_rom/include/esp32/rom/gpio.h +++ b/components/esp_rom/include/esp32/rom/gpio.h @@ -1,32 +1,17 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_GPIO_H_ #define _ROM_GPIO_H_ #include #include - #include "esp_attr.h" - #include "sdkconfig.h" -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#include "soc/gpio_reg.h" -#include "soc/soc_caps.h" -#endif - #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_rom/include/esp32/rom/spi_flash.h b/components/esp_rom/include/esp32/rom/spi_flash.h index 2192ca2417..a492c055bc 100644 --- a/components/esp_rom/include/esp32/rom/spi_flash.h +++ b/components/esp_rom/include/esp32/rom/spi_flash.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,10 +12,6 @@ #include "sdkconfig.h" #include "esp_rom_spiflash.h" -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#include "soc/spi_reg.h" -#endif - #ifdef __cplusplus extern "C" { #endif diff --git a/components/freemodbus/common/include/esp_modbus_master.h b/components/freemodbus/common/include/esp_modbus_master.h index 433e143c0f..9f4bd4735a 100644 --- a/components/freemodbus/common/include/esp_modbus_master.h +++ b/components/freemodbus/common/include/esp_modbus_master.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,6 @@ #include // for standard int types definition #include // for NULL and std defines -#include "soc/soc.h" // for BITN definitions #include "esp_modbus_common.h" // for common types #ifdef __cplusplus diff --git a/components/freemodbus/common/include/esp_modbus_slave.h b/components/freemodbus/common/include/esp_modbus_slave.h index 13fd456928..8e958c4fd9 100644 --- a/components/freemodbus/common/include/esp_modbus_slave.h +++ b/components/freemodbus/common/include/esp_modbus_slave.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ // Public interface header for slave #include // for standard int types definition #include // for NULL and std defines -#include "soc/soc.h" // for BITN definitions #include "freertos/FreeRTOS.h" // for task creation and queues access #include "freertos/event_groups.h" // for event groups #include "esp_modbus_common.h" // for common types diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h index 5c903ccfd9..a6bcaf5234 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h @@ -47,9 +47,6 @@ /* [refactor-todo] These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */ #include -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#include "soc/soc_memory_layout.h" -#endif #ifdef __cplusplus extern "C" { diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h index 68fc125e4b..00a4b59b83 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h @@ -54,9 +54,6 @@ #include #include #include -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#include "soc/soc_memory_layout.h" -#endif #ifdef __cplusplus extern "C" { diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index 018b4be128..f31a355cbe 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -27,10 +19,6 @@ #include "hal/gpio_ll.h" #include "hal/gpio_types.h" -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#include "soc/rtc_io_reg.h" -#endif - #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index 827132c24e..09abb739b5 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -1,13 +1,14 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include "soc/gpio_periph.h" +#include "sdkconfig.h" #include "soc/soc_caps.h" +#include "esp_bit_defs.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/include/hal/rtc_hal.h b/components/hal/include/hal/rtc_hal.h index 602f0737ac..14c99b054a 100644 --- a/components/hal/include/hal/rtc_hal.h +++ b/components/hal/include/hal/rtc_hal.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include "soc/soc_caps.h" #include "hal/gpio_types.h" #include "hal/rtc_cntl_ll.h" diff --git a/components/hal/include/hal/sdio_slave_types.h b/components/hal/include/hal/sdio_slave_types.h index 60e08456fc..dc48dbeb66 100644 --- a/components/hal/include/hal/sdio_slave_types.h +++ b/components/hal/include/hal/sdio_slave_types.h @@ -1,20 +1,12 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#include "soc/soc.h" +#include "esp_bit_defs.h" /// Mask of interrupts sending to the host. typedef enum { diff --git a/components/hal/include/hal/sigmadelta_types.h b/components/hal/include/hal/sigmadelta_types.h index 81023905d6..646729258c 100644 --- a/components/hal/include/hal/sigmadelta_types.h +++ b/components/hal/include/hal/sigmadelta_types.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -47,16 +39,6 @@ typedef enum { SIGMADELTA_CHANNEL_MAX, /*!< Sigma-delta channel max */ } sigmadelta_channel_t; -/** - * @brief Sigma-delta configure struct - */ -typedef struct { - sigmadelta_channel_t channel; /*!< Sigma-delta channel number */ - int8_t sigmadelta_duty; /*!< Sigma-delta duty, duty ranges from -128 to 127. */ - uint8_t sigmadelta_prescale; /*!< Sigma-delta prescale, prescale ranges from 0 to 255. */ - uint8_t sigmadelta_gpio; /*!< Sigma-delta output io number, refer to gpio.h for more details. */ -} sigmadelta_config_t; - #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/touch_sensor_types.h b/components/hal/include/hal/touch_sensor_types.h index 9085f5eecd..868e79118f 100644 --- a/components/hal/include/hal/touch_sensor_types.h +++ b/components/hal/include/hal/touch_sensor_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,10 +7,10 @@ #pragma once #include -#include "esp_attr.h" -#include "soc/soc.h" -#include "soc/soc_caps.h" #include "sdkconfig.h" +#include "esp_attr.h" +#include "esp_bit_defs.h" +#include "soc/soc_caps.h" /** Touch pad channel */ typedef enum { diff --git a/components/heap/include/esp_heap_caps_init.h b/components/heap/include/esp_heap_caps_init.h index 74e8cb9016..50aab38493 100644 --- a/components/heap/include/esp_heap_caps_init.h +++ b/components/heap/include/esp_heap_caps_init.h @@ -1,21 +1,12 @@ -// Copyright 2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include "esp_err.h" #include "esp_heap_caps.h" -#include "soc/soc_memory_layout.h" #ifdef __cplusplus extern "C" { diff --git a/components/heap/test/test_runtime_heap_reg.c b/components/heap/test/test_runtime_heap_reg.c index 92e81d8fdc..305177bcd5 100644 --- a/components/heap/test/test_runtime_heap_reg.c +++ b/components/heap/test/test_runtime_heap_reg.c @@ -3,10 +3,11 @@ */ #include +#include #include "unity.h" #include "esp_heap_caps_init.h" #include "esp_system.h" -#include +#include "heap_memory_layout.h" /* NOTE: This is not a well-formed unit test, it leaks memory */ diff --git a/components/log/CMakeLists.txt b/components/log/CMakeLists.txt index b57770a234..ff293315f2 100644 --- a/components/log/CMakeLists.txt +++ b/components/log/CMakeLists.txt @@ -7,7 +7,7 @@ if(${target} STREQUAL "linux") list(APPEND srcs "log_linux.c") else() list(APPEND srcs "log_buffers.c") - list(APPEND priv_requires soc) + list(APPEND priv_requires soc hal) endif() idf_component_register(SRCS ${srcs} diff --git a/components/sdmmc/test/test_sd.c b/components/sdmmc/test/test_sd.c index 3a47b9b0a8..ca3f6934d7 100644 --- a/components/sdmmc/test/test_sd.c +++ b/components/sdmmc/test/test_sd.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,8 @@ #include "esp_heap_caps.h" #include "esp_rom_gpio.h" #include "test_utils.h" +#include "soc/gpio_sig_map.h" +#include "soc/gpio_reg.h" // Currently no runners for S3 #define WITH_SD_TEST (SOC_SDMMC_HOST_SUPPORTED && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)) diff --git a/components/sdmmc/test/test_sdio.c b/components/sdmmc/test/test_sdio.c index ecafb1639c..a71d1f440a 100644 --- a/components/sdmmc/test/test_sdio.c +++ b/components/sdmmc/test/test_sdio.c @@ -1,16 +1,8 @@ -// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/soc_caps.h" #if SOC_SDMMC_HOST_SUPPORTED @@ -27,6 +19,7 @@ #include "driver/sdmmc_defs.h" #include "sdmmc_cmd.h" #include "unity.h" +#include "soc/gpio_reg.h" /* Second ESP32 board attached as follows: * Master Slave diff --git a/components/tinyusb/additions/src/tinyusb.c b/components/tinyusb/additions/src/tinyusb.c index 72b1b612fc..c5186eb392 100644 --- a/components/tinyusb/additions/src/tinyusb.c +++ b/components/tinyusb/additions/src/tinyusb.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,7 @@ #include "hal/usb_hal.h" #include "soc/gpio_periph.h" #include "soc/usb_periph.h" +#include "soc/gpio_pins.h" #include "tinyusb.h" #include "descriptors_control.h" #include "tusb.h" @@ -34,7 +35,7 @@ static void configure_pins(usb_hal_context_t *usb) esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false); } else { esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false); - if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) { + if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) { gpio_ll_input_enable(&GPIO, iopin->pin); } } diff --git a/components/ulp/include/esp32/ulp.h b/components/ulp/include/esp32/ulp.h index e5d673a23c..764dd1102e 100644 --- a/components/ulp/include/esp32/ulp.h +++ b/components/ulp/include/esp32/ulp.h @@ -1,24 +1,16 @@ -// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include #include #include #include "esp_err.h" -#include "soc/soc.h" #include "ulp_common.h" +#include "soc/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/components/ulp/include/esp32s2/ulp.h b/components/ulp/include/esp32s2/ulp.h index 04d38c457e..3d92485144 100644 --- a/components/ulp/include/esp32s2/ulp.h +++ b/components/ulp/include/esp32s2/ulp.h @@ -1,24 +1,16 @@ -// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include #include #include #include "esp_err.h" -#include "soc/soc.h" #include "ulp_common.h" +#include "soc/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/components/ulp/include/esp32s2/ulp_riscv.h b/components/ulp/include/esp32s2/ulp_riscv.h index f98f2acdac..dcb539d85c 100644 --- a/components/ulp/include/esp32s2/ulp_riscv.h +++ b/components/ulp/include/esp32s2/ulp_riscv.h @@ -1,23 +1,14 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include #include #include #include "esp_err.h" -#include "soc/soc.h" #include "ulp_common.h" /** diff --git a/components/ulp/include/esp32s3/ulp.h b/components/ulp/include/esp32s3/ulp.h index 9207a00ead..de0fd290bf 100644 --- a/components/ulp/include/esp32s3/ulp.h +++ b/components/ulp/include/esp32s3/ulp.h @@ -1,24 +1,16 @@ -// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include #include #include #include "esp_err.h" -#include "soc/soc.h" #include "ulp_common.h" +#include "soc/reg_base.h" #ifdef __cplusplus extern "C" { diff --git a/docs/en/migration-guides/system.rst b/docs/en/migration-guides/system.rst index d9237fa975..4d3bde29ff 100644 --- a/docs/en/migration-guides/system.rst +++ b/docs/en/migration-guides/system.rst @@ -45,3 +45,9 @@ ESP HW Support - The header files ``soc/cpu.h`` have been deleted and deprecated CPU util functions have been removed. ESP-IDF developers should include ``esp_cpu.h`` instead for equivalent functions. - The header file ``esp_intr.h`` has been deleted. Please include ``esp_intr_alloc.h`` to allocate and manipulate interrupts. - The header file ``esp_panic.h`` has been deleted. ESP-IDF developers should include ``esp_private/panic_reason.h`` to get supported panic reasons. And should include ``esp_debug_helpers.h`` to use any debug related helper functions, e.g. print backtrace. + +SOC dependency +-------------- + +- Public API headers who are listed in the Doxyfiles won't expose unstable and unnecessary soc header files like ``soc/soc.h``, ``soc/rtc.h``. That means, the user has to explicitly include them in their code if these "missing" header files are still wanted. +- Kconfig option ``LEGACY_INCLUDE_COMMON_HEADERS`` is also removed. diff --git a/examples/bluetooth/hci/controller_hci_uart_esp32c3/main/uhci_uart_demo.c b/examples/bluetooth/hci/controller_hci_uart_esp32c3/main/uhci_uart_demo.c index 03df6fe779..b824f0a04a 100644 --- a/examples/bluetooth/hci/controller_hci_uart_esp32c3/main/uhci_uart_demo.c +++ b/examples/bluetooth/hci/controller_hci_uart_esp32c3/main/uhci_uart_demo.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -166,7 +166,7 @@ static IRAM_ATTR bool hci_uart_tl_tx_eof_callback(gdma_channel_handle_t dma_chan static void uart_gpio_set(void) { gpio_config_t io_output_conf = { - .intr_type = GPIO_PIN_INTR_DISABLE, //disable interrupt + .intr_type = GPIO_INTR_DISABLE, //disable interrupt .mode = GPIO_MODE_OUTPUT, // output mode .pin_bit_mask = GPIO_OUTPUT_PIN_SEL, // bit mask of the output pins .pull_down_en = 0, // disable pull-down mode @@ -175,7 +175,7 @@ static void uart_gpio_set(void) gpio_config(&io_output_conf); gpio_config_t io_input_conf = { - .intr_type = GPIO_PIN_INTR_DISABLE, //disable interrupt + .intr_type = GPIO_INTR_DISABLE, //disable interrupt .mode = GPIO_MODE_INPUT, // input mode .pin_bit_mask = GPIO_INPUT_PIN_SEL, // bit mask of the input pins .pull_down_en = 0, // disable pull-down mode diff --git a/examples/peripherals/spi_slave/receiver/main/app_main.c b/examples/peripherals/spi_slave/receiver/main/app_main.c index 0ea85cf207..1eca638207 100644 --- a/examples/peripherals/spi_slave/receiver/main/app_main.c +++ b/examples/peripherals/spi_slave/receiver/main/app_main.c @@ -13,27 +13,12 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "freertos/semphr.h" -#include "freertos/queue.h" -#include "lwip/sockets.h" -#include "lwip/dns.h" -#include "lwip/netdb.h" -#include "lwip/igmp.h" - -#include "esp_wifi.h" -#include "esp_system.h" -#include "esp_event.h" -#include "nvs_flash.h" -#include "soc/rtc_periph.h" -#include "driver/spi_slave.h" #include "esp_log.h" -#include "esp_spi_flash.h" +#include "driver/spi_slave.h" #include "driver/gpio.h" - - /* SPI receiver (slave) example. @@ -85,12 +70,12 @@ Pins in use. The SPI Master can use the GPIO mux, so feel free to change these i //Called after a transaction is queued and ready for pickup by master. We use this to set the handshake line high. void my_post_setup_cb(spi_slave_transaction_t *trans) { - WRITE_PERI_REG(GPIO_OUT_W1TS_REG, (1< Date: Wed, 5 Jan 2022 15:09:09 +0800 Subject: [PATCH 6/6] soc: remove dport register assert for esp32s2 Closes https://github.com/espressif/esp-idf/issues/8176 --- components/soc/esp32s2/include/soc/soc.h | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index d06c820cf5..caa446355a 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -37,59 +37,43 @@ #ifndef __ASSEMBLER__ -#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) - -#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM ) -#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); -#else -#define ASSERT_IF_DPORT_REG(_r, OP) -#endif - //write value to register #define REG_WRITE(_r, _v) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_WRITE); \ (*(volatile uint32_t *)(_r)) = (_v); \ }) //read value from register #define REG_READ(_r) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_READ); \ (*(volatile uint32_t *)(_r)); \ }) //get bit or get bits from register #define REG_GET_BIT(_r, _b) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \ (*(volatile uint32_t*)(_r) & (_b)); \ }) //set bit or set bits to register #define REG_SET_BIT(_r, _b) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \ (*(volatile uint32_t*)(_r) |= (_b)); \ }) //clear bit or clear bits of register #define REG_CLR_BIT(_r, _b) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \ (*(volatile uint32_t*)(_r) &= ~(_b)); \ }) //set bits of register controlled by mask #define REG_SET_BITS(_r, _b, _m) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \ (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ }) //get field from register, uses field _S & _V to determine mask #define REG_GET_FIELD(_r, _f) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \ ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ }) //set field of a register from variable, uses field _S & _V to determine mask #define REG_SET_FIELD(_r, _f, _v) ({ \ - ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \ (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ }) @@ -113,49 +97,41 @@ //read value from register #define READ_PERI_REG(addr) ({ \ - ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \ (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ }) //write value to register #define WRITE_PERI_REG(addr, val) ({ \ - ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \ (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ }) //clear bits of register controlled by mask #define CLEAR_PERI_REG_MASK(reg, mask) ({ \ - ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \ WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ }) //set bits of register controlled by mask #define SET_PERI_REG_MASK(reg, mask) ({ \ - ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \ WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ }) //get bits of register controlled by mask #define GET_PERI_REG_MASK(reg, mask) ({ \ - ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \ (READ_PERI_REG(reg) & (mask)); \ }) //get bits of register controlled by highest bit and lowest bit #define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ - ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \ ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ }) //set bits of register controlled by mask and shift #define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ - ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \ (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ }) //get field of register #define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ - ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \ ((READ_PERI_REG(reg)>>(shift))&(mask)); \ })