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Merge branch 'feature/support_i2s_on_p4' into 'master'

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feat(i2s): support i2s on esp32p4

Closes IDF-6508

See merge request espressif/esp-idf!24280
This commit is contained in:
Kevin (Lao Kaiyao)
2023-09-29 00:50:04 +08:00
parent 4a40c7bb5e e1039f9ce2
commit 4c6f4b39f1
58 changed files with 2560 additions and 736 deletions
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16
components/hal/esp32p4/include/hal/clk_gate_ll.h
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@@ -36,12 +36,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN;
case PERIPH_I2C1_MODULE:
return HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN;
case PERIPH_I2S0_MODULE:
return HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN | HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN;
case PERIPH_I2S1_MODULE:
return HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN | HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN;
case PERIPH_I2S2_MODULE:
return HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN | HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN;
case PERIPH_LCD_MODULE:
return HP_SYS_CLKRST_REG_LCD_CLK_EN;
case PERIPH_UART0_MODULE:
@@ -151,12 +145,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return HP_SYS_CLKRST_REG_RST_EN_CAN2;
case PERIPH_LEDC_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_LEDC;
case PERIPH_I2S0_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_I2S0_APB;
case PERIPH_I2S1_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_I2S1_APB;
case PERIPH_I2S2_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_I2S2_APB;
case PERIPH_GPSPI2_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_SPI2;
case PERIPH_GPSPI3_MODULE:
@@ -294,10 +282,6 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
case PERIPH_TWAI1_MODULE:
case PERIPH_TWAI2_MODULE:
case PERIPH_LEDC_MODULE:
case PERIPH_I2S0_MODULE:
return HP_SYS_CLKRST_HP_RST_EN1_REG;
case PERIPH_I2S1_MODULE:
case PERIPH_I2S2_MODULE:
case PERIPH_GPSPI2_MODULE:
case PERIPH_GPSPI3_MODULE:
case PERIPH_CAM_MODULE:

10
components/hal/esp32p4/include/hal/clk_tree_ll.h
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@@ -30,6 +30,16 @@ extern "C" {
#define CLK_LL_PLL_480M_FREQ_MHZ (480)
/* APLL multiplier output frequency range */
// TODO: IDF-7526 check if the APLL frequency range is same as before
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
#define CLK_LL_APLL_MULTIPLIER_MIN_HZ (350000000) // 350 MHz
#define CLK_LL_APLL_MULTIPLIER_MAX_HZ (500000000) // 500 MHz
/* APLL output frequency range */
#define CLK_LL_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define CLK_LL_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
.dac = 3, \
.dres = 3, \

1402
components/hal/esp32p4/include/hal/i2s_ll.h Normal file
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