diff --git a/components/esp_hw_support/port/esp32s3/opiram_psram.c b/components/esp_hw_support/port/esp32s3/opiram_psram.c
index f0647cc259..e7a8396623 100644
--- a/components/esp_hw_support/port/esp32s3/opiram_psram.c
+++ b/components/esp_hw_support/port/esp32s3/opiram_psram.c
@@ -215,7 +215,7 @@ static void IRAM_ATTR s_print_psram_info(opi_psram_mode_reg_t *reg_val)
                                                                                 reg_val->mr0.drive_str == 0x02 ? 4 : 8);
 }
 
-static void psram_set_cs_timing(void)
+static void IRAM_ATTR psram_set_cs_timing(void)
 {
     //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay registers for PSRAM, so we only need to set SPI0 related registers here
     SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M);
diff --git a/components/esp_hw_support/port/esp32s3/spiram_psram.c b/components/esp_hw_support/port/esp32s3/spiram_psram.c
index d84ab3f0e0..ecd10f08d9 100644
--- a/components/esp_hw_support/port/esp32s3/spiram_psram.c
+++ b/components/esp_hw_support/port/esp32s3/spiram_psram.c
@@ -290,7 +290,7 @@ static void IRAM_ATTR psram_enable_qio_mode(int spi_num)
     false);                           /* whether is program/erase operation */
 }
 
-static void psram_set_cs_timing(void)
+static void IRAM_ATTR psram_set_cs_timing(void)
 {
     //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here
     SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S);