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https://github.com/espressif/esp-idf.git
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adc: support adc dma driver on all chips
This commit is contained in:
Armando
committed by
Armando (Dou Yiwen)
Armando (Dou Yiwen)
parent
5ddce053ea
commit
4dc0d6b2fe
@@ -1,16 +1,8 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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@@ -54,6 +46,22 @@ typedef enum {
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ADC_RTC_DATA_FAIL = -1,
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} adc_ll_rtc_raw_data_t;
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typedef enum {
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ADC_LL_CTRL_DIG = 0, ///< For ADC1. Select DIG controller.
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ADC_LL_CTRL_ARB = 1, ///< For ADC2. The controller is selected by the arbiter.
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} adc_ll_controller_t;
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/**
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* @brief ADC digital controller (DMA mode) work mode.
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*
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* @note The conversion mode affects the sampling frequency:
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* ESP32H2 only support ALTER_UNIT mode
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* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
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*/
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typedef enum {
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ADC_LL_DIGI_CONV_ALTER_UNIT = 0, // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
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} adc_ll_digi_convert_mode_t;
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//These values should be set according to the HW
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typedef enum {
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ADC_LL_INTR_THRES1_LOW = BIT(26),
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@@ -65,21 +73,17 @@ typedef enum {
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} adc_ll_intr_t;
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FLAG_ATTR(adc_ll_intr_t)
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/**
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* @brief ADC controller type selection.
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*
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* @note For ADC2, use the force option with care. The system power consumption detection will use ADC2.
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* If it is forced to switch to another controller, it may cause the system to obtain incorrect values.
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* @note Normally, there is no need to switch the controller manually.
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*/
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typedef enum {
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ADC_CTRL_RTC = 0, /*!<For ADC1. Select RTC controller. For ADC2. The controller is selected by the arbiter. Arbiter in default mode. */
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ADC_CTRL_DIG = 2, /*!<For ADC1. Select DIG controller. For ADC2. The controller is selected by the arbiter. Arbiter in default mode. */
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ADC2_CTRL_PWDET = 3,/*!<For ADC2. The controller is selected by the arbiter. Arbiter in default mode. */
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ADC2_CTRL_FORCE_PWDET = 3, /*!<For ADC2. Arbiter in shield mode. Force select Wi-Fi controller work. */
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ADC2_CTRL_FORCE_RTC = 4, /*!<For ADC2. Arbiter in shield mode. Force select RTC controller work. */
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ADC2_CTRL_FORCE_DIG = 6, /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
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} adc_ll_controller_t;
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typedef struct {
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union {
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struct {
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uint8_t atten: 2;
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uint8_t channel: 3;
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uint8_t unit: 1;
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uint8_t reserved: 2;
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};
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uint8_t val;
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};
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} __attribute__((packed)) adc_ll_digi_pattern_table_t;
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/*---------------------------------------------------------------
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Digital controller setting
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@@ -157,6 +161,18 @@ static inline void adc_ll_digi_convert_limit_disable(void)
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APB_SARADC.ctrl2.meas_num_limit = 0;
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}
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/**
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* Set adc conversion mode for digital controller.
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*
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* @note ESP32H2 only support ADC1 single mode.
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*
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* @param mode Conversion mode select.
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*/
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static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
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{
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//ESP32H2 only supports ADC_CONV_ALTER_UNIT mode
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}
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/**
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* Set pattern table length for digital controller.
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* The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection,
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@@ -181,16 +197,18 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
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* @param pattern_index Items index. Range: 0 ~ 7.
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* @param pattern Stored conversion rules.
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*/
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static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern)
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static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
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{
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uint32_t tab;
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uint8_t index = pattern_index / 4;
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uint8_t offset = (pattern_index % 4) * 6;
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adc_ll_digi_pattern_table_t pattern = {0};
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tab = APB_SARADC.sar_patt_tab[index].sar_patt_tab1; // Read old register value
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tab &= (~(0xFC0000 >> offset)); // Clear old data
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tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data
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APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back
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pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5);
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tab = APB_SARADC.sar_patt_tab[index].sar_patt_tab1; // Read old register value
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tab &= (~(0xFC0000 >> offset)); // Clear old data
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tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data
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APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back
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}
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/**
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@@ -260,9 +278,9 @@ static inline void adc_ll_digi_trigger_disable(void)
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/**
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* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
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* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
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* Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1).
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*
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* @param div_num Division factor. Range: 1 ~ 255.
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* @param div_num Division factor. Range: 0 ~ 255.
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* @param div_b Division factor. Range: 1 ~ 63.
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* @param div_a Division factor. Range: 0 ~ 63.
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*/
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@@ -278,7 +296,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
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*
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* @param use_apll true: use APLL clock; false: use APB clock.
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*/
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static inline void adc_ll_digi_controller_clk_enable(bool use_apll)
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static inline void adc_ll_digi_clk_sel(bool use_apll)
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{
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if (use_apll) {
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APB_SARADC.apb_adc_clkm_conf.clk_sel = 1; // APLL clock
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@@ -445,8 +463,7 @@ static inline void adc_ll_digi_reset(void)
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static inline void adc_ll_pwdet_set_cct(uint32_t cct)
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{
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/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
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// RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct;
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abort(); // ESP32H2-TODO: IDF-3389
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abort();
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}
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/**
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@@ -458,9 +475,7 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct)
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static inline uint32_t adc_ll_pwdet_get_cct(void)
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{
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/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
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// return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
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abort(); // ESP32H2-TODO: IDF-3389
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return 0;
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abort();
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}
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/**
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@@ -497,8 +512,8 @@ static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n,
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*/
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static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
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{
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// /* Bit1 0:Fsm 1: SW mode
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// Bit0 0:SW mode power down 1: SW mode power on */
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/* Bit1 0:Fsm 1: SW mode
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Bit0 0:SW mode power down 1: SW mode power on */
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if (manage == ADC_POWER_SW_ON) {
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APB_SARADC.ctrl.sar_clk_gated = 1;
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APB_SARADC.ctrl.xpd_sar_force = 3;
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@@ -506,30 +521,14 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
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APB_SARADC.ctrl.sar_clk_gated = 1;
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APB_SARADC.ctrl.xpd_sar_force = 0;
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} else if (manage == ADC_POWER_SW_OFF) {
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APB_SARADC.ctrl.xpd_sar_force = 2;
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APB_SARADC.ctrl.sar_clk_gated = 0;
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APB_SARADC.ctrl.xpd_sar_force = 2;
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}
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}
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/**
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* Get ADC module power management.
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*
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* @return
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* - ADC power status.
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*/
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static inline adc_ll_power_t adc_ll_get_power_manage(void)
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static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
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{
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/* Bit1 0:Fsm 1: SW mode
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Bit0 0:SW mode power down 1: SW mode power on */
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adc_ll_power_t manage;
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if (APB_SARADC.ctrl.xpd_sar_force == 3) {
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manage = ADC_POWER_SW_ON;
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} else if (APB_SARADC.ctrl.xpd_sar_force == 2) {
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manage = ADC_POWER_SW_OFF;
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} else {
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manage = ADC_POWER_BY_FSM;
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}
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return manage;
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//Not used on ESP32H2
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}
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/**
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@@ -688,7 +687,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
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*/
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static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
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{
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// ESP32H2-TODO: IDF-3389
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abort();
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}
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/*---------------------------------------------------------------
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