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unit_test:refactor ref clock to use RMT carrier

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This commit is contained in:
morris
2020-08-14 13:47:08 +08:00
parent 9bc2773b22
commit 4dd649d533
6 changed files with 109 additions and 182 deletions
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85
components/esp32/test/test_delay.c
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@@ -1,85 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include "unity.h"
#include "esp_rom_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "test_utils.h"
typedef struct {
int delay_us;
int method;
int result;
SemaphoreHandle_t done;
} delay_test_arg_t;
static void test_delay_task(void* p)
{
delay_test_arg_t* arg = (delay_test_arg_t*) p;
vTaskDelay(1);
uint64_t start = ref_clock_get();
switch (arg->method) {
case 0:
esp_rom_delay_us(arg->delay_us);
break;
case 1:
vTaskDelay(arg->delay_us / portTICK_PERIOD_MS / 1000);
break;
default:
TEST_FAIL();
}
uint64_t stop = ref_clock_get();
arg->result = (int) (stop - start);
xSemaphoreGive(arg->done);
vTaskDelete(NULL);
}
TEST_CASE("ets_delay produces correct delay on both CPUs", "[delay]")
{
int delay_ms = 50;
const delay_test_arg_t args = {
.delay_us = delay_ms * 1000,
.method = 0,
.done = xSemaphoreCreateBinary()
};
ref_clock_init();
xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void*) &args, 3, NULL, 0);
TEST_ASSERT( xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS) );
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#if portNUM_PROCESSORS == 2
xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void*) &args, 3, NULL, 1);
TEST_ASSERT( xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS) );
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#endif
ref_clock_deinit();
vSemaphoreDelete(args.done);
}
TEST_CASE("vTaskDelay produces correct delay on both CPUs", "[delay]")
{
int delay_ms = 50;
const delay_test_arg_t args = {
.delay_us = delay_ms * 1000,
.method = 1,
.done = xSemaphoreCreateBinary()
};
ref_clock_init();
xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void*) &args, 3, NULL, 0);
TEST_ASSERT( xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS) );
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#if portNUM_PROCESSORS == 2
xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void*) &args, 3, NULL, 1);
TEST_ASSERT( xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS) );
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#endif
ref_clock_deinit();
vSemaphoreDelete(args.done);
}

3
components/esp_common/test/CMakeLists.txt
View File

@@ -1,3 +1,2 @@
idf_component_register(SRC_DIRS . idf_component_register(SRC_DIRS .
PRIV_REQUIRES unity spi_flash PRIV_REQUIRES unity test_utils spi_flash)
)

18
components/esp32s2/test/test_delay.c → components/esp_common/test/test_delay.c
View File

@@ -2,11 +2,11 @@
#include <stdlib.h> #include <stdlib.h>
#include <time.h> #include <time.h>
#include <sys/time.h> #include <sys/time.h>
#include "unity.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "freertos/semphr.h" #include "freertos/semphr.h"
#include "unity.h"
#include "test_utils.h" #include "test_utils.h"
typedef struct { typedef struct {
@@ -38,7 +38,7 @@ static void test_delay_task(void *p)
vTaskDelete(NULL); vTaskDelete(NULL);
} }
TEST_CASE("ets_delay produces correct delay", "[delay]") TEST_CASE("esp_rom_delay_us produces correct delay on CPUs", "[delay]")
{ {
int delay_ms = 50; int delay_ms = 50;
const delay_test_arg_t args = { const delay_test_arg_t args = {
@@ -51,11 +51,17 @@ TEST_CASE("ets_delay produces correct delay", "[delay]")
TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS)); TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS));
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result); TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#if portNUM_PROCESSORS == 2
xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void *)&args, 3, NULL, 1);
TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS));
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#endif
ref_clock_deinit(); ref_clock_deinit();
vSemaphoreDelete(args.done); vSemaphoreDelete(args.done);
} }
TEST_CASE("vTaskDelay produces correct delay", "[delay]") TEST_CASE("vTaskDelay produces correct delay on CPUs", "[delay]")
{ {
int delay_ms = 50; int delay_ms = 50;
const delay_test_arg_t args = { const delay_test_arg_t args = {
@@ -68,6 +74,12 @@ TEST_CASE("vTaskDelay produces correct delay", "[delay]")
TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS)); TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS));
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result); TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#if portNUM_PROCESSORS == 2
xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void *)&args, 3, NULL, 1);
TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS));
TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
#endif
ref_clock_deinit(); ref_clock_deinit();
vSemaphoreDelete(args.done); vSemaphoreDelete(args.done);
} }

8
components/soc/src/esp32s2/include/hal/rmt_ll.h
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@@ -334,8 +334,12 @@ static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{ {
dev->carrier_duty_ch[channel].high = high_ticks; // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
dev->carrier_duty_ch[channel].low = low_ticks; // We take care of the "read-modify-write" procedure by ourselves.
typeof(dev->carrier_duty_ch[0]) reg;
reg.high = high_ticks;
reg.low = low_ticks;
dev->carrier_duty_ch[channel].val = reg.val;
} }
static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)

8
components/soc/src/esp32s3/include/hal/rmt_ll.h
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@@ -314,8 +314,12 @@ static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{ {
dev->carrier_duty_ch[channel].high = high_ticks; // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
dev->carrier_duty_ch[channel].low = low_ticks; // We take care of the "read-modify-write" procedure by ourselves.
typeof(dev->carrier_duty_ch[0]) reg;
reg.high = high_ticks;
reg.low = low_ticks;
dev->carrier_duty_ch[channel].val = reg.val;
} }
static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)

151
tools/unit-test-app/components/test_utils/ref_clock.c
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@@ -1,4 +1,4 @@
// Copyright 2017 Espressif Systems (Shanghai) PTE LTD // Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@@ -12,45 +12,39 @@
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
/* Unit tests need to have access to reliable timestamps even if CPU and APB /**
* clock frequencies change over time. This reference clock is built upon two * Some unit test cases need to have access to reliable timestamps even when CPU and APB clock frequencies change over time.
* peripherals: one RMT channel and one PCNT channel, plus one GPIO to connect * This reference clock is built upon two peripherals: one RMT channel and one PCNT channel (hopefully we can have these two peripherals in all ESP chips).
* these peripherals.
* *
* RMT channel is configured to use REF_TICK as clock source, which is a 1 MHz * +---------------------+ 500KHz Square Wave +--------------------------+
* clock derived from APB_CLK using a set of dividers. The divider is changed * | RMT (channel 0, TX) +----------------------------------->+ PCNT (unit 0, channel 0) |
* automatically by hardware depending on the current clock source of APB_CLK. * +---------------------+ +--------------------------+
* For example, if APB_CLK is derived from PLL, one divider is used, and when *
* APB_CLK is derived from XTAL, another divider is used. RMT channel clocked * RMT TX channel is configured to use a fixed clock (e.g. REF_TICK, XTAL) as clock source, so that our ref clock won't be affected during APB/CPU clock switch.
* by REF_TICK is configured to generate a continuous 0.5 MHz signal, which is * Configure RMT channel to generate a 500KHz square wave (using carrier feature) to one GPIO.
* connected to a GPIO. PCNT takes the input signal from this GPIO and counts * PCNT takes the input signal from the GPIO and counts the edges (which occur at 1MHz frequency).
* the edges (which occur at 1MHz frequency). PCNT counter is only 16 bit wide, * PCNT counter is only 16 bit wide, an interrupt is configured to trigger when the counter reaches 30000,
* so an interrupt is configured to trigger when the counter reaches 30000,
* incrementing a 32-bit millisecond counter maintained by software. * incrementing a 32-bit millisecond counter maintained by software.
* Together these two counters may be used at any time to obtain the timestamp.
*/ */
#include "sdkconfig.h"
#include "test_utils.h" #include "test_utils.h"
#include "soc/soc.h" #include "freertos/FreeRTOS.h"
#include "esp_intr_alloc.h"
#include "driver/periph_ctrl.h"
#include "soc/gpio_sig_map.h"
#include "soc/gpio_periph.h"
#include "hal/rmt_hal.h" #include "hal/rmt_hal.h"
#include "hal/rmt_ll.h" #include "hal/rmt_ll.h"
#include "soc/pcnt_caps.h"
#include "hal/pcnt_hal.h" #include "hal/pcnt_hal.h"
#include "soc/gpio_periph.h"
#include "soc/dport_reg.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "driver/periph_ctrl.h"
#include "esp_rom_gpio.h" #include "esp_rom_gpio.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "sdkconfig.h"
/* Select which RMT and PCNT channels, and GPIO to use */ #define REF_CLOCK_RMT_CHANNEL 0 // RMT channel 0
#define REF_CLOCK_RMT_CHANNEL SOC_RMT_CHANNELS_NUM - 1 #define REF_CLOCK_PCNT_UNIT 0 // PCNT unit 0 channel 0
#define REF_CLOCK_PCNT_UNIT 0 #define REF_CLOCK_GPIO 21 // GPIO used to combine RMT out signal with PCNT input signal
#define REF_CLOCK_GPIO 21
#define REF_CLOCK_PRESCALER_MS 30 #define REF_CLOCK_PRESCALER_MS 30 // PCNT high threshold interrupt fired every 30ms
static void IRAM_ATTR pcnt_isr(void *arg); static void IRAM_ATTR pcnt_isr(void *arg);
@@ -58,52 +52,51 @@ static intr_handle_t s_intr_handle;
static portMUX_TYPE s_lock = portMUX_INITIALIZER_UNLOCKED; static portMUX_TYPE s_lock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t s_milliseconds; static volatile uint32_t s_milliseconds;
static rmt_hal_context_t s_rmt_hal;
static pcnt_hal_context_t s_pcnt_hal;
static int get_pcnt_sig(void) void ref_clock_init(void)
{ {
#if CONFIG_IDF_TARGET_ESP32 assert(s_intr_handle == NULL && "ref clock already initialized");
return (REF_CLOCK_PCNT_UNIT < 5) ?
PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT :
PCNT_SIG_CH0_IN5_IDX + 4 * (REF_CLOCK_PCNT_UNIT - 5);
#elif CONFIG_IDF_TARGET_ESP32S2
return PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT;
#endif
}
static rmt_hal_context_t s_rmt;
static pcnt_hal_context_t s_pcnt;
void ref_clock_init()
{
assert(s_intr_handle == NULL && "already initialized");
// Route RMT output to GPIO matrix // Route RMT output to GPIO matrix
esp_rom_gpio_connect_out_signal(REF_CLOCK_GPIO, RMT_SIG_OUT0_IDX + REF_CLOCK_RMT_CHANNEL, false, false); esp_rom_gpio_connect_out_signal(REF_CLOCK_GPIO, RMT_SIG_OUT0_IDX, false, false);
// Initialize RMT // Initialize RMT
periph_module_enable(PERIPH_RMT_MODULE); periph_module_enable(PERIPH_RMT_MODULE);
rmt_hal_init(&s_rmt); rmt_hal_init(&s_rmt_hal);
rmt_ll_enable_mem_access(s_rmt.regs, true);
rmt_item32_t data = { rmt_item32_t data = {
.duration0 = 1, .duration0 = 1,
.level0 = 1, .level0 = 1,
.duration1 = 0, .duration1 = 0,
.level1 = 0 .level1 = 0
}; };
rmt_hal_transmit(&s_rmt, REF_CLOCK_RMT_CHANNEL, &data, 1, 0);
rmt_ll_start_tx(s_rmt.regs, REF_CLOCK_RMT_CHANNEL); rmt_ll_enable_drive_clock(s_rmt_hal.regs, true);
rmt_ll_set_mem_owner(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 0); #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
rmt_ll_reset_tx_pointer(s_rmt.regs, REF_CLOCK_RMT_CHANNEL); rmt_ll_set_counter_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 0); // select REF_TICK (1MHz)
rmt_ll_enable_carrier(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, false); #else
rmt_ll_set_counter_clock_div(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 1); // TODO: configure RMT module clock source to fixed 1MHz
rmt_ll_set_mem_blocks(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 1); #endif
rmt_ll_set_counter_clock_src(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 0); rmt_hal_set_counter_clock(&s_rmt_hal, REF_CLOCK_RMT_CHANNEL, 1000000, 1000000); // counter clock: 1MHz
rmt_ll_enable_tx_loop(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, true); rmt_ll_enable_tx_idle(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true); // enable idle output
rmt_ll_start_tx(s_rmt.regs, REF_CLOCK_RMT_CHANNEL); rmt_ll_set_tx_idle_level(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 1); // idle level: 1
rmt_ll_enable_carrier(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true);
#if !CONFIG_IDF_TARGET_ESP32
rmt_ll_tx_set_carrier_always_on(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true);
#endif
rmt_hal_set_carrier_clock(&s_rmt_hal, REF_CLOCK_RMT_CHANNEL, 1000000, 500000, 0.5); // set carrier to 500KHz
rmt_ll_set_carrier_on_level(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 1);
rmt_ll_enable_mem_access(s_rmt_hal.regs, true);
rmt_ll_reset_tx_pointer(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL);
rmt_ll_set_mem_blocks(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 1);
rmt_ll_write_memory(s_rmt_hal.mem, REF_CLOCK_RMT_CHANNEL, &data, 1, 0);
rmt_ll_enable_tx_loop(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, false);
rmt_ll_start_tx(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL);
// Route signal to PCNT // Route signal to PCNT
int pcnt_sig_idx = get_pcnt_sig(); esp_rom_gpio_connect_in_signal(REF_CLOCK_GPIO, PCNT_SIG_CH0_IN0_IDX, false);
esp_rom_gpio_connect_in_signal(REF_CLOCK_GPIO, pcnt_sig_idx, false);
if (REF_CLOCK_GPIO != 20) { if (REF_CLOCK_GPIO != 20) {
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[REF_CLOCK_GPIO]); PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[REF_CLOCK_GPIO]);
} else { } else {
@@ -112,54 +105,54 @@ void ref_clock_init()
// Initialize PCNT // Initialize PCNT
periph_module_enable(PERIPH_PCNT_MODULE); periph_module_enable(PERIPH_PCNT_MODULE);
pcnt_hal_init(&s_pcnt, REF_CLOCK_PCNT_UNIT); pcnt_hal_init(&s_pcnt_hal, REF_CLOCK_PCNT_UNIT);
pcnt_ll_set_mode(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_CHANNEL_0, pcnt_ll_set_mode(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, PCNT_CHANNEL_0,
PCNT_COUNT_INC, PCNT_COUNT_INC, PCNT_COUNT_INC, PCNT_COUNT_INC,
PCNT_MODE_KEEP, PCNT_MODE_KEEP); PCNT_MODE_KEEP, PCNT_MODE_KEEP);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_L_LIM); pcnt_ll_event_disable(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_L_LIM);
pcnt_ll_event_enable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_H_LIM); pcnt_ll_event_enable(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_H_LIM);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_ZERO); pcnt_ll_event_disable(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_ZERO);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_THRES_0); pcnt_ll_event_disable(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_THRES_0);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_THRES_1); pcnt_ll_event_disable(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_THRES_1);
pcnt_ll_set_event_value(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_H_LIM, REF_CLOCK_PRESCALER_MS * 1000); pcnt_ll_set_event_value(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_H_LIM, REF_CLOCK_PRESCALER_MS * 1000);
// Enable PCNT and wait for it to start counting // Enable PCNT and wait for it to start counting
pcnt_ll_counter_resume(s_pcnt.dev, REF_CLOCK_PCNT_UNIT); pcnt_ll_counter_resume(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT);
pcnt_ll_counter_clear(s_pcnt.dev, REF_CLOCK_PCNT_UNIT); pcnt_ll_counter_clear(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT);
esp_rom_delay_us(10000); esp_rom_delay_us(10000);
// Enable interrupt // Enable interrupt
s_milliseconds = 0; s_milliseconds = 0;
ESP_ERROR_CHECK(esp_intr_alloc(ETS_PCNT_INTR_SOURCE, ESP_INTR_FLAG_IRAM, pcnt_isr, NULL, &s_intr_handle)); ESP_ERROR_CHECK(esp_intr_alloc(ETS_PCNT_INTR_SOURCE, ESP_INTR_FLAG_IRAM, pcnt_isr, NULL, &s_intr_handle));
pcnt_ll_clear_intr_status(s_pcnt.dev, BIT(REF_CLOCK_PCNT_UNIT)); pcnt_ll_clear_intr_status(s_pcnt_hal.dev, BIT(REF_CLOCK_PCNT_UNIT));
pcnt_ll_intr_enable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT); pcnt_ll_intr_enable(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT);
} }
static void IRAM_ATTR pcnt_isr(void *arg) static void IRAM_ATTR pcnt_isr(void *arg)
{ {
portENTER_CRITICAL_ISR(&s_lock); portENTER_CRITICAL_ISR(&s_lock);
pcnt_ll_clear_intr_status(s_pcnt.dev, BIT(REF_CLOCK_PCNT_UNIT)); pcnt_ll_clear_intr_status(s_pcnt_hal.dev, BIT(REF_CLOCK_PCNT_UNIT));
s_milliseconds += REF_CLOCK_PRESCALER_MS; s_milliseconds += REF_CLOCK_PRESCALER_MS;
portEXIT_CRITICAL_ISR(&s_lock); portEXIT_CRITICAL_ISR(&s_lock);
} }
void ref_clock_deinit() void ref_clock_deinit()
{ {
assert(s_intr_handle && "deinit called without init"); assert(s_intr_handle && "ref clock deinit called without init");
// Disable interrupt // Disable interrupt
pcnt_ll_intr_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT); pcnt_ll_intr_disable(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT);
esp_intr_free(s_intr_handle); esp_intr_free(s_intr_handle);
s_intr_handle = NULL; s_intr_handle = NULL;
// Disable RMT // Disable RMT
rmt_ll_stop_tx(s_rmt.regs, REF_CLOCK_RMT_CHANNEL); rmt_ll_enable_carrier(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, false);
periph_module_disable(PERIPH_RMT_MODULE); periph_module_disable(PERIPH_RMT_MODULE);
// Disable PCNT // Disable PCNT
pcnt_ll_counter_pause(s_pcnt.dev, REF_CLOCK_PCNT_UNIT); pcnt_ll_counter_pause(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT);
periph_module_disable(PERIPH_PCNT_MODULE); periph_module_disable(PERIPH_PCNT_MODULE);
} }
@@ -167,13 +160,13 @@ uint64_t ref_clock_get()
{ {
portENTER_CRITICAL(&s_lock); portENTER_CRITICAL(&s_lock);
int16_t microseconds = 0; int16_t microseconds = 0;
pcnt_ll_get_counter_value(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, &microseconds); pcnt_ll_get_counter_value(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, &microseconds);
uint32_t milliseconds = s_milliseconds; uint32_t milliseconds = s_milliseconds;
uint32_t intr_status = 0; uint32_t intr_status = 0;
pcnt_ll_get_intr_status(s_pcnt.dev, &intr_status); pcnt_ll_get_intr_status(s_pcnt_hal.dev, &intr_status);
if (intr_status & BIT(REF_CLOCK_PCNT_UNIT)) { if (intr_status & BIT(REF_CLOCK_PCNT_UNIT)) {
// refresh counter value, in case the overflow has happened after reading cnt_val // refresh counter value, in case the overflow has happened after reading cnt_val
pcnt_ll_get_counter_value(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, &microseconds); pcnt_ll_get_counter_value(s_pcnt_hal.dev, REF_CLOCK_PCNT_UNIT, &microseconds);
milliseconds += REF_CLOCK_PRESCALER_MS; milliseconds += REF_CLOCK_PRESCALER_MS;
} }
portEXIT_CRITICAL(&s_lock); portEXIT_CRITICAL(&s_lock);