From cc8413a330731a6c199c2b92648aeacf35c97494 Mon Sep 17 00:00:00 2001 From: Krzysztof Date: Tue, 12 Oct 2021 13:25:51 +0200 Subject: [PATCH] docs: Update 'Hardware Reference' section for ESP32-S3 --- .../hw-reference/chip-series-comparison.rst | 86 +++++++++++++++---- docs/en/hw-reference/index.rst | 13 ++- .../hw-reference/chip-series-comparison.rst | 78 ++++++++++++++--- docs/zh_CN/hw-reference/index.rst | 15 ++-- 4 files changed, 153 insertions(+), 39 deletions(-) diff --git a/docs/en/hw-reference/chip-series-comparison.rst b/docs/en/hw-reference/chip-series-comparison.rst index 39a2ae56b9..d706b53d1f 100644 --- a/docs/en/hw-reference/chip-series-comparison.rst +++ b/docs/en/hw-reference/chip-series-comparison.rst @@ -7,229 +7,278 @@ Chip Series Comparison The comparison below covers key features of chips supported by ESP-IDF. For the full list of features please refer to respective datasheets in Section `Related Documents`_. .. list-table:: Chip Series Comparison - :widths: 20 40 40 40 + :widths: 20 40 40 40 40 :header-rows: 1 * - Feature - ESP32 Series - ESP32-S2 Series - ESP32-C3 Series + - ESP32-S3 Series * - Launch year - 2016 - 2020 - 2020 + - 2020 * - Variants - See `ESP32 Datasheet (PDF) `_ - See `ESP32-S2 Datasheet (PDF) `_ - See `ESP32-C3 Datasheet (PDF) `_ + - See `ESP32-S3 Datasheet (PDF) `_ * - Core - - Xtensa® dual-core 32-bit LX6 with 600 MIPS (in total); 200 MIPS for ESP32-U4WDH/ESP32-S0WD (single-core variants); 400 MIPS for ESP32-D2WD - - Xtensa® single-core 32-bit LX7 with 300 MIPS + - Xtensa® dual-/single core 32-bit LX6 + - Xtensa® single-core 32-bit LX7 - 32-bit single-core RISC-V + - Xtensa® dual-core 32-bit LX7 * - Wi-Fi protocols - 802.11 b/g/n, 2.4 GHz - 802.11 b/g/n, 2.4 GHz - 802.11 b/g/n, 2.4 GHz + - 802.11 b/g/n, 2.4 GHz * - Bluetooth® - Bluetooth v4.2 BR/EDR and Bluetooth Low Energy - ✖️ - Bluetooth 5.0 + - Bluetooth 5.0 * - Typical frequency - - 240 MHz (160 MHz for ESP32-S0WD, ESP32-D2WD, and ESP32-U4WDH) + - 240 MHz (160 MHz for ESP32-S0WD) - 240 MHz - 160 MHz + - 240 MHz * - SRAM - 520 KB - 320 KB - 400 KB + - 512 KB * - ROM - 448 KB for booting and core functions - 128 KB for booting and core functions - 384 KB for booting and core functions + - 384 KB for booting and core functions * - Embedded flash - 2 MB, 4 MB, or none, depending on variants - 2 MB, 4 MB, or none, depending on variants - 4 MB or none, depending on variants + - 8 MB or none, depending on variants * - External flash - Up to 16 MB device, address 11 MB + 248 KB each time - Up to 1 GB device, address 11.5 MB each time - Up to 16 MB device, address 8 MB each time + - Up to 1 GB device, address 32 MB each time * - External RAM - Up to 8 MB device, address 4 MB each time - Up to 1 GB device, address 11.5 MB each time - ✖️ + - Up to 1 GB device, address 32 MB each time * - Cache - ✔️ Two-way set associative - ✔️ Four-way set associative, independent instruction cache and data cache - ✔️ Eight-way set associative, 32-bit data/instruction bus width + - ✔️ Four-way or eight-way set associative for instruction cache; four-way set associative for data cache, 32-bit data/instruction bus width * - **Peripherals** - - - + - * - ADC - Two 12-bit, 18 channels - - Two 13-bit, 20 channels + - Two 12-bit, 20 channels - Two 12-bit SAR ADCs, at most 6 channels + - Two 12-bit SAR ADCs, 20 channels * - DAC - Two 8-bit channels - Two 8-bit channels - ✖️ + - ✖️ * - Timers - Four 64-bit general-purpose timers, and three watchdog timers - Four 64-bit general-purpose timers, and three watchdog timers - Two 54-bit general-purpose timers, and three watchdog timers + - Four 54-bit general-purpose timers, and three watchdog timers * - Temperature sensor - ✖️ - 1 - 1 + - 1 * - Touch sensor - 10 - 14 - ✖️ + - 14 * - Hall sensor - 1 - ✖️ - ✖️ + - ✖️ * - GPIO - 34 - 43 - 22 + - 45 * - SPI - 4 - - 4 with more modes, compared with ESP32 + - 4 - 3 + - 4 * - LCD interface - 1 - 1 - ✖️ + - 1 * - UART - 3 - 2 :sup:`1` - 2 :sup:`1` + - 3 * - I2C - 2 - 2 - 1 + - 2 * - I2S - 2, can be configured to operate with 8/16/32/40/48-bit resolution as an input or output channel. - 1, can be configured to operate with 8/16/24/32/48/64-bit resolution as an input or output channel. - 1, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel. + - 2, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel. * - Camera interface - 1 - 1 - ✖️ + - 1 * - DMA - Dedicated DMA to UART, SPI, I2S, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi - Dedicated DMA to UART, SPI, AES, SHA, I2S, and ADC Controller - General-purpose, 3 TX channels, 3 RX channels + - General-purpose, 5 TX channels, 5 RX channels * - RMT - 8 channels - 4 channels :sup:`1`, can be configured to TX/RX channels - 4 channels :sup:`2`, 2 TX channels, 2 RX channels + - 8 channels :sup:`2`, 4 TX channels, 4 RX channels * - Pulse counter - 8 channels - 4 channels :sup:`1` - ✖️ + - 4 channels :sup:`1` * - LED PWM - 16 channels - 8 channels :sup:`1` - 6 channels :sup:`2` + - 8 channels :sup:`1` * - MCPWM - 2, six PWM outputs - ✖️ - ✖️ + - 2, six PWM outputs * - USB OTG - ✖️ - 1 - ✖️ + - 1 * - TWAI® controller (compatible with ISO 11898-1) - 1 - 1 - 1 + - 1 * - SD/SDIO/MMC host controller - 1 - ✖️ - ✖️ + - 1 * - SDIO slave controller - 1 - ✖️ - ✖️ + - ✖️ * - Ethernet MAC - 1 - ✖️ - ✖️ + - ✖️ * - ULP - ULP FSM - - PicoRV32 core with 8 KB SRAM, ULP FSM with more instructions + - PicoRV32 core with 8 KB SRAM, ULP FSM - ✖️ + - PicoRV32 core with 8 KB SRAM, ULP FSM * - Debug Assist - ✖️ - ✖️ - 1 + - ✖️ * - **Security** - - - + - * - Secure boot - ✔️ - ✔️ Faster and safer, compared with ESP32 - ✔️ Faster and safer, compared with ESP32 + - ✔️ Faster and safer, compared with ESP32 * - Flash encryption - ✔️ - ✔️ Support for PSRAM encryption. Safer, compared with ESP32 - ✔️ Safer, compared with ESP32 + - ✔️ Support for PSRAM encryption. Safer, compared with ESP32 * - OTP - 1024-bit - 4096-bit - 4096-bit + - 4096-bit * - AES - ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197) - - ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197) - - ✔️ AES-128, AES-256 (FIPS PUB 197) + - ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197); DMA support + - ✔️ AES-128, AES-256 (FIPS PUB 197); DMA support + - ✔️ AES-128, AES-256 (FIPS PUB 197); DMA support * - HASH - SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4) - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support - - SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4) + - SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4); DMA support + - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support * - RSA - Up to 4096 bits - - Up to 4096 bits, improved acceleration options compared with ESP32 + - Up to 4096 bits - Up to 3072 bits + - Up to 4096 bits * - RNG - ✔️ - ✔️ - ✔️ + - ✔️ * - HMAC - ✖️ - ✔️ - ✔️ + - ✔️ * - Digital signature - ✖️ - ✔️ - ✔️ + - ✔️ * - XTS - ✖️ - ✔️ XTS-AES-128, XTS-AES-256 - ✔️ XTS-AES-128 + - ✔️ XTS-AES-128, XTS-AES-256 * - **Other** - - - + - * - Deep-sleep (ULP sensor-monitored pattern) - 100 μA (when ADC work with a duty cycle of 1%) - 22 μA (when touch sensors work with a duty cycle of 1%) - No such pattern + - TBD * - Size - QFN48 5*5, 6*6, depending on variants - QFN56 7*7 - QFN32 5*5 + - QFN56 7*7 -**Note** 1: Reduced chip area compared with ESP32 - - -**Note** 2: Reduced chip area compared with ESP32 and ESP32-S2 - - -**Note** 3: Die size: ESP32-C3 < ESP32-S2 < ESP32 +- **Note** 1: Reduced chip area compared with ESP32 +- **Note** 2: Reduced chip area compared with ESP32 and ESP32-S2 +- **Note** 3: Die size: ESP32-C3 < ESP32-S2 < ESP32-S3 < ESP32 @@ -246,4 +295,5 @@ Related Documents - `ESP32-S2 Datasheet (PDF) `_ - `ESP32-C3 Datasheet (PDF) `_ +- `ESP32-S3 Datasheet (PDF) `_ - `ESP Product Selector `_ \ No newline at end of file diff --git a/docs/en/hw-reference/index.rst b/docs/en/hw-reference/index.rst index 8cf4fa0a70..0349b29007 100644 --- a/docs/en/hw-reference/index.rst +++ b/docs/en/hw-reference/index.rst @@ -6,10 +6,15 @@ .. toctree:: :maxdepth: 3 - :esp32 or esp32s2: Technical Reference Manual (PDF) <{IDF_TARGET_TRM_EN_URL}> - :esp32: Datasheet (PDF) - :esp32s2: Datasheet (PDF) - :esp32: Hardware Design Guidelines (PDF) + Technical Reference Manual (PDF) <{IDF_TARGET_TRM_EN_URL}> + :esp32: ESP32 Datasheet (PDF) + :esp32s2: ESP32-S2 Datasheet (PDF) + :esp32c3: ESP32-C3 Datasheet (PDF) + :esp32s3: ESP32-S3 Datasheet (PDF) + :esp32: ESP32 Hardware Design Guidelines (PDF) + :esp32s2: ESP32-S2 Hardware Design Guidelines (PDF) + :esp32c3: ESP32-C3 Hardware Design Guidelines (PDF) + :esp32s3: ESP32-S3 Hardware Design Guidelines (PDF) :esp32: Silicon Errata (PDF) Modules Development Boards diff --git a/docs/zh_CN/hw-reference/chip-series-comparison.rst b/docs/zh_CN/hw-reference/chip-series-comparison.rst index 7fac5e0cfa..860c49b7e2 100644 --- a/docs/zh_CN/hw-reference/chip-series-comparison.rst +++ b/docs/zh_CN/hw-reference/chip-series-comparison.rst @@ -7,221 +7,274 @@ 下表对比了 ESP-IDF 各系列芯片的主要特性，如需了解更多信息，请参考 `相关文档`_ 中各系列芯片的技术规格书。 .. list-table:: 芯片系列对比 - :widths: 20 40 40 40 + :widths: 20 40 40 40 40 :header-rows: 1 * - 特性 - ESP32 系列 - ESP32-S2 系列 - ESP32-C3 系列 + - ESP32-S3 系列 * - 发布时间 - 2016 - 2020 - 2020 + - 2020 * - 产品型号 - 请参考 `ESP32 技术规格书 (PDF) `_ - 请参考 `ESP32-S2 技术规格书 (PDF) `_ - 请参考 `ESP32-C3 技术规格书 (PDF) `_ + - 请参考 `ESP32-S3 技术规格书 (PDF) `_ * - 内核 - - 搭载低功耗 Xtensa® LX6 32 位双核处理器，处理速度总共高达 600 MIPS，其中 ESP32-U4WDH/ESP32-S0WD（单核）处理速度可达 200 MIPS，ESP32-D2WD 可达 400 MIPS。 - - 搭载低功耗 Xtensa® LX7 32 位单核处理器，处理速度高达 300 MIPS + - 搭载低功耗 Xtensa® LX6 32 位双核/单核处理器 + - 搭载低功耗 Xtensa® LX7 32 位单核处理器 - 搭载 RISC-V 32 位单核处理器 + - 搭载低功耗 Xtensa® LX7 32 位双核处理器 * - Wi-Fi 协议 - 802.11 b/g/n、2.4 GHz - 802.11 b/g/n、2.4 GHz - 802.11 b/g/n、2.4 GHz + - 802.11 b/g/n、2.4 GHz * - Bluetooth® - Bluetooth v4.2 BR/EDR 和 Bluetooth Low Energy - ✖️ - Bluetooth 5.0 + - Bluetooth 5.0 * - 主频 - - 240 MHz（ESP32-S0WD、ESP32-D2WD 和 ESP32-U4WDH 为 160 MHz） + - 240 MHz（ESP32-S0WD 为 160 MHz） - 240 MHz - 160 MHz + - 240 MHz * - SRAM - 520 KB - 320 KB - 400 KB + - 512 KB * - ROM - 448 KB 用于程序启动和内核功能调用 - 128 KB 用于程序启动和内核功能调用 - 384 KB 用于程序启动和内核功能调用 + - 384 KB 用于程序启动和内核功能调用 * - 嵌入式 flash - 2 MB、4 MB 或无嵌入式 flash，不同型号有差异 - 2 MB、4 MB 或无嵌入式 flash，不同型号有差异 - 4 MB 或无嵌入式 flash，不同型号有差异 + - 8 MB 或无嵌入式 flash，不同型号有差异 * - 外部 flash - 最大支持 16 MB，一次最多可映射 11 MB + 248 KB - 最大支持 1 GB，一次最多可映射 11.5 MB - 最大支持 16 MB，一次最多可映射 8 MB + - 最大支持 1 GB，一次最多可映射 32 MB * - 片外 RAM - 最大支持 8 MB，一次最多可映射 4 MB - 最大支持 1 GB，一次最多可映射 11.5 MB - ✖️ + - 最大支持 1 GB，一次最多可映射 32 MB * - Cache - ✔️ 2 路组相联 - ✔️ 4 路组相联，独立的指令和数据 cache - ✔️ 8 路组相连，32 位数据/指令总线宽度 + - ✔️ 指令 cache 可配置为 4 路组相连或 8 路组相连，数据 cache 固定为 4 路组相连，32 位数据/指令总线宽度 * - **外设** + - - - - * - 模/数转换器 (ADC) - 两个 12 位 SAR ADC，多达 18 个通道 - - 两个 13 位 SAR ADC，多达 18 个通道 + - 两个 12 位 SAR ADC，多达 20 个通道 - 两个 12 位 SAR ADC，最多支持 6 个通道 + - 两个 12 位 SAR ADC，多达 20 个通道 * - 数/模转换器 (DAC) - 两个 8 位通道 - 两个 8 位通道 - ✖️ + - ✖️ * - 定时器 - 4 个 64 位通用定时器，3 个看门狗定时器 - 4 个 64 位通用定时器，3 个看门狗定时器 - 2 个 54 位通用定时器，3 个看门狗定时器 + - 4 个 54 位通用定时器，3 个看门狗定时器 * - 温度传感器 - ✖️ - 1 - 1 + - 1 * - 触摸传感器 - 10 - 14 - ✖️ + - 14 * - 霍尔传感器 - 1 - ✖️ - ✖️ + - ✖️ * - 通用输入/输出接口 (GPIO) - 34 - 43 - 22 + - 45 * - 串行外设接口 (SPI) - 4 - - 4 个 SPI，比 ESP32 支持更多模式 + - 4 - 3 + - 4 * - LCD 接口 - 1 - 1 - ✖️ + - 1 * - 通用异步收发器 (UART) - 3 - 2 [#one]_ - 2 [#one]_ + - 3 * - I2C 接口 - 2 - 2 - 1 + - 2 * - I2S 接口 - 2 个，可配置为 8/16/32/40/48 位的输入输出通道 - 1 个，可配置为 8/16/24/32/48/64 位的输入输出通道 - 1 个，可配置为 8/16/24/32 位的输入输出通道 + - 2 个，可配置为 8/16/24/32 位的输入输出通道 * - Camera 接口 - 1 - 1 - ✖️ + - 1 * - DMA - UART、SPI、I2S、SDIO 从机、SD/MMC 主机、EMAC、BT 和 Wi-Fi 都有专用的 DMA 控制器 - UART、SPI、AES、SHA、I2S 和 ADC 控制器都有专用的 DMA 控制器 - 通用 DMA 控制器，3 个接收通道和 3 个发送通道 + - 通用 DMA 控制器，5 个接收通道和 5 个发送通道 * - 红外遥控器 (RMT) - 支持 8 通道 - 支持 4 通道 [#one]_，可配置为红外发射和接收 - 支持 4 通道 [#two]_，双通道的红外发射和双通道的红外接收 + - 支持 8 通道 [#one]_，可配置为红外发射和接收 * - 脉冲计数器 - 8 通道 - 4 通道 [#one]_ - ✖️ + - 4 通道 [#one]_ * - LED PWM - 16 通道 - 8 通道 [#one]_ - 6 通道 [#two]_ + - 8 通道 [#one]_ * - MCPWM - 2，提供六个 PWM 输出 - ✖️ - ✖️ + - 2，提供六个 PWM 输出 * - USB OTG - ✖️ - 1 - ✖️ + - 1 * - TWAI® 控制器（兼容 ISO 11898-1 协议） - 1 - 1 - 1 + - 1 * - SD/SDIO/MMC 主机控制器 - 1 - ✖️ - ✖️ + - 1 * - SDIO 从机控制器 - 1 - ✖️ - ✖️ + - ✖️ * - 以太网 MAC 接口 - 1 - ✖️ - ✖️ + - ✖️ * - 超低功耗协处理器 (ULP) - ULP FSM - - PicoRV32 内核，8 KB SRAM，ULP FSM 支持更多指令 + - PicoRV32 内核，8 KB SRAM，ULP FSM - ✖️ + - PicoRV32 内核，8 KB SRAM，ULP FSM * - 辅助调试 - ✖️ - ✖️ - 1 + - ✖️ * - **安全机制** - - - + - * - 安全启动 - ✔️ - ✔️ 比 ESP32 更快更安全 - ✔️ 比 ESP32 更快更安全 + - ✔️ 比 ESP32 更快更安全 * - Flash 加密 - ✔️ - ✔️ 支持 PSRAM 加密，比 ESP32 更安全 - ✔️ 比 ESP32 更安全 + - ✔️ 支持 PSRAM 加密，比 ESP32 更安全 * - OTP - 1024 位 - 4096 位 - 4096 位 + - 4096 位 * - AES - ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197) - - ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197) - - ✔️ AES-128, AES-256 (FIPS PUB 197) + - ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197); 支持 DMA + - ✔️ AES-128, AES-256 (FIPS PUB 197); 支持 DMA + - ✔️ AES-128, AES-256 (FIPS PUB 197); 支持 DMA * - HASH - SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4) - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); 支持 DMA - - SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4) + - SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4); 支持 DMA + - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); 支持 DMA * - RSA - 高达 4096 位 - - 高达 4096 位，与 ESP32 相比，改善了加速选项 + - 高达 4096 位 - 高达 3072 位 + - 高达 4096 位 * - 随机数生成器 (RNG) - ✔️ - ✔️ - ✔️ + - ✔️ * - HMAC - ✖️ - ✔️ - ✔️ + - ✔️ * - 数字签名 - ✖️ - ✔️ - ✔️ + - ✔️ * - XTS - ✖️ - ✔️ XTS-AES-128, XTS-AES-256 - ✔️ XTS-AES-128 + - ✔️ XTS-AES-128, XTS-AES-256 * - **其它** - - - + - * - Deep-sleep 功耗（超低功耗传感器监测方式） - 100 μA（ADC 以 1% 占空比工作时） - 22 μA（触摸传感器以 1% 占空比工作时） - 无此模式 + - TBD * - 封装尺寸 - QFN48 5*5、6*6，不同型号有差异 - QFN56 7*7 - QFN32 5*5 + - QFN56 7*7 .. note:: @@ -231,7 +284,7 @@ .. note:: - 芯片大小 (die size)：ESP32-C3 < ESP32-S2 < ESP32 + 芯片大小 (die size)：ESP32-C3 < ESP32-S2 < ESP32-S3 < ESP32 相关文档 @@ -246,4 +299,5 @@ - `ESP32-S2 技术规格书 (PDF) `_ - `ESP32-C3 技术规格书 (PDF) `_ +- `ESP32-S3 技术规格书 (PDF) `_ - `ESP 产品选型 `_ \ No newline at end of file diff --git a/docs/zh_CN/hw-reference/index.rst b/docs/zh_CN/hw-reference/index.rst index 997eed6e18..eab3bee3a3 100644 --- a/docs/zh_CN/hw-reference/index.rst +++ b/docs/zh_CN/hw-reference/index.rst @@ -4,12 +4,17 @@ :link_to_translation:`en:[English]` .. toctree:: - :maxdepth: 3 + :maxdepth: 3 - :esp32 or esp32s2: {IDF_TARGET_NAME} 技术参考手册 (PDF) <{IDF_TARGET_TRM_CN_URL}> - :esp32: ESP32 技术规格书 (PDF) - :esp32s2: ESP32-S2 技术规格书 (PDF) - :esp32: ESP32 硬件设计指南 (PDF) + {IDF_TARGET_NAME} 技术参考手册 (PDF) <{IDF_TARGET_TRM_CN_URL}> + :esp32: ESP32 技术规格书 (PDF) + :esp32s2: ESP32-S2 技术规格书 (PDF) + :esp32c3: ESP32-C3 技术规格书 (PDF) + :esp32s3: ESP32-S3 技术规格书 (PDF) + :esp32: ESP32 硬件设计指南 (PDF) + :esp32s2: ESP32-S2 硬件设计指南 (PDF) + :esp32c3: ESP32-C3 硬件设计指南 (PDF) + :esp32s3: ESP32-S3 硬件设计指南 (PDF) :esp32: ESP32 勘误表及解决方法 (PDF) 模组 开发板