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Merge branch 'feature/esp32h21_core_support' into 'master'

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feat(esp32h21): added support for misc core system features

Closes IDF-12042, IDF-11598, IDF-11596, IDF-11874, IDF-11873, IDF-11528, and IDF-11511

See merge request espressif/esp-idf!38773
This commit is contained in:
Marius Vikhammer
2025-04-29 14:53:52 +08:00
parent 8344af1f09 1256078ea2
commit 4ea1facb42
13 changed files with 60 additions and 26 deletions
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4
components/esp_rom/test_apps/rom_impl_components/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

4
components/esp_system/ld/esp32h2/memory.ld.in
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@@ -61,7 +61,7 @@ MEMORY
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/** /**
* lp ram memory (RWX). Persists over deep sleep. // ESP32H2-TODO IDF-6272 * lp ram memory (RWX). Persists over deep sleep.
*/ */
lp_ram_seg(RW) : org = 0x50000000, len = 0x1000 - RESERVE_RTC_MEM lp_ram_seg(RW) : org = 0x50000000, len = 0x1000 - RESERVE_RTC_MEM
@@ -83,7 +83,7 @@ _data_seg_org = ORIGIN(rtc_data_seg);
/** /**
* The lines below define location alias for .rtc.data section * The lines below define location alias for .rtc.data section
* As C3 only has RTC fast memory, this is not configurable like on other targets * As H2 only has RTC fast memory, this is not configurable like on other targets
*/ */
REGION_ALIAS("rtc_iram_seg", lp_ram_seg ); REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); REGION_ALIAS("rtc_data_seg", rtc_iram_seg );

8
components/esp_system/ld/esp32h21/memory.ld.in
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@@ -1,10 +1,9 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/* TODO: [ESP32H21] IDF-11900, IDF-11908 */
/** /**
* ESP32-H21 Linker Script Memory Layout * ESP32-H21 Linker Script Memory Layout
@@ -63,7 +62,7 @@ MEMORY
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/** /**
* lp ram memory (RWX). Persists over deep sleep. // ESP32H21-TODO IDF-11899 * lp ram memory (RWX). Persists over deep sleep.
*/ */
lp_ram_seg(RW) : org = 0x50000000, len = 0x1000 - RESERVE_RTC_MEM lp_ram_seg(RW) : org = 0x50000000, len = 0x1000 - RESERVE_RTC_MEM
@@ -85,7 +84,8 @@ _data_seg_org = ORIGIN(rtc_data_seg);
/** /**
* The lines below define location alias for .rtc.data section * The lines below define location alias for .rtc.data section
* As H21 only has RTC fast memory, this is not configurable like on other targets * H21 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
* Thus, the following region segments are not configurable like on other targets
*/ */
REGION_ALIAS("rtc_iram_seg", lp_ram_seg ); REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); REGION_ALIAS("rtc_data_seg", rtc_iram_seg );

4
components/esp_system/test_apps/esp_system_unity_tests/main/test_task_wdt.c
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@@ -49,7 +49,7 @@ TEST_CASE("Task WDT task timeout", "[task_wdt]")
TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit());
} }
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION && SOC_LIGHT_SLEEP_SUPPORTED
TEST_CASE("Task WDT task timeout after peripheral powerdown lightsleep", "[task_wdt]") TEST_CASE("Task WDT task timeout after peripheral powerdown lightsleep", "[task_wdt]")
{ {
timeout_flag = false; timeout_flag = false;
@@ -89,7 +89,7 @@ TEST_CASE("Task WDT task timeout after peripheral powerdown lightsleep", "[task_
#if SOC_MWDT_SUPPORT_XTAL #if SOC_MWDT_SUPPORT_XTAL
#if CONFIG_IDF_TARGET_ESP32H2 #if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21
#define TEST_CPU_FREQUENCY_MHZ 48 #define TEST_CPU_FREQUENCY_MHZ 48
#else #else
#define TEST_CPU_FREQUENCY_MHZ 40 #define TEST_CPU_FREQUENCY_MHZ 40

2
components/hal/esp32h21/include/hal/cpu_utility_ll.h
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@@ -10,8 +10,6 @@
#include "soc/pcr_reg.h" #include "soc/pcr_reg.h"
#include "esp_attr.h" #include "esp_attr.h"
//TODO: [ESP32H21] IDF-11873, inherit from h2
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif

2
components/hal/esp32h21/include/hal/lpwdt_ll.h
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@@ -23,8 +23,6 @@ extern "C" {
#include "rom/ets_sys.h" #include "rom/ets_sys.h"
//TODO: [ESP32H21] IDF-11511, inherit from h2
/* The value that needs to be written to LP_WDT_WKEY to write-enable the wdt registers */ /* The value that needs to be written to LP_WDT_WKEY to write-enable the wdt registers */
#define LP_WDT_WKEY_VALUE 0x50D83AA1 #define LP_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */ /* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */

2
components/hal/esp32h21/include/hal/mwdt_ll.h
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@@ -23,8 +23,6 @@ extern "C" {
#include "esp_attr.h" #include "esp_attr.h"
#include "hal/misc.h" #include "hal/misc.h"
//TODO: [ESP32H21] IDF-11528, inherit from h2
/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */ /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
#define MWDT_LL_DEFAULT_CLK_PRESCALER 16000 #define MWDT_LL_DEFAULT_CLK_PRESCALER 16000

2
components/hal/esp32h21/include/hal/rwdt_ll.h
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@@ -14,8 +14,6 @@ extern "C" {
#include "hal/lpwdt_ll.h" #include "hal/lpwdt_ll.h"
//TODO: [ESP32H21] IDF-11511, inherit from h2
typedef lp_wdt_dev_t rwdt_dev_t; typedef lp_wdt_dev_t rwdt_dev_t;
#define RWDT_DEV_GET() &LP_WDT #define RWDT_DEV_GET() &LP_WDT

3
components/hal/esp32h21/include/hal/systimer_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,7 +12,6 @@
#include "soc/pcr_struct.h" #include "soc/pcr_struct.h"
#include "hal/assert.h" #include "hal/assert.h"
//TODO: [ESP32H21] IDF-11596, inherit from h2
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

1
components/heap/port/esp32h21/memory_layout.c
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@@ -12,7 +12,6 @@
#include "heap_memory_layout.h" #include "heap_memory_layout.h"
#include "esp_heap_caps.h" #include "esp_heap_caps.h"
//TODO: [ESP32H21] IDF-11525
/** /**
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.

12
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
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@@ -31,6 +31,10 @@ config SOC_EFUSE_SUPPORTED
bool bool
default y default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
config SOC_RTC_MEM_SUPPORTED config SOC_RTC_MEM_SUPPORTED
bool bool
default y default y
@@ -83,6 +87,10 @@ config SOC_SECURE_BOOT_SUPPORTED
bool bool
default y default y
config SOC_WDT_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED config SOC_SPI_FLASH_SUPPORTED
bool bool
default y default y
@@ -643,6 +651,10 @@ config SOC_MWDT_SUPPORT_XTAL
bool bool
default y default y
config SOC_MWDT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_EFUSE_DIS_PAD_JTAG config SOC_EFUSE_DIS_PAD_JTAG
bool bool
default y default y

10
components/soc/esp32h21/include/soc/soc_caps.h
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@@ -34,14 +34,14 @@
// #define SOC_ULP_SUPPORTED 1 // #define SOC_ULP_SUPPORTED 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11507 #define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11507
// #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548 #define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548
// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608 // #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608
// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573 // #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573
#define SOC_GPSPI_SUPPORTED 1 #define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568 // #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568
#define SOC_I2C_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11596, IDF-11598 #define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660 // #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660
#define SOC_MPI_SUPPORTED 1 #define SOC_MPI_SUPPORTED 1
#define SOC_SHA_SUPPORTED 1 #define SOC_SHA_SUPPORTED 1
@@ -59,8 +59,8 @@
// #define SOC_LP_AON_SUPPORTED 1 // #define SOC_LP_AON_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // #define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11521 // #define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11521
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11545 // #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11544
// #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11528 #define SOC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526 #define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526
// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503 // #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503
#define SOC_MODEM_CLOCK_SUPPORTED 1 #define SOC_MODEM_CLOCK_SUPPORTED 1
@@ -447,7 +447,7 @@
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ /*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1) #define SOC_MWDT_SUPPORT_XTAL (1)
// #define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) #define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/ /*-------------------------- TWAI CAPS ---------------------------------------*/
// #define SOC_TWAI_CONTROLLER_NUM 1UL // #define SOC_TWAI_CONTROLLER_NUM 1UL

32
components/soc/esp32h21/wdt_periph.c Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/wdt_periph.h"
#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
};
static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
};
const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
[0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
[1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
};