From 4efab0d0ff74c01bfaa5aa9180c5c279e051b9de Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Tue, 15 Feb 2022 02:09:16 +0800 Subject: [PATCH] soc/esp32s3: merge gpio caps into soc_caps.h --- .../hal/esp32s3/include/hal/rtc_io_ll.h | 2 + .../soc/esp32s3/include/soc/gpio_caps.h | 40 ------------------- .../soc/esp32s3/include/soc/rtc_io_caps.h | 21 ---------- components/soc/esp32s3/include/soc/soc_caps.h | 22 +++++++++- 4 files changed, 22 insertions(+), 63 deletions(-) delete mode 100644 components/soc/esp32s3/include/soc/gpio_caps.h delete mode 100644 components/soc/esp32s3/include/soc/rtc_io_caps.h diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h index 2bd6d12fad..08a3c63e6a 100644 --- a/components/hal/esp32s3/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h @@ -18,6 +18,8 @@ #include "hal/rtc_io_types.h" #include "hal/gpio_types.h" +#define RTCIO_LL_PIN_FUNC 0 + #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/gpio_caps.h b/components/soc/esp32s3/include/soc/gpio_caps.h deleted file mode 100644 index e2ddcdbb53..0000000000 --- a/components/soc/esp32s3/include/soc/gpio_caps.h +++ /dev/null @@ -1,40 +0,0 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -// ESP32-S3 has 1 GPIO peripheral -#define SOC_GPIO_PORT (1) -#define SOC_GPIO_PIN_COUNT (49) - -// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. -#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) -// Force hold is a new function of ESP32-S3 -#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) - -// 0~48 except from 22~25 are valid -#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) -// No GPIO is input only -#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK) - -// Support to configure slept status -#define SOC_GPIO_SUPPORT_SLP_SWITCH (1) - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32s3/include/soc/rtc_io_caps.h b/components/soc/esp32s3/include/soc/rtc_io_caps.h deleted file mode 100644 index 2127adac62..0000000000 --- a/components/soc/esp32s3/include/soc/rtc_io_caps.h +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_RTCIO_PIN_COUNT 22 -#define RTCIO_LL_PIN_FUNC 0 -#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 -#define SOC_RTCIO_HOLD_SUPPORTED 1 -#define SOC_RTCIO_WAKE_SUPPORTED 1 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index b93413c502..3fb138a817 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -95,7 +95,22 @@ #define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction /*-------------------------- GPIO CAPS ---------------------------------------*/ -#include "gpio_caps.h" +// ESP32-S3 has 1 GPIO peripheral +#define SOC_GPIO_PORT (1U) +#define SOC_GPIO_PIN_COUNT (49) + +// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// Force hold is a new function of ESP32-S3 +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) + +// 0~48 except from 22~25 are valid +#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) +// No GPIO is input only +#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK) + +// Support to configure slept status +#define SOC_GPIO_SUPPORT_SLP_SWITCH (1) /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ @@ -175,7 +190,10 @@ #define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3) /*-------------------------- RTCIO CAPS --------------------------------------*/ -#include "rtc_io_caps.h" +#define SOC_RTCIO_PIN_COUNT 22 +#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 +#define SOC_RTCIO_HOLD_SUPPORTED 1 +#define SOC_RTCIO_WAKE_SUPPORTED 1 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/ #define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral