From 4f1046a292c66725802cbe594924ed63dc4588ae Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Mon, 25 Jul 2022 14:02:23 +0800 Subject: [PATCH] ulp-riscv: made ulp_riscv_delay_cycles more accurate --- .../ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h | 11 ++++++++++- components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c | 9 --------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h index 0f6d749754..a53b949b2b 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h @@ -94,7 +94,16 @@ void ulp_riscv_timer_resume(void); * * @param cycles Number of cycles to busy wait */ -void ulp_riscv_delay_cycles(uint32_t cycles); +void static inline ulp_riscv_delay_cycles(uint32_t cycles) +{ + uint32_t start = ULP_RISCV_GET_CCOUNT(); + /* Off with an estimate of cycles in this function to improve accuracy */ + uint32_t end = start + cycles - 20; + + while (ULP_RISCV_GET_CCOUNT() < end) { + /* Wait */ + } +} /** * @brief Clears the GPIO wakeup interrupt bit diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c index 75e48982c0..c2f4a3de92 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c @@ -35,15 +35,6 @@ void ulp_riscv_halt(void) while(1); } -void ulp_riscv_delay_cycles(uint32_t cycles) -{ - uint32_t start = ULP_RISCV_GET_CCOUNT(); - - while ((ULP_RISCV_GET_CCOUNT() - start) < cycles) { - /* Wait */ - } -} - void ulp_riscv_timer_stop(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);