diff --git a/components/hal/esp32c5/include/hal/ahb_dma_ll.h b/components/hal/esp32c5/include/hal/ahb_dma_ll.h index 1546adf8c4..787edf0ec5 100644 --- a/components/hal/esp32c5/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32c5/include/hal/ahb_dma_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,8 +26,8 @@ extern "C" { #define GDMA_LL_RX_EVENT_MASK (0x7F) #define GDMA_LL_TX_EVENT_MASK (0x3F) -// any "dummy" peripheral ID can be used for M2M mode -#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC31) +// for M2M mode, hardware will automatically assign peri_sel ID depends on the channel number (ch0: 10, ch1: 11, ch2: 12) +#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1C00) #define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F) #define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) @@ -220,6 +220,9 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha case 32: burst_mode = 2; // incr8 break; + case 64: + burst_mode = 3; // incr16 + break; default: HAL_ASSERT(false); break; @@ -470,6 +473,9 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha case 32: burst_mode = 2; // incr8 break; + case 64: + burst_mode = 3; // incr16 + break; default: HAL_ASSERT(false); break; diff --git a/components/soc/esp32c5/gdma_periph.c b/components/soc/esp32c5/gdma_periph.c index 1d9f4aa808..3389c09605 100644 --- a/components/soc/esp32c5/gdma_periph.c +++ b/components/soc/esp32c5/gdma_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,19 +34,19 @@ const gdma_signal_conn_t gdma_periph_signals = { AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG - AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG + AHB_DMA_MODULE_CLK_EN_REG */ #define G0P0_RETENTION_REGS_CNT_0 13 #define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) -#define G0P0_RETENTION_REGS_CNT_1 12 +#define G0P0_RETENTION_REGS_CNT_1 11 #define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc) static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; -static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; +static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0x0c900000, 0x601, 0x0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ @@ -72,19 +72,19 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG - AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG + AHB_DMA_MODULE_CLK_EN_REG */ #define G0P1_RETENTION_REGS_CNT_0 13 #define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) -#define G0P1_RETENTION_REGS_CNT_1 12 +#define G0P1_RETENTION_REGS_CNT_1 11 #define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304) static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; -static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; +static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x434800, 0x18, 0x0}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ @@ -107,23 +107,24 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { /* AHB_DMA Channel (Group0, Pair2) Registers Context Include: AHB_DMA_MISC_CONF_REG AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG - - AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_IN_PERI_SEL_CH2_REG AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG + + AHB_DMA_OUT_PERI_SEL_CH2_REG AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH2_REG AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG - AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG - AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG + AHB_DMA_MODULE_CLK_EN_REG */ -#define G0P2_RETENTION_REGS_CNT_0 3 +#define G0P2_RETENTION_REGS_CNT_0 8 #define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) -#define G0P2_RETENTION_REGS_CNT_1 22 -#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x1f0) -static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x0}; -static const uint32_t g0p2_regs_map1[4] = {0x13001813, 0x18, 0x18000, 0x7f26000}; +#define G0P2_RETENTION_REGS_CNT_1 16 +#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x250) +static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x604c0000}; +static const uint32_t g0p2_regs_map1[4] = {0x1813, 0x1800000, 0x72600000, 0x3008}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ diff --git a/components/soc/esp32c5/register/soc/ahb_dma_reg.h b/components/soc/esp32c5/register/soc/ahb_dma_reg.h index 03854c3d4c..b33d44a6da 100644 --- a/components/soc/esp32c5/register/soc/ahb_dma_reg.h +++ b/components/soc/esp32c5/register/soc/ahb_dma_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,1215 +16,1383 @@ extern "C" { */ #define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0) /** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_RAW_M (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S) #define AHB_DMA_IN_DONE_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT. + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT. + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S 7 /** AHB_DMA_IN_INT_ST_CH0_REG register * Masked interrupt status of RX channel 0 */ #define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4) /** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_ST (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_ST_M (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S) #define AHB_DMA_IN_DONE_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_ST_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT. + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT. + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S 7 /** AHB_DMA_IN_INT_ENA_CH0_REG register * Interrupt enable bits of RX channel 0 */ #define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8) /** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT. + * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_ENA (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_ENA_M (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S) #define AHB_DMA_IN_DONE_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_ENA_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT. + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT. + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S 7 /** AHB_DMA_IN_INT_CLR_CH0_REG register * Interrupt clear bits of RX channel 0 */ #define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc) /** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT. + * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_CLR (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_CLR_M (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S) #define AHB_DMA_IN_DONE_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_CLR_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT. + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT. + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S 7 /** AHB_DMA_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel 1 */ #define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10) /** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_RAW_M (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S) #define AHB_DMA_IN_DONE_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT. + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT. + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S 7 /** AHB_DMA_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel 1 */ #define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14) /** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_ST (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_ST_M (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S) #define AHB_DMA_IN_DONE_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_ST_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT. + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT. + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S 7 /** AHB_DMA_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel 1 */ #define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18) /** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT. + * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_ENA (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_ENA_M (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S) #define AHB_DMA_IN_DONE_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_ENA_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT. + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT. + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S 7 /** AHB_DMA_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel 1 */ #define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c) /** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT. + * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_CLR (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_CLR_M (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S) #define AHB_DMA_IN_DONE_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_CLR_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT. + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT. + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S 7 /** AHB_DMA_IN_INT_RAW_CH2_REG register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel 2 */ #define AHB_DMA_IN_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20) /** AHB_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT. + * The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT */ #define AHB_DMA_IN_DONE_CH2_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH2_INT_RAW_M (AHB_DMA_IN_DONE_CH2_INT_RAW_V << AHB_DMA_IN_DONE_CH2_INT_RAW_S) #define AHB_DMA_IN_DONE_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DONE_CH2_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT. + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT */ #define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S) #define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT. + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT */ #define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S) #define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 /** AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT */ #define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT. + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT */ #define AHB_DMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S) #define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT. + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT */ #define AHB_DMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S) #define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S 7 /** AHB_DMA_IN_INT_ST_CH2_REG register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel 2 */ #define AHB_DMA_IN_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x24) /** AHB_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT. + * The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT */ #define AHB_DMA_IN_DONE_CH2_INT_ST (BIT(0)) #define AHB_DMA_IN_DONE_CH2_INT_ST_M (AHB_DMA_IN_DONE_CH2_INT_ST_V << AHB_DMA_IN_DONE_CH2_INT_ST_S) #define AHB_DMA_IN_DONE_CH2_INT_ST_V 0x00000001U #define AHB_DMA_IN_DONE_CH2_INT_ST_S 0 /** AHB_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT. + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT */ #define AHB_DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S) #define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S 1 /** AHB_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT. + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT */ #define AHB_DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S) #define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S 2 /** AHB_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT */ #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 /** AHB_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT. + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT */ #define AHB_DMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH2_INT_ST_M (AHB_DMA_INFIFO_OVF_CH2_INT_ST_V << AHB_DMA_INFIFO_OVF_CH2_INT_ST_S) #define AHB_DMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH2_INT_ST_S 5 /** AHB_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT. + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT */ #define AHB_DMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH2_INT_ST_M (AHB_DMA_INFIFO_UDF_CH2_INT_ST_V << AHB_DMA_INFIFO_UDF_CH2_INT_ST_S) #define AHB_DMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH2_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S 7 /** AHB_DMA_IN_INT_ENA_CH2_REG register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel 2 */ #define AHB_DMA_IN_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x28) /** AHB_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH2_INT. + * Write 1 to enable AHB_DMA_IN_DONE_CH2_INT */ #define AHB_DMA_IN_DONE_CH2_INT_ENA (BIT(0)) #define AHB_DMA_IN_DONE_CH2_INT_ENA_M (AHB_DMA_IN_DONE_CH2_INT_ENA_V << AHB_DMA_IN_DONE_CH2_INT_ENA_S) #define AHB_DMA_IN_DONE_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DONE_CH2_INT_ENA_S 0 /** AHB_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT. + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT */ #define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S) #define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 /** AHB_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT. + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT */ #define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S) #define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 /** AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT */ #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 /** AHB_DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT. + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT */ #define AHB_DMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S) #define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S 5 /** AHB_DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT. + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT */ #define AHB_DMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S) #define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S 7 /** AHB_DMA_IN_INT_CLR_CH2_REG register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel 2 */ #define AHB_DMA_IN_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x2c) /** AHB_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH2_INT. + * Write 1 to clear AHB_DMA_IN_DONE_CH2_INT */ #define AHB_DMA_IN_DONE_CH2_INT_CLR (BIT(0)) #define AHB_DMA_IN_DONE_CH2_INT_CLR_M (AHB_DMA_IN_DONE_CH2_INT_CLR_V << AHB_DMA_IN_DONE_CH2_INT_CLR_S) #define AHB_DMA_IN_DONE_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DONE_CH2_INT_CLR_S 0 /** AHB_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT. + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT */ #define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S) #define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 /** AHB_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT. + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT */ #define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S) #define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 /** AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT */ #define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S) #define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 /** AHB_DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT. + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT */ #define AHB_DMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S) #define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S 5 /** AHB_DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT. + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT */ #define AHB_DMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S) #define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S 7 /** AHB_DMA_OUT_INT_RAW_CH0_REG register - * Raw interrupt status of TX channel 0 + * //Raw interrupt status of TX channel 0 */ #define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30) /** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_RAW_M (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S) #define AHB_DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S) #define AHB_DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_RAW_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S 6 /** AHB_DMA_OUT_INT_ST_CH0_REG register * Masked interrupt status of TX channel 0 */ #define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34) /** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_ST (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_ST_M (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S) #define AHB_DMA_OUT_DONE_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_ST_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_ST (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_ST_M (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S) #define AHB_DMA_OUT_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_ST_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S 6 /** AHB_DMA_OUT_INT_ENA_CH0_REG register * Interrupt enable bits of TX channel 0 */ #define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38) /** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_ENA (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_ENA_M (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S) #define AHB_DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_ENA_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_ENA (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S) #define AHB_DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_ENA_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S 6 /** AHB_DMA_OUT_INT_CLR_CH0_REG register * Interrupt clear bits of TX channel 0 */ #define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c) /** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_CLR (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_CLR_M (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S) #define AHB_DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_CLR_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_CLR (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S) #define AHB_DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_CLR_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S 6 /** AHB_DMA_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 0 + * //Raw interrupt status of TX channel 1 */ #define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40) /** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_RAW_M (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S) #define AHB_DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S) #define AHB_DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_RAW_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S 6 /** AHB_DMA_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 1 */ #define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44) /** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_ST (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_ST_M (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S) #define AHB_DMA_OUT_DONE_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_ST_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_ST (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_ST_M (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S) #define AHB_DMA_OUT_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_ST_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S 6 /** AHB_DMA_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 1 */ #define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48) /** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_ENA (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_ENA_M (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S) #define AHB_DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_ENA_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_ENA (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S) #define AHB_DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_ENA_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S 6 /** AHB_DMA_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 1 */ #define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c) /** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_CLR (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_CLR_M (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S) #define AHB_DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_CLR_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_CLR (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S) #define AHB_DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_CLR_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S 6 /** AHB_DMA_OUT_INT_RAW_CH2_REG register - * Raw interrupt status of TX channel 0 + * //Raw interrupt status of TX channel 2 */ #define AHB_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x50) /** AHB_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT. + * The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT */ #define AHB_DMA_OUT_DONE_CH2_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH2_INT_RAW_M (AHB_DMA_OUT_DONE_CH2_INT_RAW_V << AHB_DMA_OUT_DONE_CH2_INT_RAW_S) #define AHB_DMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DONE_CH2_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT. + * The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT */ #define AHB_DMA_OUT_EOF_CH2_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_EOF_CH2_INT_RAW_S) #define AHB_DMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_EOF_CH2_INT_RAW_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT. + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT. + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT */ #define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT */ #define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S 6 /** AHB_DMA_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 2 */ #define AHB_DMA_OUT_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x54) /** AHB_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT. + * The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT */ #define AHB_DMA_OUT_DONE_CH2_INT_ST (BIT(0)) #define AHB_DMA_OUT_DONE_CH2_INT_ST_M (AHB_DMA_OUT_DONE_CH2_INT_ST_V << AHB_DMA_OUT_DONE_CH2_INT_ST_S) #define AHB_DMA_OUT_DONE_CH2_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DONE_CH2_INT_ST_S 0 /** AHB_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT. + * The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT */ #define AHB_DMA_OUT_EOF_CH2_INT_ST (BIT(1)) #define AHB_DMA_OUT_EOF_CH2_INT_ST_M (AHB_DMA_OUT_EOF_CH2_INT_ST_V << AHB_DMA_OUT_EOF_CH2_INT_ST_S) #define AHB_DMA_OUT_EOF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_OUT_EOF_CH2_INT_ST_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT. + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT. + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 /** AHB_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT */ #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S 4 /** AHB_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT */ #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S 6 /** AHB_DMA_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 2 */ #define AHB_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x58) /** AHB_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT. + * Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT */ #define AHB_DMA_OUT_DONE_CH2_INT_ENA (BIT(0)) #define AHB_DMA_OUT_DONE_CH2_INT_ENA_M (AHB_DMA_OUT_DONE_CH2_INT_ENA_V << AHB_DMA_OUT_DONE_CH2_INT_ENA_S) #define AHB_DMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DONE_CH2_INT_ENA_S 0 /** AHB_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT. + * Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT */ #define AHB_DMA_OUT_EOF_CH2_INT_ENA (BIT(1)) #define AHB_DMA_OUT_EOF_CH2_INT_ENA_M (AHB_DMA_OUT_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_EOF_CH2_INT_ENA_S) #define AHB_DMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_EOF_CH2_INT_ENA_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT. + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT. + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 /** AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT */ #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 /** AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT */ #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S 6 /** AHB_DMA_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 2 */ #define AHB_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x5c) /** AHB_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT. + * Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT */ #define AHB_DMA_OUT_DONE_CH2_INT_CLR (BIT(0)) #define AHB_DMA_OUT_DONE_CH2_INT_CLR_M (AHB_DMA_OUT_DONE_CH2_INT_CLR_V << AHB_DMA_OUT_DONE_CH2_INT_CLR_S) #define AHB_DMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DONE_CH2_INT_CLR_S 0 /** AHB_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT. + * Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT */ #define AHB_DMA_OUT_EOF_CH2_INT_CLR (BIT(1)) #define AHB_DMA_OUT_EOF_CH2_INT_CLR_M (AHB_DMA_OUT_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_EOF_CH2_INT_CLR_S) #define AHB_DMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_EOF_CH2_INT_CLR_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT. + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S) #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT. + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 /** AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT */ #define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S) #define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 /** AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT */ #define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S) #define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S 6 /** AHB_DMA_AHB_TEST_REG register - * reserved + * only for test */ #define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60) /** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; @@ -1243,27 +1411,29 @@ extern "C" { #define AHB_DMA_AHB_TESTADDR_S 4 /** AHB_DMA_MISC_CONF_REG register - * Miscellaneous register + * reserved */ #define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0x64) /** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM. + * Write 1 and then 0 to reset the internal AHB FSM */ #define AHB_DMA_AHBM_RST_INTER (BIT(0)) #define AHB_DMA_AHBM_RST_INTER_M (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S) #define AHB_DMA_AHBM_RST_INTER_V 0x00000001U #define AHB_DMA_AHBM_RST_INTER_S 0 /** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; - * Configures whether or not to disable the fixed-priority channel arbitration.\\0: - * Enable\\1: Disable\\ + * Configures whether to disable the fixed-priority channel arbitration. + * 0: Enable + * 1: Disable */ #define AHB_DMA_ARB_PRI_DIS (BIT(2)) #define AHB_DMA_ARB_PRI_DIS_M (AHB_DMA_ARB_PRI_DIS_V << AHB_DMA_ARB_PRI_DIS_S) #define AHB_DMA_ARB_PRI_DIS_V 0x00000001U #define AHB_DMA_ARB_PRI_DIS_S 2 /** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0; - * Configures clock gating.\\0: Support clock only when the application writes - * registers.\\ 1: Always force the clock on for registers.\\ + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ #define AHB_DMA_CLK_EN (BIT(3)) #define AHB_DMA_CLK_EN_M (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S) @@ -1274,8 +1444,8 @@ extern "C" { * Version control register */ #define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0x68) -/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 36770448; - * Version control register. +/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 2410220; + * Version control register */ #define AHB_DMA_DATE 0xFFFFFFFFU #define AHB_DMA_DATE_M (AHB_DMA_DATE_V << AHB_DMA_DATE_S) @@ -1294,39 +1464,46 @@ extern "C" { #define AHB_DMA_IN_RST_CH0_V 0x00000001U #define AHB_DMA_IN_RST_CH0_S 0 /** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_IN_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH0_M (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S) #define AHB_DMA_IN_LOOP_TEST_CH0_V 0x00000001U #define AHB_DMA_IN_LOOP_TEST_CH0_S 1 /** AHB_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable INCR burst transfer for RX channel 0 to read - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for RX channel 0 to read + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INDSCR_BURST_EN_CH0 (BIT(2)) #define AHB_DMA_INDSCR_BURST_EN_CH0_M (AHB_DMA_INDSCR_BURST_EN_CH0_V << AHB_DMA_INDSCR_BURST_EN_CH0_S) #define AHB_DMA_INDSCR_BURST_EN_CH0_V 0x00000001U #define AHB_DMA_INDSCR_BURST_EN_CH0_S 2 /** AHB_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_MEM_TRANS_EN_CH0 (BIT(4)) #define AHB_DMA_MEM_TRANS_EN_CH0_M (AHB_DMA_MEM_TRANS_EN_CH0_V << AHB_DMA_MEM_TRANS_EN_CH0_S) #define AHB_DMA_MEM_TRANS_EN_CH0_V 0x00000001U #define AHB_DMA_MEM_TRANS_EN_CH0_S 4 /** AHB_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ETM control for RX channel0.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for RX channel0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_ETM_EN_CH0 (BIT(5)) #define AHB_DMA_IN_ETM_EN_CH0_M (AHB_DMA_IN_ETM_EN_CH0_V << AHB_DMA_IN_ETM_EN_CH0_S) #define AHB_DMA_IN_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH0_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures max burst size for Rx channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S) @@ -1338,8 +1515,9 @@ extern "C" { */ #define AHB_DMA_IN_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x74) /** AHB_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for RX channel 0.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for RX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_CHECK_OWNER_CH0 (BIT(12)) #define AHB_DMA_IN_CHECK_OWNER_CH0_M (AHB_DMA_IN_CHECK_OWNER_CH0_V << AHB_DMA_IN_CHECK_OWNER_CH0_S) @@ -1351,21 +1529,25 @@ extern "C" { */ #define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78) /** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; - * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_INFIFO_FULL_CH0 (BIT(0)) #define AHB_DMA_INFIFO_FULL_CH0_M (AHB_DMA_INFIFO_FULL_CH0_V << AHB_DMA_INFIFO_FULL_CH0_S) #define AHB_DMA_INFIFO_FULL_CH0_V 0x00000001U #define AHB_DMA_INFIFO_FULL_CH0_S 0 /** AHB_DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_INFIFO_EMPTY_CH0 (BIT(1)) #define AHB_DMA_INFIFO_EMPTY_CH0_M (AHB_DMA_INFIFO_EMPTY_CH0_V << AHB_DMA_INFIFO_EMPTY_CH0_S) #define AHB_DMA_INFIFO_EMPTY_CH0_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH0_S 1 /** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 0. + * Represents the number of data bytes in L1 RX FIFO for RX channel 0 */ #define AHB_DMA_INFIFO_CNT_CH0 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH0_M (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S) @@ -1408,7 +1590,7 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH0_S 27 /** AHB_DMA_IN_POP_CH0_REG register - * Pop control register of RX channel 0 + * Receive FIFO status of RX channel 0 */ #define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c) /** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; @@ -1419,8 +1601,9 @@ extern "C" { #define AHB_DMA_INFIFO_RDATA_CH0_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH0_S 0 /** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; - * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: - * Pop\\ + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop */ #define AHB_DMA_INFIFO_POP_CH0 (BIT(12)) #define AHB_DMA_INFIFO_POP_CH0_M (AHB_DMA_INFIFO_POP_CH0_V << AHB_DMA_INFIFO_POP_CH0_S) @@ -1428,43 +1611,51 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH0_S 12 /** AHB_DMA_IN_LINK_CH0_REG register - * Linked list descriptor configuration and control register of RX channel 0 + * Receive FIFO status of RX channel 0 */ #define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80) /** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1; - * Configures whether or not to return to current receive descriptor's address when - * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . */ #define AHB_DMA_INLINK_AUTO_RET_CH0 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH0_M (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S) #define AHB_DMA_INLINK_AUTO_RET_CH0_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH0_S 0 /** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether or not to stop AHB_DMA's RX channel 0 from receiving data.\\0: - * Invalid. No effect\\1: Stop\\ + * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_INLINK_STOP_CH0 (BIT(1)) #define AHB_DMA_INLINK_STOP_CH0_M (AHB_DMA_INLINK_STOP_CH0_V << AHB_DMA_INLINK_STOP_CH0_S) #define AHB_DMA_INLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH0_S 1 /** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable AHB_DMA's RX channel 0 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INLINK_START_CH0 (BIT(2)) #define AHB_DMA_INLINK_START_CH0_M (AHB_DMA_INLINK_START_CH0_V << AHB_DMA_INLINK_START_CH0_S) #define AHB_DMA_INLINK_START_CH0_V 0x00000001U #define AHB_DMA_INLINK_START_CH0_S 2 /** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0; - * Configures whether or not to restart RX channel 0 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart RX channel 0 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_INLINK_RESTART_CH0 (BIT(3)) #define AHB_DMA_INLINK_RESTART_CH0_M (AHB_DMA_INLINK_RESTART_CH0_V << AHB_DMA_INLINK_RESTART_CH0_S) #define AHB_DMA_INLINK_RESTART_CH0_V 0x00000001U #define AHB_DMA_INLINK_RESTART_CH0_S 3 /** AHB_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_INLINK_PARK_CH0 (BIT(4)) #define AHB_DMA_INLINK_PARK_CH0_M (AHB_DMA_INLINK_PARK_CH0_V << AHB_DMA_INLINK_PARK_CH0_S) @@ -1476,8 +1667,7 @@ extern "C" { */ #define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84) /** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * reserved */ #define AHB_DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH0_M (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S) @@ -1491,7 +1681,8 @@ extern "C" { #define AHB_DMA_IN_DSCR_STATE_CH0_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH0_S 18 /** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. */ #define AHB_DMA_IN_STATE_CH0 0x00000007U #define AHB_DMA_IN_STATE_CH0_M (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S) @@ -1569,7 +1760,7 @@ extern "C" { #define AHB_DMA_IN_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) /** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; * Configures the priority of RX channel 0.The larger of the value, the higher of the - * priority. + * priority.. */ #define AHB_DMA_RX_PRI_CH0 0x0000000FU #define AHB_DMA_RX_PRI_CH0_M (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S) @@ -1581,9 +1772,21 @@ extern "C" { */ #define AHB_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0xa0) /** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 0.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to RX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy */ #define AHB_DMA_PERI_IN_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH0_M (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S) @@ -1595,57 +1798,67 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0) /** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ + * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset */ #define AHB_DMA_OUT_RST_CH0 (BIT(0)) #define AHB_DMA_OUT_RST_CH0_M (AHB_DMA_OUT_RST_CH0_V << AHB_DMA_OUT_RST_CH0_S) #define AHB_DMA_OUT_RST_CH0_V 0x00000001U #define AHB_DMA_OUT_RST_CH0_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_OUT_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH0_M (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S) #define AHB_DMA_OUT_LOOP_TEST_CH0_V 0x00000001U #define AHB_DMA_OUT_LOOP_TEST_CH0_S 1 /** AHB_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) #define AHB_DMA_OUT_AUTO_WRBACK_CH0_M (AHB_DMA_OUT_AUTO_WRBACK_CH0_V << AHB_DMA_OUT_AUTO_WRBACK_CH0_S) #define AHB_DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U #define AHB_DMA_OUT_AUTO_WRBACK_CH0_S 2 /** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel 0 is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH0 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH0_M (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S) #define AHB_DMA_OUT_EOF_MODE_CH0_V 0x00000001U #define AHB_DMA_OUT_EOF_MODE_CH0_S 3 /** AHB_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel 0 reading - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for TX channel 0 reading + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) #define AHB_DMA_OUTDSCR_BURST_EN_CH0_M (AHB_DMA_OUTDSCR_BURST_EN_CH0_V << AHB_DMA_OUTDSCR_BURST_EN_CH0_S) #define AHB_DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U #define AHB_DMA_OUTDSCR_BURST_EN_CH0_S 4 /** AHB_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for TX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_ETM_EN_CH0 (BIT(6)) #define AHB_DMA_OUT_ETM_EN_CH0_M (AHB_DMA_OUT_ETM_EN_CH0_V << AHB_DMA_OUT_ETM_EN_CH0_S) #define AHB_DMA_OUT_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH0_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures max burst size for TX channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S) @@ -1657,8 +1870,9 @@ extern "C" { */ #define AHB_DMA_OUT_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd4) /** AHB_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for TX channel 0.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for TX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) #define AHB_DMA_OUT_CHECK_OWNER_CH0_M (AHB_DMA_OUT_CHECK_OWNER_CH0_V << AHB_DMA_OUT_CHECK_OWNER_CH0_S) @@ -1666,53 +1880,57 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH0_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH0_REG register - * Transmit FIFO status of TX channel 0 + * Receive FIFO status of RX channel 0 */ #define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8) /** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; - * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_OUTFIFO_FULL_CH0 (BIT(0)) #define AHB_DMA_OUTFIFO_FULL_CH0_M (AHB_DMA_OUTFIFO_FULL_CH0_V << AHB_DMA_OUTFIFO_FULL_CH0_S) #define AHB_DMA_OUTFIFO_FULL_CH0_V 0x00000001U #define AHB_DMA_OUTFIFO_FULL_CH0_S 0 /** AHB_DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) #define AHB_DMA_OUTFIFO_EMPTY_CH0_M (AHB_DMA_OUTFIFO_EMPTY_CH0_V << AHB_DMA_OUTFIFO_EMPTY_CH0_S) #define AHB_DMA_OUTFIFO_EMPTY_CH0_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH0_S 1 /** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 0. + * Represents the number of data bytes in L1 TX FIFO for TX channel 0 */ #define AHB_DMA_OUTFIFO_CNT_CH0 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH0_M (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S) #define AHB_DMA_OUTFIFO_CNT_CH0_V 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH0_S 8 /** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 /** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 /** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 /** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S) @@ -1724,15 +1942,16 @@ extern "C" { */ #define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc) /** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_WDATA_CH0 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_M (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S) #define AHB_DMA_OUTFIFO_WDATA_CH0_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; - * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No - * effect\\1: Push\\ + * Configures the data that need to be pushed into AHB_DMA FIFO. */ #define AHB_DMA_OUTFIFO_PUSH_CH0 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH0_M (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S) @@ -1740,35 +1959,40 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH0_S 9 /** AHB_DMA_OUT_LINK_CH0_REG register - * Linked list descriptor configuration and control register of TX channel 0 + * Push control register of TX channel 0 */ #define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0) /** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to stop AHB_DMA's TX channel 0 from transmitting - * data.\\0: Invalid. No effect\\1: Stop\\ + * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_OUTLINK_STOP_CH0 (BIT(0)) #define AHB_DMA_OUTLINK_STOP_CH0_M (AHB_DMA_OUTLINK_STOP_CH0_V << AHB_DMA_OUTLINK_STOP_CH0_S) #define AHB_DMA_OUTLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH0_S 0 /** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable AHB_DMA's TX channel 0 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTLINK_START_CH0 (BIT(1)) #define AHB_DMA_OUTLINK_START_CH0_M (AHB_DMA_OUTLINK_START_CH0_V << AHB_DMA_OUTLINK_START_CH0_S) #define AHB_DMA_OUTLINK_START_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH0_S 1 /** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether or not to restart TX channel 0 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart TX channel 0 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_OUTLINK_RESTART_CH0 (BIT(2)) #define AHB_DMA_OUTLINK_RESTART_CH0_M (AHB_DMA_OUTLINK_RESTART_CH0_V << AHB_DMA_OUTLINK_RESTART_CH0_S) #define AHB_DMA_OUTLINK_RESTART_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_RESTART_CH0_S 2 /** AHB_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_OUTLINK_PARK_CH0 (BIT(3)) #define AHB_DMA_OUTLINK_PARK_CH0_M (AHB_DMA_OUTLINK_PARK_CH0_V << AHB_DMA_OUTLINK_PARK_CH0_S) @@ -1873,7 +2097,7 @@ extern "C" { #define AHB_DMA_OUT_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) /** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; * Configures the priority of TX channel 0.The larger of the value, the higher of the - * priority. + * priority.. */ #define AHB_DMA_TX_PRI_CH0 0x0000000FU #define AHB_DMA_TX_PRI_CH0_M (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S) @@ -1885,9 +2109,21 @@ extern "C" { */ #define AHB_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x100) /** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 0.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to TX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy */ #define AHB_DMA_PERI_OUT_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH0_M (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S) @@ -1895,50 +2131,57 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH0_S 0 /** AHB_DMA_IN_CONF0_CH1_REG register - * Configuration register 0 of RX channel 0 + * Configuration register 0 of RX channel 1 */ #define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130) /** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH1 (BIT(0)) #define AHB_DMA_IN_RST_CH1_M (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S) #define AHB_DMA_IN_RST_CH1_V 0x00000001U #define AHB_DMA_IN_RST_CH1_S 0 /** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_IN_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH1_M (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S) #define AHB_DMA_IN_LOOP_TEST_CH1_V 0x00000001U #define AHB_DMA_IN_LOOP_TEST_CH1_S 1 /** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable INCR burst transfer for RX channel 1 to read - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for RX channel 1 to read + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INDSCR_BURST_EN_CH1 (BIT(2)) #define AHB_DMA_INDSCR_BURST_EN_CH1_M (AHB_DMA_INDSCR_BURST_EN_CH1_V << AHB_DMA_INDSCR_BURST_EN_CH1_S) #define AHB_DMA_INDSCR_BURST_EN_CH1_V 0x00000001U #define AHB_DMA_INDSCR_BURST_EN_CH1_S 2 /** AHB_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_MEM_TRANS_EN_CH1 (BIT(4)) #define AHB_DMA_MEM_TRANS_EN_CH1_M (AHB_DMA_MEM_TRANS_EN_CH1_V << AHB_DMA_MEM_TRANS_EN_CH1_S) #define AHB_DMA_MEM_TRANS_EN_CH1_V 0x00000001U #define AHB_DMA_MEM_TRANS_EN_CH1_S 4 /** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ETM control for RX channel1.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for RX channel1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_ETM_EN_CH1 (BIT(5)) #define AHB_DMA_IN_ETM_EN_CH1_M (AHB_DMA_IN_ETM_EN_CH1_V << AHB_DMA_IN_ETM_EN_CH1_S) #define AHB_DMA_IN_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH1_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures max burst size for Rx channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S) @@ -1946,12 +2189,13 @@ extern "C" { #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S 6 /** AHB_DMA_IN_CONF1_CH1_REG register - * Configuration register 1 of RX channel 0 + * Configuration register 1 of RX channel 1 */ #define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x134) /** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for RX channel 1.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for RX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_CHECK_OWNER_CH1 (BIT(12)) #define AHB_DMA_IN_CHECK_OWNER_CH1_M (AHB_DMA_IN_CHECK_OWNER_CH1_V << AHB_DMA_IN_CHECK_OWNER_CH1_S) @@ -1959,25 +2203,29 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH1_S 12 /** AHB_DMA_INFIFO_STATUS_CH1_REG register - * Receive FIFO status of RX channel 0 + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138) /** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; - * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_INFIFO_FULL_CH1 (BIT(0)) #define AHB_DMA_INFIFO_FULL_CH1_M (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S) #define AHB_DMA_INFIFO_FULL_CH1_V 0x00000001U #define AHB_DMA_INFIFO_FULL_CH1_S 0 /** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_INFIFO_EMPTY_CH1 (BIT(1)) #define AHB_DMA_INFIFO_EMPTY_CH1_M (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S) #define AHB_DMA_INFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH1_S 1 /** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 1. + * Represents the number of data bytes in L1 RX FIFO for RX channel 1 */ #define AHB_DMA_INFIFO_CNT_CH1 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH1_M (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S) @@ -2020,7 +2268,7 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH1_S 27 /** AHB_DMA_IN_POP_CH1_REG register - * Pop control register of RX channel 0 + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c) /** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; @@ -2031,8 +2279,9 @@ extern "C" { #define AHB_DMA_INFIFO_RDATA_CH1_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH1_S 0 /** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; - * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: - * Pop\\ + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop */ #define AHB_DMA_INFIFO_POP_CH1 (BIT(12)) #define AHB_DMA_INFIFO_POP_CH1_M (AHB_DMA_INFIFO_POP_CH1_V << AHB_DMA_INFIFO_POP_CH1_S) @@ -2040,43 +2289,51 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH1_S 12 /** AHB_DMA_IN_LINK_CH1_REG register - * Linked list descriptor configuration and control register of RX channel 0 + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140) /** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; - * Configures whether or not to return to current receive descriptor's address when - * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . */ #define AHB_DMA_INLINK_AUTO_RET_CH1 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH1_M (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S) #define AHB_DMA_INLINK_AUTO_RET_CH1_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH1_S 0 /** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to stop AHB_DMA's RX channel 1 from receiving data.\\0: - * Invalid. No effect\\1: Stop\\ + * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_INLINK_STOP_CH1 (BIT(1)) #define AHB_DMA_INLINK_STOP_CH1_M (AHB_DMA_INLINK_STOP_CH1_V << AHB_DMA_INLINK_STOP_CH1_S) #define AHB_DMA_INLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH1_S 1 /** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable AHB_DMA's RX channel 1 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INLINK_START_CH1 (BIT(2)) #define AHB_DMA_INLINK_START_CH1_M (AHB_DMA_INLINK_START_CH1_V << AHB_DMA_INLINK_START_CH1_S) #define AHB_DMA_INLINK_START_CH1_V 0x00000001U #define AHB_DMA_INLINK_START_CH1_S 2 /** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0; - * Configures whether or not to restart RX channel 1 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart RX channel 1 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_INLINK_RESTART_CH1 (BIT(3)) #define AHB_DMA_INLINK_RESTART_CH1_M (AHB_DMA_INLINK_RESTART_CH1_V << AHB_DMA_INLINK_RESTART_CH1_S) #define AHB_DMA_INLINK_RESTART_CH1_V 0x00000001U #define AHB_DMA_INLINK_RESTART_CH1_S 3 /** AHB_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_INLINK_PARK_CH1 (BIT(4)) #define AHB_DMA_INLINK_PARK_CH1_M (AHB_DMA_INLINK_PARK_CH1_V << AHB_DMA_INLINK_PARK_CH1_S) @@ -2084,12 +2341,11 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH1_S 4 /** AHB_DMA_IN_STATE_CH1_REG register - * Receive status of RX channel 0 + * Receive status of RX channel 1 */ #define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144) /** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * reserved */ #define AHB_DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH1_M (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S) @@ -2103,7 +2359,8 @@ extern "C" { #define AHB_DMA_IN_DSCR_STATE_CH1_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH1_S 18 /** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. */ #define AHB_DMA_IN_STATE_CH1 0x00000007U #define AHB_DMA_IN_STATE_CH1_M (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S) @@ -2111,7 +2368,7 @@ extern "C" { #define AHB_DMA_IN_STATE_CH1_S 20 /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Receive descriptor address when EOF occurs on RX channel 0 + * Receive descriptor address when EOF occurs on RX channel 1 */ #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x148) /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2124,7 +2381,7 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Receive descriptor address when errors occur of RX channel 0 + * Receive descriptor address when errors occur of RX channel 1 */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c) /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2137,7 +2394,7 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_CH1_REG register - * Current receive descriptor address of RX channel 0 + * Current receive descriptor address of RX channel 1 */ #define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150) /** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2150,7 +2407,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH1_S 0 /** AHB_DMA_IN_DSCR_BF0_CH1_REG register - * The last receive descriptor address of RX channel 0 + * The last receive descriptor address of RX channel 1 */ #define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154) /** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2163,7 +2420,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_IN_DSCR_BF1_CH1_REG register - * The second-to-last receive descriptor address of RX channel 0 + * The second-to-last receive descriptor address of RX channel 1 */ #define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158) /** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2176,12 +2433,12 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF1_CH1_S 0 /** AHB_DMA_IN_PRI_CH1_REG register - * Priority register of RX channel 0 + * Priority register of RX channel 1 */ #define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) /** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; * Configures the priority of RX channel 1.The larger of the value, the higher of the - * priority. + * priority.. */ #define AHB_DMA_RX_PRI_CH1 0x0000000FU #define AHB_DMA_RX_PRI_CH1_M (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S) @@ -2189,13 +2446,25 @@ extern "C" { #define AHB_DMA_RX_PRI_CH1_S 0 /** AHB_DMA_IN_PERI_SEL_CH1_REG register - * Peripheral selection register of RX channel 0 + * Peripheral selection register of RX channel 1 */ #define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x160) /** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 1.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to RX channel 1. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy */ #define AHB_DMA_PERI_IN_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH1_M (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S) @@ -2207,57 +2476,67 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190) /** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ + * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset */ #define AHB_DMA_OUT_RST_CH1 (BIT(0)) #define AHB_DMA_OUT_RST_CH1_M (AHB_DMA_OUT_RST_CH1_V << AHB_DMA_OUT_RST_CH1_S) #define AHB_DMA_OUT_RST_CH1_V 0x00000001U #define AHB_DMA_OUT_RST_CH1_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_OUT_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH1_M (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S) #define AHB_DMA_OUT_LOOP_TEST_CH1_V 0x00000001U #define AHB_DMA_OUT_LOOP_TEST_CH1_S 1 /** AHB_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) #define AHB_DMA_OUT_AUTO_WRBACK_CH1_M (AHB_DMA_OUT_AUTO_WRBACK_CH1_V << AHB_DMA_OUT_AUTO_WRBACK_CH1_S) #define AHB_DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U #define AHB_DMA_OUT_AUTO_WRBACK_CH1_S 2 /** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel 1 is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel 1 is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH1 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH1_M (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S) #define AHB_DMA_OUT_EOF_MODE_CH1_V 0x00000001U #define AHB_DMA_OUT_EOF_MODE_CH1_S 3 /** AHB_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel 1 reading - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for TX channel 1 reading + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) #define AHB_DMA_OUTDSCR_BURST_EN_CH1_M (AHB_DMA_OUTDSCR_BURST_EN_CH1_V << AHB_DMA_OUTDSCR_BURST_EN_CH1_S) #define AHB_DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U #define AHB_DMA_OUTDSCR_BURST_EN_CH1_S 4 /** AHB_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel 1.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for TX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_ETM_EN_CH1 (BIT(6)) #define AHB_DMA_OUT_ETM_EN_CH1_M (AHB_DMA_OUT_ETM_EN_CH1_V << AHB_DMA_OUT_ETM_EN_CH1_S) #define AHB_DMA_OUT_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH1_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures max burst size for TX channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S) @@ -2265,12 +2544,13 @@ extern "C" { #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S 8 /** AHB_DMA_OUT_CONF1_CH1_REG register - * Configuration register 1 of TX channel 0 + * Configuration register 1 of TX channel 1 */ #define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x194) /** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for TX channel 1.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for TX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) #define AHB_DMA_OUT_CHECK_OWNER_CH1_M (AHB_DMA_OUT_CHECK_OWNER_CH1_V << AHB_DMA_OUT_CHECK_OWNER_CH1_S) @@ -2278,53 +2558,57 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH1_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH1_REG register - * Transmit FIFO status of TX channel 0 + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198) /** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; - * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_OUTFIFO_FULL_CH1 (BIT(0)) #define AHB_DMA_OUTFIFO_FULL_CH1_M (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S) #define AHB_DMA_OUTFIFO_FULL_CH1_V 0x00000001U #define AHB_DMA_OUTFIFO_FULL_CH1_S 0 /** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) #define AHB_DMA_OUTFIFO_EMPTY_CH1_M (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S) #define AHB_DMA_OUTFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH1_S 1 /** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 1. + * Represents the number of data bytes in L1 TX FIFO for TX channel 1 */ #define AHB_DMA_OUTFIFO_CNT_CH1 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH1_M (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S) #define AHB_DMA_OUTFIFO_CNT_CH1_V 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH1_S 8 /** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 /** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 /** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 /** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S) @@ -2332,19 +2616,20 @@ extern "C" { #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 /** AHB_DMA_OUT_PUSH_CH1_REG register - * Push control register of TX channel 0 + * Push control register of TX channel 1 */ #define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c) /** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_WDATA_CH1 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_M (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S) #define AHB_DMA_OUTFIFO_WDATA_CH1_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; - * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No - * effect\\1: Push\\ + * Configures the data that need to be pushed into AHB_DMA FIFO. */ #define AHB_DMA_OUTFIFO_PUSH_CH1 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH1_M (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S) @@ -2352,35 +2637,40 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH1_S 9 /** AHB_DMA_OUT_LINK_CH1_REG register - * Linked list descriptor configuration and control register of TX channel 0 + * Push control register of TX channel 1 */ #define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0) /** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; - * Configures whether or not to stop AHB_DMA's TX channel 1 from transmitting - * data.\\0: Invalid. No effect\\1: Stop\\ + * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_OUTLINK_STOP_CH1 (BIT(0)) #define AHB_DMA_OUTLINK_STOP_CH1_M (AHB_DMA_OUTLINK_STOP_CH1_V << AHB_DMA_OUTLINK_STOP_CH1_S) #define AHB_DMA_OUTLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH1_S 0 /** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable AHB_DMA's TX channel 1 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTLINK_START_CH1 (BIT(1)) #define AHB_DMA_OUTLINK_START_CH1_M (AHB_DMA_OUTLINK_START_CH1_V << AHB_DMA_OUTLINK_START_CH1_S) #define AHB_DMA_OUTLINK_START_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH1_S 1 /** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether or not to restart TX channel 1 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart TX channel 1 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_OUTLINK_RESTART_CH1 (BIT(2)) #define AHB_DMA_OUTLINK_RESTART_CH1_M (AHB_DMA_OUTLINK_RESTART_CH1_V << AHB_DMA_OUTLINK_RESTART_CH1_S) #define AHB_DMA_OUTLINK_RESTART_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_RESTART_CH1_S 2 /** AHB_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_OUTLINK_PARK_CH1 (BIT(3)) #define AHB_DMA_OUTLINK_PARK_CH1_M (AHB_DMA_OUTLINK_PARK_CH1_V << AHB_DMA_OUTLINK_PARK_CH1_S) @@ -2388,7 +2678,7 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH1_S 3 /** AHB_DMA_OUT_STATE_CH1_REG register - * Transmit status of TX channel 0 + * Transmit status of TX channel 1 */ #define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -2415,7 +2705,7 @@ extern "C" { #define AHB_DMA_OUT_STATE_CH1_S 20 /** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register - * Transmit descriptor address when EOF occurs on TX channel 0 + * Transmit descriptor address when EOF occurs on TX channel 1 */ #define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a8) /** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2428,7 +2718,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register - * The last transmit descriptor address when EOF occurs on TX channel 0 + * The last transmit descriptor address when EOF occurs on TX channel 1 */ #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1ac) /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2441,7 +2731,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_CH1_REG register - * Current transmit descriptor address of TX channel 0 + * Current transmit descriptor address of TX channel 1 */ #define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0) /** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2454,7 +2744,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH1_REG register - * The last transmit descriptor address of TX channel 0 + * The last transmit descriptor address of TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2467,7 +2757,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH1_REG register - * The second-to-last transmit descriptor address of TX channel 0 + * The second-to-last transmit descriptor address of TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2480,12 +2770,12 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S 0 /** AHB_DMA_OUT_PRI_CH1_REG register - * Priority register of TX channel 0 + * Priority register of TX channel 1 */ #define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) /** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; * Configures the priority of TX channel 1.The larger of the value, the higher of the - * priority. + * priority.. */ #define AHB_DMA_TX_PRI_CH1 0x0000000FU #define AHB_DMA_TX_PRI_CH1_M (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S) @@ -2493,13 +2783,25 @@ extern "C" { #define AHB_DMA_TX_PRI_CH1_S 0 /** AHB_DMA_OUT_PERI_SEL_CH1_REG register - * Peripheral selection register of TX channel 0 + * Peripheral selection register of TX channel 1 */ #define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c0) /** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 1.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to TX channel 1. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy */ #define AHB_DMA_PERI_OUT_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH1_M (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S) @@ -2507,50 +2809,57 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH1_S 0 /** AHB_DMA_IN_CONF0_CH2_REG register - * Configuration register 0 of RX channel 0 + * Configuration register 0 of RX channel 2 */ #define AHB_DMA_IN_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f0) /** AHB_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH2 (BIT(0)) #define AHB_DMA_IN_RST_CH2_M (AHB_DMA_IN_RST_CH2_V << AHB_DMA_IN_RST_CH2_S) #define AHB_DMA_IN_RST_CH2_V 0x00000001U #define AHB_DMA_IN_RST_CH2_S 0 /** AHB_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_IN_LOOP_TEST_CH2 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH2_M (AHB_DMA_IN_LOOP_TEST_CH2_V << AHB_DMA_IN_LOOP_TEST_CH2_S) #define AHB_DMA_IN_LOOP_TEST_CH2_V 0x00000001U #define AHB_DMA_IN_LOOP_TEST_CH2_S 1 /** AHB_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable INCR burst transfer for RX channel 2 to read - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for RX channel 2 to read + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INDSCR_BURST_EN_CH2 (BIT(2)) #define AHB_DMA_INDSCR_BURST_EN_CH2_M (AHB_DMA_INDSCR_BURST_EN_CH2_V << AHB_DMA_INDSCR_BURST_EN_CH2_S) #define AHB_DMA_INDSCR_BURST_EN_CH2_V 0x00000001U #define AHB_DMA_INDSCR_BURST_EN_CH2_S 2 /** AHB_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_MEM_TRANS_EN_CH2 (BIT(4)) #define AHB_DMA_MEM_TRANS_EN_CH2_M (AHB_DMA_MEM_TRANS_EN_CH2_V << AHB_DMA_MEM_TRANS_EN_CH2_S) #define AHB_DMA_MEM_TRANS_EN_CH2_V 0x00000001U #define AHB_DMA_MEM_TRANS_EN_CH2_S 4 /** AHB_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ETM control for RX channel2.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for RX channel2. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_ETM_EN_CH2 (BIT(5)) #define AHB_DMA_IN_ETM_EN_CH2_M (AHB_DMA_IN_ETM_EN_CH2_V << AHB_DMA_IN_ETM_EN_CH2_S) #define AHB_DMA_IN_ETM_EN_CH2_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH2_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel2.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures max burst size for Rx channel2. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S) @@ -2558,12 +2867,13 @@ extern "C" { #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S 6 /** AHB_DMA_IN_CONF1_CH2_REG register - * Configuration register 1 of RX channel 0 + * Configuration register 1 of RX channel 2 */ #define AHB_DMA_IN_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f4) /** AHB_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for RX channel 2.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for RX channel 2. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_CHECK_OWNER_CH2 (BIT(12)) #define AHB_DMA_IN_CHECK_OWNER_CH2_M (AHB_DMA_IN_CHECK_OWNER_CH2_V << AHB_DMA_IN_CHECK_OWNER_CH2_S) @@ -2571,25 +2881,29 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH2_S 12 /** AHB_DMA_INFIFO_STATUS_CH2_REG register - * Receive FIFO status of RX channel 0 + * Receive FIFO status of RX channel 2 */ #define AHB_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f8) /** AHB_DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; - * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_INFIFO_FULL_CH2 (BIT(0)) #define AHB_DMA_INFIFO_FULL_CH2_M (AHB_DMA_INFIFO_FULL_CH2_V << AHB_DMA_INFIFO_FULL_CH2_S) #define AHB_DMA_INFIFO_FULL_CH2_V 0x00000001U #define AHB_DMA_INFIFO_FULL_CH2_S 0 /** AHB_DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_INFIFO_EMPTY_CH2 (BIT(1)) #define AHB_DMA_INFIFO_EMPTY_CH2_M (AHB_DMA_INFIFO_EMPTY_CH2_V << AHB_DMA_INFIFO_EMPTY_CH2_S) #define AHB_DMA_INFIFO_EMPTY_CH2_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH2_S 1 /** AHB_DMA_INFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 2. + * Represents the number of data bytes in L1 RX FIFO for RX channel 2 */ #define AHB_DMA_INFIFO_CNT_CH2 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH2_M (AHB_DMA_INFIFO_CNT_CH2_V << AHB_DMA_INFIFO_CNT_CH2_S) @@ -2632,7 +2946,7 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH2_S 27 /** AHB_DMA_IN_POP_CH2_REG register - * Pop control register of RX channel 0 + * Receive FIFO status of RX channel 2 */ #define AHB_DMA_IN_POP_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1fc) /** AHB_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; @@ -2643,8 +2957,9 @@ extern "C" { #define AHB_DMA_INFIFO_RDATA_CH2_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH2_S 0 /** AHB_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; - * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: - * Pop\\ + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop */ #define AHB_DMA_INFIFO_POP_CH2 (BIT(12)) #define AHB_DMA_INFIFO_POP_CH2_M (AHB_DMA_INFIFO_POP_CH2_V << AHB_DMA_INFIFO_POP_CH2_S) @@ -2652,43 +2967,51 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH2_S 12 /** AHB_DMA_IN_LINK_CH2_REG register - * Linked list descriptor configuration and control register of RX channel 0 + * Receive FIFO status of RX channel 2 */ #define AHB_DMA_IN_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x200) /** AHB_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1; - * Configures whether or not to return to current receive descriptor's address when - * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . */ #define AHB_DMA_INLINK_AUTO_RET_CH2 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH2_M (AHB_DMA_INLINK_AUTO_RET_CH2_V << AHB_DMA_INLINK_AUTO_RET_CH2_S) #define AHB_DMA_INLINK_AUTO_RET_CH2_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH2_S 0 /** AHB_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0; - * Configures whether or not to stop AHB_DMA's RX channel 2 from receiving data.\\0: - * Invalid. No effect\\1: Stop\\ + * Configures whether to stop AHB_DMA's RX channel 2 from receiving data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_INLINK_STOP_CH2 (BIT(1)) #define AHB_DMA_INLINK_STOP_CH2_M (AHB_DMA_INLINK_STOP_CH2_V << AHB_DMA_INLINK_STOP_CH2_S) #define AHB_DMA_INLINK_STOP_CH2_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH2_S 1 /** AHB_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable AHB_DMA's RX channel 2 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable AHB_DMA's RX channel 2 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INLINK_START_CH2 (BIT(2)) #define AHB_DMA_INLINK_START_CH2_M (AHB_DMA_INLINK_START_CH2_V << AHB_DMA_INLINK_START_CH2_S) #define AHB_DMA_INLINK_START_CH2_V 0x00000001U #define AHB_DMA_INLINK_START_CH2_S 2 /** AHB_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0; - * Configures whether or not to restart RX channel 2 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart RX channel 2 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_INLINK_RESTART_CH2 (BIT(3)) #define AHB_DMA_INLINK_RESTART_CH2_M (AHB_DMA_INLINK_RESTART_CH2_V << AHB_DMA_INLINK_RESTART_CH2_S) #define AHB_DMA_INLINK_RESTART_CH2_V 0x00000001U #define AHB_DMA_INLINK_RESTART_CH2_S 3 /** AHB_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_INLINK_PARK_CH2 (BIT(4)) #define AHB_DMA_INLINK_PARK_CH2_M (AHB_DMA_INLINK_PARK_CH2_V << AHB_DMA_INLINK_PARK_CH2_S) @@ -2696,12 +3019,11 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH2_S 4 /** AHB_DMA_IN_STATE_CH2_REG register - * Receive status of RX channel 0 + * Receive status of RX channel 2 */ #define AHB_DMA_IN_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x204) /** AHB_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * reserved */ #define AHB_DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH2_M (AHB_DMA_INLINK_DSCR_ADDR_CH2_V << AHB_DMA_INLINK_DSCR_ADDR_CH2_S) @@ -2715,7 +3037,8 @@ extern "C" { #define AHB_DMA_IN_DSCR_STATE_CH2_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH2_S 18 /** AHB_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * reserved + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. */ #define AHB_DMA_IN_STATE_CH2 0x00000007U #define AHB_DMA_IN_STATE_CH2_M (AHB_DMA_IN_STATE_CH2_V << AHB_DMA_IN_STATE_CH2_S) @@ -2723,7 +3046,7 @@ extern "C" { #define AHB_DMA_IN_STATE_CH2_S 20 /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register - * Receive descriptor address when EOF occurs on RX channel 0 + * Receive descriptor address when EOF occurs on RX channel 2 */ #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x208) /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2736,7 +3059,7 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register - * Receive descriptor address when errors occur of RX channel 0 + * Receive descriptor address when errors occur of RX channel 2 */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20c) /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2749,7 +3072,7 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 /** AHB_DMA_IN_DSCR_CH2_REG register - * Current receive descriptor address of RX channel 0 + * Current receive descriptor address of RX channel 2 */ #define AHB_DMA_IN_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x210) /** AHB_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2762,7 +3085,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH2_S 0 /** AHB_DMA_IN_DSCR_BF0_CH2_REG register - * The last receive descriptor address of RX channel 0 + * The last receive descriptor address of RX channel 2 */ #define AHB_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x214) /** AHB_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2775,7 +3098,7 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH2_S 0 /** AHB_DMA_IN_DSCR_BF1_CH2_REG register - * The second-to-last receive descriptor address of RX channel 0 + * The second-to-last receive descriptor address of RX channel 2 */ #define AHB_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x218) /** AHB_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2788,12 +3111,12 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF1_CH2_S 0 /** AHB_DMA_IN_PRI_CH2_REG register - * Priority register of RX channel 0 + * Priority register of RX channel 2 */ #define AHB_DMA_IN_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x21c) /** AHB_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; * Configures the priority of RX channel 2.The larger of the value, the higher of the - * priority. + * priority.. */ #define AHB_DMA_RX_PRI_CH2 0x0000000FU #define AHB_DMA_RX_PRI_CH2_M (AHB_DMA_RX_PRI_CH2_V << AHB_DMA_RX_PRI_CH2_S) @@ -2801,13 +3124,25 @@ extern "C" { #define AHB_DMA_RX_PRI_CH2_S 0 /** AHB_DMA_IN_PERI_SEL_CH2_REG register - * Peripheral selection register of RX channel 0 + * Peripheral selection register of RX channel 2 */ #define AHB_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x220) /** AHB_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 2.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to RX channel 2. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy */ #define AHB_DMA_PERI_IN_SEL_CH2 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH2_M (AHB_DMA_PERI_IN_SEL_CH2_V << AHB_DMA_PERI_IN_SEL_CH2_S) @@ -2815,61 +3150,71 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH2_S 0 /** AHB_DMA_OUT_CONF0_CH2_REG register - * Configuration register 0 of TX channel 1 + * Configuration register 0 of TX channel 2 */ #define AHB_DMA_OUT_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x250) /** AHB_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ + * Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset */ #define AHB_DMA_OUT_RST_CH2 (BIT(0)) #define AHB_DMA_OUT_RST_CH2_M (AHB_DMA_OUT_RST_CH2_V << AHB_DMA_OUT_RST_CH2_S) #define AHB_DMA_OUT_RST_CH2_V 0x00000001U #define AHB_DMA_OUT_RST_CH2_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_OUT_LOOP_TEST_CH2 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH2_M (AHB_DMA_OUT_LOOP_TEST_CH2_V << AHB_DMA_OUT_LOOP_TEST_CH2_S) #define AHB_DMA_OUT_LOOP_TEST_CH2_V 0x00000001U #define AHB_DMA_OUT_LOOP_TEST_CH2_S 1 /** AHB_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) #define AHB_DMA_OUT_AUTO_WRBACK_CH2_M (AHB_DMA_OUT_AUTO_WRBACK_CH2_V << AHB_DMA_OUT_AUTO_WRBACK_CH2_S) #define AHB_DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U #define AHB_DMA_OUT_AUTO_WRBACK_CH2_S 2 /** AHB_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel 2 is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel 2 is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 2 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 2 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH2 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH2_M (AHB_DMA_OUT_EOF_MODE_CH2_V << AHB_DMA_OUT_EOF_MODE_CH2_S) #define AHB_DMA_OUT_EOF_MODE_CH2_V 0x00000001U #define AHB_DMA_OUT_EOF_MODE_CH2_S 3 /** AHB_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel 2 reading - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for TX channel 2 reading + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) #define AHB_DMA_OUTDSCR_BURST_EN_CH2_M (AHB_DMA_OUTDSCR_BURST_EN_CH2_V << AHB_DMA_OUTDSCR_BURST_EN_CH2_S) #define AHB_DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U #define AHB_DMA_OUTDSCR_BURST_EN_CH2_S 4 /** AHB_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel 2.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for TX channel 2. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_ETM_EN_CH2 (BIT(6)) #define AHB_DMA_OUT_ETM_EN_CH2_M (AHB_DMA_OUT_ETM_EN_CH2_V << AHB_DMA_OUT_ETM_EN_CH2_S) #define AHB_DMA_OUT_ETM_EN_CH2_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH2_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel2.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures max burst size for TX channel2. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S) @@ -2877,12 +3222,13 @@ extern "C" { #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S 8 /** AHB_DMA_OUT_CONF1_CH2_REG register - * Configuration register 1 of TX channel 0 + * Configuration register 1 of TX channel 2 */ #define AHB_DMA_OUT_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x254) /** AHB_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for TX channel 2.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for TX channel 2. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) #define AHB_DMA_OUT_CHECK_OWNER_CH2_M (AHB_DMA_OUT_CHECK_OWNER_CH2_V << AHB_DMA_OUT_CHECK_OWNER_CH2_S) @@ -2890,53 +3236,57 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH2_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH2_REG register - * Transmit FIFO status of TX channel 0 + * Receive FIFO status of RX channel 2 */ #define AHB_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x258) /** AHB_DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; - * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_OUTFIFO_FULL_CH2 (BIT(0)) #define AHB_DMA_OUTFIFO_FULL_CH2_M (AHB_DMA_OUTFIFO_FULL_CH2_V << AHB_DMA_OUTFIFO_FULL_CH2_S) #define AHB_DMA_OUTFIFO_FULL_CH2_V 0x00000001U #define AHB_DMA_OUTFIFO_FULL_CH2_S 0 /** AHB_DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) #define AHB_DMA_OUTFIFO_EMPTY_CH2_M (AHB_DMA_OUTFIFO_EMPTY_CH2_V << AHB_DMA_OUTFIFO_EMPTY_CH2_S) #define AHB_DMA_OUTFIFO_EMPTY_CH2_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH2_S 1 /** AHB_DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 2. + * Represents the number of data bytes in L1 TX FIFO for TX channel 2 */ #define AHB_DMA_OUTFIFO_CNT_CH2 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH2_M (AHB_DMA_OUTFIFO_CNT_CH2_V << AHB_DMA_OUTFIFO_CNT_CH2_S) #define AHB_DMA_OUTFIFO_CNT_CH2_V 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH2_S 8 /** AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 /** AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 /** AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 /** AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S) @@ -2944,19 +3294,20 @@ extern "C" { #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 /** AHB_DMA_OUT_PUSH_CH2_REG register - * Push control register of TX channel 0 + * Push control register of TX channel 2 */ #define AHB_DMA_OUT_PUSH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x25c) /** AHB_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_WDATA_CH2 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH2_M (AHB_DMA_OUTFIFO_WDATA_CH2_V << AHB_DMA_OUTFIFO_WDATA_CH2_S) #define AHB_DMA_OUTFIFO_WDATA_CH2_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH2_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; - * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No - * effect\\1: Push\\ + * Configures the data that need to be pushed into AHB_DMA FIFO. */ #define AHB_DMA_OUTFIFO_PUSH_CH2 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH2_M (AHB_DMA_OUTFIFO_PUSH_CH2_V << AHB_DMA_OUTFIFO_PUSH_CH2_S) @@ -2964,35 +3315,40 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH2_S 9 /** AHB_DMA_OUT_LINK_CH2_REG register - * Linked list descriptor configuration and control register of TX channel 0 + * Push control register of TX channel 2 */ #define AHB_DMA_OUT_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x260) /** AHB_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0; - * Configures whether or not to stop AHB_DMA's TX channel 2 from transmitting - * data.\\0: Invalid. No effect\\1: Stop\\ + * Configures whether to stop AHB_DMA's TX channel 2 from transmitting data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_OUTLINK_STOP_CH2 (BIT(0)) #define AHB_DMA_OUTLINK_STOP_CH2_M (AHB_DMA_OUTLINK_STOP_CH2_V << AHB_DMA_OUTLINK_STOP_CH2_S) #define AHB_DMA_OUTLINK_STOP_CH2_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH2_S 0 /** AHB_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable AHB_DMA's TX channel 2 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable AHB_DMA's TX channel 2 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTLINK_START_CH2 (BIT(1)) #define AHB_DMA_OUTLINK_START_CH2_M (AHB_DMA_OUTLINK_START_CH2_V << AHB_DMA_OUTLINK_START_CH2_S) #define AHB_DMA_OUTLINK_START_CH2_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH2_S 1 /** AHB_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to restart TX channel 2 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart TX channel 2 for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_OUTLINK_RESTART_CH2 (BIT(2)) #define AHB_DMA_OUTLINK_RESTART_CH2_M (AHB_DMA_OUTLINK_RESTART_CH2_V << AHB_DMA_OUTLINK_RESTART_CH2_S) #define AHB_DMA_OUTLINK_RESTART_CH2_V 0x00000001U #define AHB_DMA_OUTLINK_RESTART_CH2_S 2 /** AHB_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_OUTLINK_PARK_CH2 (BIT(3)) #define AHB_DMA_OUTLINK_PARK_CH2_M (AHB_DMA_OUTLINK_PARK_CH2_V << AHB_DMA_OUTLINK_PARK_CH2_S) @@ -3000,7 +3356,7 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH2_S 3 /** AHB_DMA_OUT_STATE_CH2_REG register - * Transmit status of TX channel 0 + * Transmit status of TX channel 2 */ #define AHB_DMA_OUT_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x264) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; @@ -3027,7 +3383,7 @@ extern "C" { #define AHB_DMA_OUT_STATE_CH2_S 20 /** AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG register - * Transmit descriptor address when EOF occurs on TX channel 0 + * Transmit descriptor address when EOF occurs on TX channel 2 */ #define AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x268) /** AHB_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3040,7 +3396,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_DES_ADDR_CH2_S 0 /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register - * The last transmit descriptor address when EOF occurs on TX channel 0 + * The last transmit descriptor address when EOF occurs on TX channel 2 */ #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x26c) /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3053,7 +3409,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 /** AHB_DMA_OUT_DSCR_CH2_REG register - * Current transmit descriptor address of TX channel 0 + * Current transmit descriptor address of TX channel 2 */ #define AHB_DMA_OUT_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x270) /** AHB_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3066,7 +3422,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH2_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH2_REG register - * The last transmit descriptor address of TX channel 0 + * The last transmit descriptor address of TX channel 2 */ #define AHB_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x274) /** AHB_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3079,7 +3435,7 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH2_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH2_REG register - * The second-to-last transmit descriptor address of TX channel 0 + * The second-to-last transmit descriptor address of TX channel 2 */ #define AHB_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x278) /** AHB_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; @@ -3092,12 +3448,12 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF1_CH2_S 0 /** AHB_DMA_OUT_PRI_CH2_REG register - * Priority register of TX channel 0 + * Priority register of TX channel 2 */ #define AHB_DMA_OUT_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x27c) /** AHB_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; * Configures the priority of TX channel 2.The larger of the value, the higher of the - * priority. + * priority.. */ #define AHB_DMA_TX_PRI_CH2 0x0000000FU #define AHB_DMA_TX_PRI_CH2_M (AHB_DMA_TX_PRI_CH2_V << AHB_DMA_TX_PRI_CH2_S) @@ -3105,141 +3461,154 @@ extern "C" { #define AHB_DMA_TX_PRI_CH2_S 0 /** AHB_DMA_OUT_PERI_SEL_CH2_REG register - * Peripheral selection register of TX channel 0 + * Peripheral selection register of TX channel 2 */ #define AHB_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x280) /** AHB_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 2.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to TX channel 2. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy + * \ */ #define AHB_DMA_PERI_OUT_SEL_CH2 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH2_M (AHB_DMA_PERI_OUT_SEL_CH2_V << AHB_DMA_PERI_OUT_SEL_CH2_S) #define AHB_DMA_PERI_OUT_SEL_CH2_V 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH2_S 0 -/** AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG register +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG register * TX channel 0 arbitration weight configuration register */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) -/** AHB_DMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; * Configures the weight(i.e the number of tokens) of TX channel0 */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_M (AHB_DMA_TX_CH_ARB_WEIGH_CH0_V << AHB_DMA_TX_CH_ARB_WEIGH_CH0_S) -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_V 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S 0 -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG register +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG register * TX channel 0 weight arbitration optimization enable register */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; * reserved */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S 0 -/** AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG register - * TX channel 0 arbitration weight configuration register +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG register + * TX channel 1 arbitration weight configuration register */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) -/** AHB_DMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; * Configures the weight(i.e the number of tokens) of TX channel1 */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_M (AHB_DMA_TX_CH_ARB_WEIGH_CH1_V << AHB_DMA_TX_CH_ARB_WEIGH_CH1_S) -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_V 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S 0 -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG register - * TX channel 0 weight arbitration optimization enable register +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG register + * TX channel 1 weight arbitration optimization enable register */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; * reserved */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S 0 -/** AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG register - * TX channel 0 arbitration weight configuration register +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG register + * TX channel 2 arbitration weight configuration register */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x32c) -/** AHB_DMA_TX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0; +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x32c) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 : R/W; bitpos: [3:0]; default: 0; * Configures the weight(i.e the number of tokens) of TX channel2 */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH2 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_M (AHB_DMA_TX_CH_ARB_WEIGH_CH2_V << AHB_DMA_TX_CH_ARB_WEIGH_CH2_S) -#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_V 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S 0 -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG register - * TX channel 0 weight arbitration optimization enable register +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG register + * TX channel 2 weight arbitration optimization enable register */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x330) -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0; +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x330) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [0]; default: 0; * reserved */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S 0 -/** AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG register +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG register * RX channel 0 arbitration weight configuration register */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) -/** AHB_DMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) +/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; * Configures the weight(i.e the number of tokens) of RX channel0 */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_M (AHB_DMA_RX_CH_ARB_WEIGH_CH0_V << AHB_DMA_RX_CH_ARB_WEIGH_CH0_S) -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_V 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S) +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S 0 -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG register +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG register * RX channel 0 weight arbitration optimization enable register */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; * reserved */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S 0 -/** AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG register - * RX channel 0 arbitration weight configuration register +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG register + * RX channel 1 arbitration weight configuration register */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) -/** AHB_DMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) +/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; * Configures the weight(i.e the number of tokens) of RX channel1 */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_M (AHB_DMA_RX_CH_ARB_WEIGH_CH1_V << AHB_DMA_RX_CH_ARB_WEIGH_CH1_S) -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_V 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S) +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S 0 -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG register - * RX channel 0 weight arbitration optimization enable register +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG register + * RX channel 1 weight arbitration optimization enable register */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; * reserved */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S 0 /** AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG register - * RX channel 0 arbitration weight configuration register + * RX channel 2 arbitration weight configuration register */ #define AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a4) /** AHB_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0; @@ -3250,24 +3619,24 @@ extern "C" { #define AHB_DMA_RX_CH_ARB_WEIGH_CH2_V 0x0000000FU #define AHB_DMA_RX_CH_ARB_WEIGH_CH2_S 0 -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG register - * RX channel 0 weight arbitration optimization enable register +/** AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2_REG register + * RX channel 2 weight arbitration optimization enable register */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a8) -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0; +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a8) +/** AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2 : R/W; bitpos: [0]; default: 0; * reserved */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S 0 +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2_S) +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGH_OPT_DIS_CH2_S 0 /** AHB_DMA_IN_LINK_ADDR_CH0_REG register * Link list descriptor address configuration of RX channel 0 */ #define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac) /** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Configures the 32 bits of the first receive descriptor's address */ #define AHB_DMA_INLINK_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH0_M (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S) @@ -3275,11 +3644,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH0_S 0 /** AHB_DMA_IN_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of RX channel 0 + * Link list descriptor address configuration of RX channel 1 */ #define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0) /** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Configures the 32 bits of the first receive descriptor's address */ #define AHB_DMA_INLINK_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH1_M (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S) @@ -3287,11 +3656,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH1_S 0 /** AHB_DMA_IN_LINK_ADDR_CH2_REG register - * Link list descriptor address configuration of RX channel 0 + * Link list descriptor address configuration of RX channel 2 */ #define AHB_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b4) /** AHB_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Configures the 32 bits of the first receive descriptor's address */ #define AHB_DMA_INLINK_ADDR_CH2 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH2_M (AHB_DMA_INLINK_ADDR_CH2_V << AHB_DMA_INLINK_ADDR_CH2_S) @@ -3311,7 +3680,7 @@ extern "C" { #define AHB_DMA_OUTLINK_ADDR_CH0_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of TX channel 0 + * Link list descriptor address configuration of TX channel 1 */ #define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc) /** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; @@ -3323,7 +3692,7 @@ extern "C" { #define AHB_DMA_OUTLINK_ADDR_CH1_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH2_REG register - * Link list descriptor address configuration of TX channel 0 + * Link list descriptor address configuration of TX channel 2 */ #define AHB_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3c0) /** AHB_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; @@ -3339,7 +3708,7 @@ extern "C" { */ #define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c4) /** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * Configures the start address of accessible address space. + * Accessible address space start address configuration register */ #define AHB_DMA_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU #define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S) @@ -3358,53 +3727,210 @@ extern "C" { #define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V 0xFFFFFFFFU #define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S 0 -/** AHB_DMA_ARB_TIMEOUT_TX_REG register +/** AHB_DMA_ARB_TIMEOUT_REG register * TX arbitration timeout configuration register */ -#define AHB_DMA_ARB_TIMEOUT_TX_REG (DR_REG_AHB_DMA_BASE + 0x3cc) -/** AHB_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. +#define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x3dc) +/** AHB_DMA_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot. Measurement unit: AHB bus clock cycle. */ -#define AHB_DMA_ARB_TIMEOUT_TX 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_TX_M (AHB_DMA_ARB_TIMEOUT_TX_V << AHB_DMA_ARB_TIMEOUT_TX_S) -#define AHB_DMA_ARB_TIMEOUT_TX_V 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_TX_S 0 +#define AHB_DMA_ARB_TIMEOUT_NUM 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_NUM_M (AHB_DMA_ARB_TIMEOUT_NUM_V << AHB_DMA_ARB_TIMEOUT_NUM_S) +#define AHB_DMA_ARB_TIMEOUT_NUM_V 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_NUM_S 0 -/** AHB_DMA_ARB_TIMEOUT_RX_REG register - * RX arbitration timeout configuration register - */ -#define AHB_DMA_ARB_TIMEOUT_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d0) -/** AHB_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. - */ -#define AHB_DMA_ARB_TIMEOUT_RX 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_RX_M (AHB_DMA_ARB_TIMEOUT_RX_V << AHB_DMA_ARB_TIMEOUT_RX_S) -#define AHB_DMA_ARB_TIMEOUT_RX_V 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_RX_S 0 - -/** AHB_DMA_WEIGHT_EN_TX_REG register +/** AHB_DMA_WEIGHT_EN_REG register * TX weight arbitration enable register */ -#define AHB_DMA_WEIGHT_EN_TX_REG (DR_REG_AHB_DMA_BASE + 0x3d4) -/** AHB_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for TX.\\0: Disable\\1: Enable\\ +#define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x400) +/** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration. + * 0: Disable + * 1: Enable */ -#define AHB_DMA_WEIGHT_EN_TX (BIT(0)) -#define AHB_DMA_WEIGHT_EN_TX_M (AHB_DMA_WEIGHT_EN_TX_V << AHB_DMA_WEIGHT_EN_TX_S) -#define AHB_DMA_WEIGHT_EN_TX_V 0x00000001U -#define AHB_DMA_WEIGHT_EN_TX_S 0 +#define AHB_DMA_WEIGHT_EN (BIT(0)) +#define AHB_DMA_WEIGHT_EN_M (AHB_DMA_WEIGHT_EN_V << AHB_DMA_WEIGHT_EN_S) +#define AHB_DMA_WEIGHT_EN_V 0x00000001U +#define AHB_DMA_WEIGHT_EN_S 0 -/** AHB_DMA_WEIGHT_EN_RX_REG register - * RX weight arbitration enable register +/** AHB_DMA_MODULE_CLK_EN_REG register + * Module clock force on register */ -#define AHB_DMA_WEIGHT_EN_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d8) -/** AHB_DMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for RX.\\0: Disable\\1: Enable\\ +#define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x404) +/** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [2:0]; default: 7; + * Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n: + * 0 : Not force on ahb_apb_sync n clock + * 1 : Force on ahb_apb_sync n clock */ -#define AHB_DMA_WEIGHT_EN_RX (BIT(0)) -#define AHB_DMA_WEIGHT_EN_RX_M (AHB_DMA_WEIGHT_EN_RX_V << AHB_DMA_WEIGHT_EN_RX_S) -#define AHB_DMA_WEIGHT_EN_RX_V 0x00000001U -#define AHB_DMA_WEIGHT_EN_RX_S 0 +#define AHB_DMA_AHB_APB_SYNC_CLK_EN 0x00000007U +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_M (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S) +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_V 0x00000007U +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_S 0 +/** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [5:3]; default: 7; + * Configures whether to force on out_dscr 2~0 module clock. For bit n: + * 0 : Not force on out_dscr n clock + * 1 : Force on out_dscr n clock + */ +#define AHB_DMA_OUT_DSCR_CLK_EN 0x00000007U +#define AHB_DMA_OUT_DSCR_CLK_EN_M (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S) +#define AHB_DMA_OUT_DSCR_CLK_EN_V 0x00000007U +#define AHB_DMA_OUT_DSCR_CLK_EN_S 3 +/** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [8:6]; default: 7; + * Configures whether to force on out_ctrl 2~0 module clock. For bit n: + * 0 : Not force on out_ctrl n clock + * 1 : Force on out_ctrl n clock + */ +#define AHB_DMA_OUT_CTRL_CLK_EN 0x00000007U +#define AHB_DMA_OUT_CTRL_CLK_EN_M (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S) +#define AHB_DMA_OUT_CTRL_CLK_EN_V 0x00000007U +#define AHB_DMA_OUT_CTRL_CLK_EN_S 6 +/** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [11:9]; default: 7; + * Configures whether to force on in_dscr 2~0 module clock. For bit n: + * 0 : Not force on in_dscr n clock + * 1 : Force on in_dscr n clock + */ +#define AHB_DMA_IN_DSCR_CLK_EN 0x00000007U +#define AHB_DMA_IN_DSCR_CLK_EN_M (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S) +#define AHB_DMA_IN_DSCR_CLK_EN_V 0x00000007U +#define AHB_DMA_IN_DSCR_CLK_EN_S 9 +/** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [14:12]; default: 7; + * Configures whether to force on in_ctrl 2~0 module clock. For bit n: + * 0 : Not force on in_ctrl n clock + * 1 : Force on in_ctrl n clock + */ +#define AHB_DMA_IN_CTRL_CLK_EN 0x00000007U +#define AHB_DMA_IN_CTRL_CLK_EN_M (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S) +#define AHB_DMA_IN_CTRL_CLK_EN_V 0x00000007U +#define AHB_DMA_IN_CTRL_CLK_EN_S 12 +/** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 0; + * Configures whether to force on cmd_arb module clock. + * 0 : Not force on cmd_arb clock + * 1 : Force on cmd_arb clock + */ +#define AHB_DMA_CMD_ARB_CLK_EN (BIT(27)) +#define AHB_DMA_CMD_ARB_CLK_EN_M (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S) +#define AHB_DMA_CMD_ARB_CLK_EN_V 0x00000001U +#define AHB_DMA_CMD_ARB_CLK_EN_S 27 +/** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 0; + * Configures whether to force on ahbinf module clock. + * 0 : Not force on ahbinf clock + * 1 : Force on ahbinf clock + */ +#define AHB_DMA_AHBINF_CLK_EN (BIT(28)) +#define AHB_DMA_AHBINF_CLK_EN_M (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S) +#define AHB_DMA_AHBINF_CLK_EN_V 0x00000001U +#define AHB_DMA_AHBINF_CLK_EN_S 28 + +/** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register + * AHB response error status 0 register + */ +#define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x408) +/** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents the address of the AHB response error. + */ +#define AHB_DMA_AHBINF_RESP_ERR_ADDR 0xFFFFFFFFU +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_M (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S) +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_V 0xFFFFFFFFU +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_S 0 + +/** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register + * AHB response error status 1 register + */ +#define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x40c) +/** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0; + * Represents the AHB response error is write request. + */ +#define AHB_DMA_AHBINF_RESP_ERR_WR (BIT(0)) +#define AHB_DMA_AHBINF_RESP_ERR_WR_M (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S) +#define AHB_DMA_AHBINF_RESP_ERR_WR_V 0x00000001U +#define AHB_DMA_AHBINF_RESP_ERR_WR_S 0 +/** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [4:1]; default: 15; + * Represents the AHB response error request id. + */ +#define AHB_DMA_AHBINF_RESP_ERR_ID 0x0000000FU +#define AHB_DMA_AHBINF_RESP_ERR_ID_M (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S) +#define AHB_DMA_AHBINF_RESP_ERR_ID_V 0x0000000FU +#define AHB_DMA_AHBINF_RESP_ERR_ID_S 1 +/** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [7:5]; default: 0; + * Represents the AHB response error request channel id.bit[2]=1:TX channel. + * bit[2]=0:RX channel. + */ +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID 0x00000007U +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S) +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_V 0x00000007U +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_S 5 + +/** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register + * RX_done Inlink descriptor address of RX channel 0 + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x410) +/** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_M (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S) +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH0_S 0 + +/** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register + * TX done outlink descriptor address of TX channel 0 + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x414) +/** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_M (AHB_DMA_OUT_DONE_DES_ADDR_CH0_V << AHB_DMA_OUT_DONE_DES_ADDR_CH0_S) +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_S 0 + +/** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register + * RX_done Inlink descriptor address of RX channel 1 + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x418) +/** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_M (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S) +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH1_S 0 + +/** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register + * TX done outlink descriptor address of TX channel 1 + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x41c) +/** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_M (AHB_DMA_OUT_DONE_DES_ADDR_CH1_V << AHB_DMA_OUT_DONE_DES_ADDR_CH1_S) +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_S 0 + +/** AHB_DMA_IN_DONE_DES_ADDR_CH2_REG register + * RX_done Inlink descriptor address of RX channel 2 + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x420) +/** AHB_DMA_IN_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ +#define AHB_DMA_IN_DONE_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_M (AHB_DMA_IN_DONE_DES_ADDR_CH2_V << AHB_DMA_IN_DONE_DES_ADDR_CH2_S) +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_IN_DONE_DES_ADDR_CH2_S 0 + +/** AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG register + * TX done outlink descriptor address of TX channel 2 + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x424) +/** AHB_DMA_OUT_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_M (AHB_DMA_OUT_DONE_DES_ADDR_CH2_V << AHB_DMA_OUT_DONE_DES_ADDR_CH2_S) +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_V 0xFFFFFFFFU +#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h b/components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h deleted file mode 100644 index 3a48a96c91..0000000000 --- a/components/soc/esp32c5/register/soc/ahb_dma_reg_eco2.h +++ /dev/null @@ -1,3977 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** AHB_DMA_IN_INT_RAW_CH0_REG register - * Raw interrupt status of RX channel 0 - */ -#define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0) -/** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT - */ -#define AHB_DMA_IN_DONE_CH0_INT_RAW (BIT(0)) -#define AHB_DMA_IN_DONE_CH0_INT_RAW_M (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S) -#define AHB_DMA_IN_DONE_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DONE_CH0_INT_RAW_S 0 -/** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 -/** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 -/** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT - */ -#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S) -#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S 5 -/** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT - */ -#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S) -#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S 7 - -/** AHB_DMA_IN_INT_ST_CH0_REG register - * Masked interrupt status of RX channel 0 - */ -#define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4) -/** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT - */ -#define AHB_DMA_IN_DONE_CH0_INT_ST (BIT(0)) -#define AHB_DMA_IN_DONE_CH0_INT_ST_M (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S) -#define AHB_DMA_IN_DONE_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DONE_CH0_INT_ST_S 0 -/** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S 1 -/** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 -/** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT - */ -#define AHB_DMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S) -#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S 5 -/** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT - */ -#define AHB_DMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S) -#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S 7 - -/** AHB_DMA_IN_INT_ENA_CH0_REG register - * Interrupt enable bits of RX channel 0 - */ -#define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8) -/** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT - */ -#define AHB_DMA_IN_DONE_CH0_INT_ENA (BIT(0)) -#define AHB_DMA_IN_DONE_CH0_INT_ENA_M (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S) -#define AHB_DMA_IN_DONE_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DONE_CH0_INT_ENA_S 0 -/** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 -/** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 -/** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT - */ -#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S) -#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S 5 -/** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT - */ -#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S) -#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S 7 - -/** AHB_DMA_IN_INT_CLR_CH0_REG register - * Interrupt clear bits of RX channel 0 - */ -#define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc) -/** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT - */ -#define AHB_DMA_IN_DONE_CH0_INT_CLR (BIT(0)) -#define AHB_DMA_IN_DONE_CH0_INT_CLR_M (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S) -#define AHB_DMA_IN_DONE_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DONE_CH0_INT_CLR_S 0 -/** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S) -#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 -/** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S) -#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S) -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 -/** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT - */ -#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S) -#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S 5 -/** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT - */ -#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S) -#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S 7 - -/** AHB_DMA_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 1 - */ -#define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10) -/** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT - */ -#define AHB_DMA_IN_DONE_CH1_INT_RAW (BIT(0)) -#define AHB_DMA_IN_DONE_CH1_INT_RAW_M (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S) -#define AHB_DMA_IN_DONE_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DONE_CH1_INT_RAW_S 0 -/** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 -/** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 -/** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT - */ -#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S) -#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S 5 -/** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT - */ -#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S) -#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S 7 - -/** AHB_DMA_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 1 - */ -#define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14) -/** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT - */ -#define AHB_DMA_IN_DONE_CH1_INT_ST (BIT(0)) -#define AHB_DMA_IN_DONE_CH1_INT_ST_M (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S) -#define AHB_DMA_IN_DONE_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DONE_CH1_INT_ST_S 0 -/** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S 1 -/** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 -/** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT - */ -#define AHB_DMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S) -#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S 5 -/** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT - */ -#define AHB_DMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S) -#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S 7 - -/** AHB_DMA_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 1 - */ -#define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18) -/** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT - */ -#define AHB_DMA_IN_DONE_CH1_INT_ENA (BIT(0)) -#define AHB_DMA_IN_DONE_CH1_INT_ENA_M (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S) -#define AHB_DMA_IN_DONE_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DONE_CH1_INT_ENA_S 0 -/** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 -/** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 -/** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT - */ -#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S) -#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S 5 -/** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT - */ -#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S) -#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S 7 - -/** AHB_DMA_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 1 - */ -#define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c) -/** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT - */ -#define AHB_DMA_IN_DONE_CH1_INT_CLR (BIT(0)) -#define AHB_DMA_IN_DONE_CH1_INT_CLR_M (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S) -#define AHB_DMA_IN_DONE_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DONE_CH1_INT_CLR_S 0 -/** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S) -#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 -/** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S) -#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S) -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 -/** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT - */ -#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S) -#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S 5 -/** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT - */ -#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S) -#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S 7 - -/** AHB_DMA_IN_INT_RAW_CH2_REG register - * Raw interrupt status of RX channel 2 - */ -#define AHB_DMA_IN_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20) -/** AHB_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT - */ -#define AHB_DMA_IN_DONE_CH2_INT_RAW (BIT(0)) -#define AHB_DMA_IN_DONE_CH2_INT_RAW_M (AHB_DMA_IN_DONE_CH2_INT_RAW_V << AHB_DMA_IN_DONE_CH2_INT_RAW_S) -#define AHB_DMA_IN_DONE_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DONE_CH2_INT_RAW_S 0 -/** AHB_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 -/** AHB_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 -/** AHB_DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT - */ -#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S) -#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S 5 -/** AHB_DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT - */ -#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S) -#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S 7 - -/** AHB_DMA_IN_INT_ST_CH2_REG register - * Masked interrupt status of RX channel 2 - */ -#define AHB_DMA_IN_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x24) -/** AHB_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT - */ -#define AHB_DMA_IN_DONE_CH2_INT_ST (BIT(0)) -#define AHB_DMA_IN_DONE_CH2_INT_ST_M (AHB_DMA_IN_DONE_CH2_INT_ST_V << AHB_DMA_IN_DONE_CH2_INT_ST_S) -#define AHB_DMA_IN_DONE_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DONE_CH2_INT_ST_S 0 -/** AHB_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S 1 -/** AHB_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 -/** AHB_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT - */ -#define AHB_DMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_M (AHB_DMA_INFIFO_OVF_CH2_INT_ST_V << AHB_DMA_INFIFO_OVF_CH2_INT_ST_S) -#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_S 5 -/** AHB_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT - */ -#define AHB_DMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_M (AHB_DMA_INFIFO_UDF_CH2_INT_ST_V << AHB_DMA_INFIFO_UDF_CH2_INT_ST_S) -#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S 7 - -/** AHB_DMA_IN_INT_ENA_CH2_REG register - * Interrupt enable bits of RX channel 2 - */ -#define AHB_DMA_IN_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x28) -/** AHB_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH2_INT - */ -#define AHB_DMA_IN_DONE_CH2_INT_ENA (BIT(0)) -#define AHB_DMA_IN_DONE_CH2_INT_ENA_M (AHB_DMA_IN_DONE_CH2_INT_ENA_V << AHB_DMA_IN_DONE_CH2_INT_ENA_S) -#define AHB_DMA_IN_DONE_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DONE_CH2_INT_ENA_S 0 -/** AHB_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 -/** AHB_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 -/** AHB_DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT - */ -#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S) -#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S 5 -/** AHB_DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT - */ -#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S) -#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S 7 - -/** AHB_DMA_IN_INT_CLR_CH2_REG register - * Interrupt clear bits of RX channel 2 - */ -#define AHB_DMA_IN_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x2c) -/** AHB_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH2_INT - */ -#define AHB_DMA_IN_DONE_CH2_INT_CLR (BIT(0)) -#define AHB_DMA_IN_DONE_CH2_INT_CLR_M (AHB_DMA_IN_DONE_CH2_INT_CLR_V << AHB_DMA_IN_DONE_CH2_INT_CLR_S) -#define AHB_DMA_IN_DONE_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DONE_CH2_INT_CLR_S 0 -/** AHB_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT - */ -#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S) -#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 -/** AHB_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT - */ -#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S) -#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 -/** AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S) -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 -/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 -/** AHB_DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT - */ -#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) -#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S) -#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S 5 -/** AHB_DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT - */ -#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) -#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S) -#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S 6 -/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT - */ -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR (BIT(7)) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S) -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S 7 - -/** AHB_DMA_OUT_INT_RAW_CH0_REG register - * //Raw interrupt status of TX channel 0 - */ -#define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30) -/** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT - */ -#define AHB_DMA_OUT_DONE_CH0_INT_RAW (BIT(0)) -#define AHB_DMA_OUT_DONE_CH0_INT_RAW_M (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S) -#define AHB_DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH0_INT_RAW_S 0 -/** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT - */ -#define AHB_DMA_OUT_EOF_CH0_INT_RAW (BIT(1)) -#define AHB_DMA_OUT_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S) -#define AHB_DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH0_INT_RAW_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S 6 - -/** AHB_DMA_OUT_INT_ST_CH0_REG register - * Masked interrupt status of TX channel 0 - */ -#define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34) -/** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT - */ -#define AHB_DMA_OUT_DONE_CH0_INT_ST (BIT(0)) -#define AHB_DMA_OUT_DONE_CH0_INT_ST_M (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S) -#define AHB_DMA_OUT_DONE_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH0_INT_ST_S 0 -/** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT - */ -#define AHB_DMA_OUT_EOF_CH0_INT_ST (BIT(1)) -#define AHB_DMA_OUT_EOF_CH0_INT_ST_M (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S) -#define AHB_DMA_OUT_EOF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH0_INT_ST_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S 6 - -/** AHB_DMA_OUT_INT_ENA_CH0_REG register - * Interrupt enable bits of TX channel 0 - */ -#define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38) -/** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT - */ -#define AHB_DMA_OUT_DONE_CH0_INT_ENA (BIT(0)) -#define AHB_DMA_OUT_DONE_CH0_INT_ENA_M (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S) -#define AHB_DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH0_INT_ENA_S 0 -/** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT - */ -#define AHB_DMA_OUT_EOF_CH0_INT_ENA (BIT(1)) -#define AHB_DMA_OUT_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S) -#define AHB_DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH0_INT_ENA_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S 6 - -/** AHB_DMA_OUT_INT_CLR_CH0_REG register - * Interrupt clear bits of TX channel 0 - */ -#define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c) -/** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT - */ -#define AHB_DMA_OUT_DONE_CH0_INT_CLR (BIT(0)) -#define AHB_DMA_OUT_DONE_CH0_INT_CLR_M (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S) -#define AHB_DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH0_INT_CLR_S 0 -/** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT - */ -#define AHB_DMA_OUT_EOF_CH0_INT_CLR (BIT(1)) -#define AHB_DMA_OUT_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S) -#define AHB_DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH0_INT_CLR_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S) -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S) -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S 6 - -/** AHB_DMA_OUT_INT_RAW_CH1_REG register - * //Raw interrupt status of TX channel 1 - */ -#define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40) -/** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT - */ -#define AHB_DMA_OUT_DONE_CH1_INT_RAW (BIT(0)) -#define AHB_DMA_OUT_DONE_CH1_INT_RAW_M (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S) -#define AHB_DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH1_INT_RAW_S 0 -/** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT - */ -#define AHB_DMA_OUT_EOF_CH1_INT_RAW (BIT(1)) -#define AHB_DMA_OUT_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S) -#define AHB_DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH1_INT_RAW_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S 6 - -/** AHB_DMA_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 1 - */ -#define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44) -/** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT - */ -#define AHB_DMA_OUT_DONE_CH1_INT_ST (BIT(0)) -#define AHB_DMA_OUT_DONE_CH1_INT_ST_M (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S) -#define AHB_DMA_OUT_DONE_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH1_INT_ST_S 0 -/** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT - */ -#define AHB_DMA_OUT_EOF_CH1_INT_ST (BIT(1)) -#define AHB_DMA_OUT_EOF_CH1_INT_ST_M (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S) -#define AHB_DMA_OUT_EOF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH1_INT_ST_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S 6 - -/** AHB_DMA_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 1 - */ -#define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48) -/** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT - */ -#define AHB_DMA_OUT_DONE_CH1_INT_ENA (BIT(0)) -#define AHB_DMA_OUT_DONE_CH1_INT_ENA_M (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S) -#define AHB_DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH1_INT_ENA_S 0 -/** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT - */ -#define AHB_DMA_OUT_EOF_CH1_INT_ENA (BIT(1)) -#define AHB_DMA_OUT_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S) -#define AHB_DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH1_INT_ENA_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S 6 - -/** AHB_DMA_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 1 - */ -#define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c) -/** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT - */ -#define AHB_DMA_OUT_DONE_CH1_INT_CLR (BIT(0)) -#define AHB_DMA_OUT_DONE_CH1_INT_CLR_M (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S) -#define AHB_DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH1_INT_CLR_S 0 -/** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT - */ -#define AHB_DMA_OUT_EOF_CH1_INT_CLR (BIT(1)) -#define AHB_DMA_OUT_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S) -#define AHB_DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH1_INT_CLR_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S) -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S) -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S 6 - -/** AHB_DMA_OUT_INT_RAW_CH2_REG register - * //Raw interrupt status of TX channel 2 - */ -#define AHB_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x50) -/** AHB_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT - */ -#define AHB_DMA_OUT_DONE_CH2_INT_RAW (BIT(0)) -#define AHB_DMA_OUT_DONE_CH2_INT_RAW_M (AHB_DMA_OUT_DONE_CH2_INT_RAW_V << AHB_DMA_OUT_DONE_CH2_INT_RAW_S) -#define AHB_DMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH2_INT_RAW_S 0 -/** AHB_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT - */ -#define AHB_DMA_OUT_EOF_CH2_INT_RAW (BIT(1)) -#define AHB_DMA_OUT_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_EOF_CH2_INT_RAW_S) -#define AHB_DMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH2_INT_RAW_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S 6 - -/** AHB_DMA_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 2 - */ -#define AHB_DMA_OUT_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x54) -/** AHB_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT - */ -#define AHB_DMA_OUT_DONE_CH2_INT_ST (BIT(0)) -#define AHB_DMA_OUT_DONE_CH2_INT_ST_M (AHB_DMA_OUT_DONE_CH2_INT_ST_V << AHB_DMA_OUT_DONE_CH2_INT_ST_S) -#define AHB_DMA_OUT_DONE_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH2_INT_ST_S 0 -/** AHB_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT - */ -#define AHB_DMA_OUT_EOF_CH2_INT_ST (BIT(1)) -#define AHB_DMA_OUT_EOF_CH2_INT_ST_M (AHB_DMA_OUT_EOF_CH2_INT_ST_V << AHB_DMA_OUT_EOF_CH2_INT_ST_S) -#define AHB_DMA_OUT_EOF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH2_INT_ST_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S 6 - -/** AHB_DMA_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 2 - */ -#define AHB_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x58) -/** AHB_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT - */ -#define AHB_DMA_OUT_DONE_CH2_INT_ENA (BIT(0)) -#define AHB_DMA_OUT_DONE_CH2_INT_ENA_M (AHB_DMA_OUT_DONE_CH2_INT_ENA_V << AHB_DMA_OUT_DONE_CH2_INT_ENA_S) -#define AHB_DMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH2_INT_ENA_S 0 -/** AHB_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT - */ -#define AHB_DMA_OUT_EOF_CH2_INT_ENA (BIT(1)) -#define AHB_DMA_OUT_EOF_CH2_INT_ENA_M (AHB_DMA_OUT_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_EOF_CH2_INT_ENA_S) -#define AHB_DMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH2_INT_ENA_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S 6 - -/** AHB_DMA_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 2 - */ -#define AHB_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x5c) -/** AHB_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT - */ -#define AHB_DMA_OUT_DONE_CH2_INT_CLR (BIT(0)) -#define AHB_DMA_OUT_DONE_CH2_INT_CLR_M (AHB_DMA_OUT_DONE_CH2_INT_CLR_V << AHB_DMA_OUT_DONE_CH2_INT_CLR_S) -#define AHB_DMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_DONE_CH2_INT_CLR_S 0 -/** AHB_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT - */ -#define AHB_DMA_OUT_EOF_CH2_INT_CLR (BIT(1)) -#define AHB_DMA_OUT_EOF_CH2_INT_CLR_M (AHB_DMA_OUT_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_EOF_CH2_INT_CLR_S) -#define AHB_DMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_EOF_CH2_INT_CLR_S 1 -/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S) -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 -/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 -/** AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S) -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 -/** AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT - */ -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S) -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 -/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT - */ -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR (BIT(6)) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S) -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V 0x00000001U -#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S 6 - -/** AHB_DMA_AHB_TEST_REG register - * only for test - */ -#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60) -/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; - * reserved - */ -#define AHB_DMA_AHB_TESTMODE 0x00000007U -#define AHB_DMA_AHB_TESTMODE_M (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S) -#define AHB_DMA_AHB_TESTMODE_V 0x00000007U -#define AHB_DMA_AHB_TESTMODE_S 0 -/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; - * reserved - */ -#define AHB_DMA_AHB_TESTADDR 0x00000003U -#define AHB_DMA_AHB_TESTADDR_M (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S) -#define AHB_DMA_AHB_TESTADDR_V 0x00000003U -#define AHB_DMA_AHB_TESTADDR_S 4 - -/** AHB_DMA_MISC_CONF_REG register - * reserved - */ -#define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0x64) -/** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM - */ -#define AHB_DMA_AHBM_RST_INTER (BIT(0)) -#define AHB_DMA_AHBM_RST_INTER_M (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S) -#define AHB_DMA_AHBM_RST_INTER_V 0x00000001U -#define AHB_DMA_AHBM_RST_INTER_S 0 -/** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; - * Configures whether to disable the fixed-priority channel arbitration. - * 0: Enable - * 1: Disable - */ -#define AHB_DMA_ARB_PRI_DIS (BIT(2)) -#define AHB_DMA_ARB_PRI_DIS_M (AHB_DMA_ARB_PRI_DIS_V << AHB_DMA_ARB_PRI_DIS_S) -#define AHB_DMA_ARB_PRI_DIS_V 0x00000001U -#define AHB_DMA_ARB_PRI_DIS_S 2 -/** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0; - * Configures clock gating. - * 0: Support clock only when the application writes registers. - * 1: Always force the clock on for registers. - */ -#define AHB_DMA_CLK_EN (BIT(3)) -#define AHB_DMA_CLK_EN_M (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S) -#define AHB_DMA_CLK_EN_V 0x00000001U -#define AHB_DMA_CLK_EN_S 3 - -/** AHB_DMA_DATE_REG register - * Version control register - */ -#define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0x68) -/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 2410220; - * Version control register - */ -#define AHB_DMA_DATE 0xFFFFFFFFU -#define AHB_DMA_DATE_M (AHB_DMA_DATE_V << AHB_DMA_DATE_S) -#define AHB_DMA_DATE_V 0xFFFFFFFFU -#define AHB_DMA_DATE_S 0 - -/** AHB_DMA_IN_CONF0_CH0_REG register - * Configuration register 0 of RX channel 0 - */ -#define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x70) -/** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. - */ -#define AHB_DMA_IN_RST_CH0 (BIT(0)) -#define AHB_DMA_IN_RST_CH0_M (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S) -#define AHB_DMA_IN_RST_CH0_V 0x00000001U -#define AHB_DMA_IN_RST_CH0_S 0 -/** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define AHB_DMA_IN_LOOP_TEST_CH0 (BIT(1)) -#define AHB_DMA_IN_LOOP_TEST_CH0_M (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S) -#define AHB_DMA_IN_LOOP_TEST_CH0_V 0x00000001U -#define AHB_DMA_IN_LOOP_TEST_CH0_S 1 -/** AHB_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 0 to read - * descriptors. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_INDSCR_BURST_EN_CH0 (BIT(2)) -#define AHB_DMA_INDSCR_BURST_EN_CH0_M (AHB_DMA_INDSCR_BURST_EN_CH0_V << AHB_DMA_INDSCR_BURST_EN_CH0_S) -#define AHB_DMA_INDSCR_BURST_EN_CH0_V 0x00000001U -#define AHB_DMA_INDSCR_BURST_EN_CH0_S 2 -/** AHB_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_MEM_TRANS_EN_CH0 (BIT(4)) -#define AHB_DMA_MEM_TRANS_EN_CH0_M (AHB_DMA_MEM_TRANS_EN_CH0_V << AHB_DMA_MEM_TRANS_EN_CH0_S) -#define AHB_DMA_MEM_TRANS_EN_CH0_V 0x00000001U -#define AHB_DMA_MEM_TRANS_EN_CH0_S 4 -/** AHB_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel0. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_IN_ETM_EN_CH0 (BIT(5)) -#define AHB_DMA_IN_ETM_EN_CH0_M (AHB_DMA_IN_ETM_EN_CH0_V << AHB_DMA_IN_ETM_EN_CH0_S) -#define AHB_DMA_IN_ETM_EN_CH0_V 0x00000001U -#define AHB_DMA_IN_ETM_EN_CH0_S 5 -/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S) -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V 0x00000003U -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S 6 - -/** AHB_DMA_IN_CONF1_CH0_REG register - * Configuration register 1 of RX channel 0 - */ -#define AHB_DMA_IN_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x74) -/** AHB_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 0. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_IN_CHECK_OWNER_CH0 (BIT(12)) -#define AHB_DMA_IN_CHECK_OWNER_CH0_M (AHB_DMA_IN_CHECK_OWNER_CH0_V << AHB_DMA_IN_CHECK_OWNER_CH0_S) -#define AHB_DMA_IN_CHECK_OWNER_CH0_V 0x00000001U -#define AHB_DMA_IN_CHECK_OWNER_CH0_S 12 - -/** AHB_DMA_INFIFO_STATUS_CH0_REG register - * Receive FIFO status of RX channel 0 - */ -#define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78) -/** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ -#define AHB_DMA_INFIFO_FULL_CH0 (BIT(0)) -#define AHB_DMA_INFIFO_FULL_CH0_M (AHB_DMA_INFIFO_FULL_CH0_V << AHB_DMA_INFIFO_FULL_CH0_S) -#define AHB_DMA_INFIFO_FULL_CH0_V 0x00000001U -#define AHB_DMA_INFIFO_FULL_CH0_S 0 -/** AHB_DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ -#define AHB_DMA_INFIFO_EMPTY_CH0 (BIT(1)) -#define AHB_DMA_INFIFO_EMPTY_CH0_M (AHB_DMA_INFIFO_EMPTY_CH0_V << AHB_DMA_INFIFO_EMPTY_CH0_S) -#define AHB_DMA_INFIFO_EMPTY_CH0_V 0x00000001U -#define AHB_DMA_INFIFO_EMPTY_CH0_S 1 -/** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 0 - */ -#define AHB_DMA_INFIFO_CNT_CH0 0x0000007FU -#define AHB_DMA_INFIFO_CNT_CH0_M (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S) -#define AHB_DMA_INFIFO_CNT_CH0_V 0x0000007FU -#define AHB_DMA_INFIFO_CNT_CH0_S 8 -/** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S) -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S 23 -/** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S) -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S 24 -/** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S) -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S 25 -/** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S) -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S 26 -/** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; - * reserved - */ -#define AHB_DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) -#define AHB_DMA_IN_BUF_HUNGRY_CH0_M (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S) -#define AHB_DMA_IN_BUF_HUNGRY_CH0_V 0x00000001U -#define AHB_DMA_IN_BUF_HUNGRY_CH0_S 27 - -/** AHB_DMA_IN_POP_CH0_REG register - * Receive FIFO status of RX channel 0 - */ -#define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c) -/** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ -#define AHB_DMA_INFIFO_RDATA_CH0 0x00000FFFU -#define AHB_DMA_INFIFO_RDATA_CH0_M (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S) -#define AHB_DMA_INFIFO_RDATA_CH0_V 0x00000FFFU -#define AHB_DMA_INFIFO_RDATA_CH0_S 0 -/** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ -#define AHB_DMA_INFIFO_POP_CH0 (BIT(12)) -#define AHB_DMA_INFIFO_POP_CH0_M (AHB_DMA_INFIFO_POP_CH0_V << AHB_DMA_INFIFO_POP_CH0_S) -#define AHB_DMA_INFIFO_POP_CH0_V 0x00000001U -#define AHB_DMA_INFIFO_POP_CH0_S 12 - -/** AHB_DMA_IN_LINK_CH0_REG register - * Receive FIFO status of RX channel 0 - */ -#define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80) -/** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ -#define AHB_DMA_INLINK_AUTO_RET_CH0 (BIT(0)) -#define AHB_DMA_INLINK_AUTO_RET_CH0_M (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S) -#define AHB_DMA_INLINK_AUTO_RET_CH0_V 0x00000001U -#define AHB_DMA_INLINK_AUTO_RET_CH0_S 0 -/** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ -#define AHB_DMA_INLINK_STOP_CH0 (BIT(1)) -#define AHB_DMA_INLINK_STOP_CH0_M (AHB_DMA_INLINK_STOP_CH0_V << AHB_DMA_INLINK_STOP_CH0_S) -#define AHB_DMA_INLINK_STOP_CH0_V 0x00000001U -#define AHB_DMA_INLINK_STOP_CH0_S 1 -/** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_INLINK_START_CH0 (BIT(2)) -#define AHB_DMA_INLINK_START_CH0_M (AHB_DMA_INLINK_START_CH0_V << AHB_DMA_INLINK_START_CH0_S) -#define AHB_DMA_INLINK_START_CH0_V 0x00000001U -#define AHB_DMA_INLINK_START_CH0_S 2 -/** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 0 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ -#define AHB_DMA_INLINK_RESTART_CH0 (BIT(3)) -#define AHB_DMA_INLINK_RESTART_CH0_M (AHB_DMA_INLINK_RESTART_CH0_V << AHB_DMA_INLINK_RESTART_CH0_S) -#define AHB_DMA_INLINK_RESTART_CH0_V 0x00000001U -#define AHB_DMA_INLINK_RESTART_CH0_S 3 -/** AHB_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ -#define AHB_DMA_INLINK_PARK_CH0 (BIT(4)) -#define AHB_DMA_INLINK_PARK_CH0_M (AHB_DMA_INLINK_PARK_CH0_V << AHB_DMA_INLINK_PARK_CH0_S) -#define AHB_DMA_INLINK_PARK_CH0_V 0x00000001U -#define AHB_DMA_INLINK_PARK_CH0_S 4 - -/** AHB_DMA_IN_STATE_CH0_REG register - * Receive status of RX channel 0 - */ -#define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84) -/** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * reserved - */ -#define AHB_DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define AHB_DMA_INLINK_DSCR_ADDR_CH0_M (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S) -#define AHB_DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define AHB_DMA_INLINK_DSCR_ADDR_CH0_S 0 -/** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define AHB_DMA_IN_DSCR_STATE_CH0 0x00000003U -#define AHB_DMA_IN_DSCR_STATE_CH0_M (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S) -#define AHB_DMA_IN_DSCR_STATE_CH0_V 0x00000003U -#define AHB_DMA_IN_DSCR_STATE_CH0_S 18 -/** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ -#define AHB_DMA_IN_STATE_CH0 0x00000007U -#define AHB_DMA_IN_STATE_CH0_M (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S) -#define AHB_DMA_IN_STATE_CH0_V 0x00000007U -#define AHB_DMA_IN_STATE_CH0_S 20 - -/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register - * Receive descriptor address when EOF occurs on RX channel 0 - */ -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x88) -/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_M (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S) -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 - -/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register - * Receive descriptor address when errors occur of RX channel 0 - */ -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8c) -/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S) -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 - -/** AHB_DMA_IN_DSCR_CH0_REG register - * Current receive descriptor address of RX channel 0 - */ -#define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x90) -/** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ -#define AHB_DMA_INLINK_DSCR_CH0 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_CH0_M (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S) -#define AHB_DMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_CH0_S 0 - -/** AHB_DMA_IN_DSCR_BF0_CH0_REG register - * The last receive descriptor address of RX channel 0 - */ -#define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x94) -/** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ -#define AHB_DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF0_CH0_M (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S) -#define AHB_DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF0_CH0_S 0 - -/** AHB_DMA_IN_DSCR_BF1_CH0_REG register - * The second-to-last receive descriptor address of RX channel 0 - */ -#define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x98) -/** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ -#define AHB_DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF1_CH0_M (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S) -#define AHB_DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF1_CH0_S 0 - -/** AHB_DMA_IN_PERI_CH0_REG register - * Priority register of RX channel 0 - */ -#define AHB_DMA_IN_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) -/** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 0.The larger of the value, the higher of the - * priority.. - */ -#define AHB_DMA_RX_PRI_CH0 0x0000000FU -#define AHB_DMA_RX_PRI_CH0_M (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S) -#define AHB_DMA_RX_PRI_CH0_V 0x0000000FU -#define AHB_DMA_RX_PRI_CH0_S 0 - -/** AHB_DMA_IN_PERI_SEL_CH0_REG register - * Peripheral selection register of RX channel 0 - */ -#define AHB_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0xa0) -/** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 0. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ -#define AHB_DMA_PERI_IN_SEL_CH0 0x0000003FU -#define AHB_DMA_PERI_IN_SEL_CH0_M (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S) -#define AHB_DMA_PERI_IN_SEL_CH0_V 0x0000003FU -#define AHB_DMA_PERI_IN_SEL_CH0_S 0 - -/** AHB_DMA_OUT_CONF0_CH0_REG register - * Configuration register 0 of TX channel 0 - */ -#define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0) -/** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ -#define AHB_DMA_OUT_RST_CH0 (BIT(0)) -#define AHB_DMA_OUT_RST_CH0_M (AHB_DMA_OUT_RST_CH0_V << AHB_DMA_OUT_RST_CH0_S) -#define AHB_DMA_OUT_RST_CH0_V 0x00000001U -#define AHB_DMA_OUT_RST_CH0_S 0 -/** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_LOOP_TEST_CH0 (BIT(1)) -#define AHB_DMA_OUT_LOOP_TEST_CH0_M (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S) -#define AHB_DMA_OUT_LOOP_TEST_CH0_V 0x00000001U -#define AHB_DMA_OUT_LOOP_TEST_CH0_S 1 -/** AHB_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) -#define AHB_DMA_OUT_AUTO_WRBACK_CH0_M (AHB_DMA_OUT_AUTO_WRBACK_CH0_V << AHB_DMA_OUT_AUTO_WRBACK_CH0_S) -#define AHB_DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U -#define AHB_DMA_OUT_AUTO_WRBACK_CH0_S 2 -/** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ -#define AHB_DMA_OUT_EOF_MODE_CH0 (BIT(3)) -#define AHB_DMA_OUT_EOF_MODE_CH0_M (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S) -#define AHB_DMA_OUT_EOF_MODE_CH0_V 0x00000001U -#define AHB_DMA_OUT_EOF_MODE_CH0_S 3 -/** AHB_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 0 reading - * descriptors. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) -#define AHB_DMA_OUTDSCR_BURST_EN_CH0_M (AHB_DMA_OUTDSCR_BURST_EN_CH0_V << AHB_DMA_OUTDSCR_BURST_EN_CH0_S) -#define AHB_DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U -#define AHB_DMA_OUTDSCR_BURST_EN_CH0_S 4 -/** AHB_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 0. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_ETM_EN_CH0 (BIT(6)) -#define AHB_DMA_OUT_ETM_EN_CH0_M (AHB_DMA_OUT_ETM_EN_CH0_V << AHB_DMA_OUT_ETM_EN_CH0_S) -#define AHB_DMA_OUT_ETM_EN_CH0_V 0x00000001U -#define AHB_DMA_OUT_ETM_EN_CH0_S 6 -/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S) -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V 0x00000003U -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S 8 - -/** AHB_DMA_OUT_CONF1_CH0_REG register - * Configuration register 1 of TX channel 0 - */ -#define AHB_DMA_OUT_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd4) -/** AHB_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 0. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) -#define AHB_DMA_OUT_CHECK_OWNER_CH0_M (AHB_DMA_OUT_CHECK_OWNER_CH0_V << AHB_DMA_OUT_CHECK_OWNER_CH0_S) -#define AHB_DMA_OUT_CHECK_OWNER_CH0_V 0x00000001U -#define AHB_DMA_OUT_CHECK_OWNER_CH0_S 12 - -/** AHB_DMA_OUTFIFO_STATUS_CH0_REG register - * Receive FIFO status of RX channel 0 - */ -#define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8) -/** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ -#define AHB_DMA_OUTFIFO_FULL_CH0 (BIT(0)) -#define AHB_DMA_OUTFIFO_FULL_CH0_M (AHB_DMA_OUTFIFO_FULL_CH0_V << AHB_DMA_OUTFIFO_FULL_CH0_S) -#define AHB_DMA_OUTFIFO_FULL_CH0_V 0x00000001U -#define AHB_DMA_OUTFIFO_FULL_CH0_S 0 -/** AHB_DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ -#define AHB_DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) -#define AHB_DMA_OUTFIFO_EMPTY_CH0_M (AHB_DMA_OUTFIFO_EMPTY_CH0_V << AHB_DMA_OUTFIFO_EMPTY_CH0_S) -#define AHB_DMA_OUTFIFO_EMPTY_CH0_V 0x00000001U -#define AHB_DMA_OUTFIFO_EMPTY_CH0_S 1 -/** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 0 - */ -#define AHB_DMA_OUTFIFO_CNT_CH0 0x0000007FU -#define AHB_DMA_OUTFIFO_CNT_CH0_M (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S) -#define AHB_DMA_OUTFIFO_CNT_CH0_V 0x0000007FU -#define AHB_DMA_OUTFIFO_CNT_CH0_S 8 -/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S) -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 -/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S) -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 -/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S) -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 -/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S) -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S 26 - -/** AHB_DMA_OUT_PUSH_CH0_REG register - * Push control register of TX channel 0 - */ -#define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc) -/** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ -#define AHB_DMA_OUTFIFO_WDATA_CH0 0x000001FFU -#define AHB_DMA_OUTFIFO_WDATA_CH0_M (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S) -#define AHB_DMA_OUTFIFO_WDATA_CH0_V 0x000001FFU -#define AHB_DMA_OUTFIFO_WDATA_CH0_S 0 -/** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ -#define AHB_DMA_OUTFIFO_PUSH_CH0 (BIT(9)) -#define AHB_DMA_OUTFIFO_PUSH_CH0_M (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S) -#define AHB_DMA_OUTFIFO_PUSH_CH0_V 0x00000001U -#define AHB_DMA_OUTFIFO_PUSH_CH0_S 9 - -/** AHB_DMA_OUT_LINK_CH0_REG register - * Push control register of TX channel 0 - */ -#define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0) -/** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ -#define AHB_DMA_OUTLINK_STOP_CH0 (BIT(0)) -#define AHB_DMA_OUTLINK_STOP_CH0_M (AHB_DMA_OUTLINK_STOP_CH0_V << AHB_DMA_OUTLINK_STOP_CH0_S) -#define AHB_DMA_OUTLINK_STOP_CH0_V 0x00000001U -#define AHB_DMA_OUTLINK_STOP_CH0_S 0 -/** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUTLINK_START_CH0 (BIT(1)) -#define AHB_DMA_OUTLINK_START_CH0_M (AHB_DMA_OUTLINK_START_CH0_V << AHB_DMA_OUTLINK_START_CH0_S) -#define AHB_DMA_OUTLINK_START_CH0_V 0x00000001U -#define AHB_DMA_OUTLINK_START_CH0_S 1 -/** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 0 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ -#define AHB_DMA_OUTLINK_RESTART_CH0 (BIT(2)) -#define AHB_DMA_OUTLINK_RESTART_CH0_M (AHB_DMA_OUTLINK_RESTART_CH0_V << AHB_DMA_OUTLINK_RESTART_CH0_S) -#define AHB_DMA_OUTLINK_RESTART_CH0_V 0x00000001U -#define AHB_DMA_OUTLINK_RESTART_CH0_S 2 -/** AHB_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ -#define AHB_DMA_OUTLINK_PARK_CH0 (BIT(3)) -#define AHB_DMA_OUTLINK_PARK_CH0_M (AHB_DMA_OUTLINK_PARK_CH0_V << AHB_DMA_OUTLINK_PARK_CH0_S) -#define AHB_DMA_OUTLINK_PARK_CH0_V 0x00000001U -#define AHB_DMA_OUTLINK_PARK_CH0_S 3 - -/** AHB_DMA_OUT_STATE_CH0_REG register - * Transmit status of TX channel 0 - */ -#define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe4) -/** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S) -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S 0 -/** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_DSCR_STATE_CH0 0x00000003U -#define AHB_DMA_OUT_DSCR_STATE_CH0_M (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S) -#define AHB_DMA_OUT_DSCR_STATE_CH0_V 0x00000003U -#define AHB_DMA_OUT_DSCR_STATE_CH0_S 18 -/** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_STATE_CH0 0x00000007U -#define AHB_DMA_OUT_STATE_CH0_M (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S) -#define AHB_DMA_OUT_STATE_CH0_V 0x00000007U -#define AHB_DMA_OUT_STATE_CH0_S 20 - -/** AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG register - * Transmit descriptor address when EOF occurs on TX channel 0 - */ -#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe8) -/** AHB_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ -#define AHB_DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_M (AHB_DMA_OUT_EOF_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_DES_ADDR_CH0_S) -#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_S 0 - -/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register - * The last transmit descriptor address when EOF occurs on TX channel 0 - */ -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xec) -/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S) -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 - -/** AHB_DMA_OUT_DSCR_CH0_REG register - * Current transmit descriptor address of TX channel 0 - */ -#define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf0) -/** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_CH0_M (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S) -#define AHB_DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_CH0_S 0 - -/** AHB_DMA_OUT_DSCR_BF0_CH0_REG register - * The last transmit descriptor address of TX channel 0 - */ -#define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf4) -/** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S) -#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S 0 - -/** AHB_DMA_OUT_DSCR_BF1_CH0_REG register - * The second-to-last transmit descriptor address of TX channel 0 - */ -#define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf8) -/** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S) -#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_S 0 - -/** AHB_DMA_OUT_PERI_CH0_REG register - * Priority register of TX channel 0 - */ -#define AHB_DMA_OUT_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) -/** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 0.The larger of the value, the higher of the - * priority.. - */ -#define AHB_DMA_TX_PRI_CH0 0x0000000FU -#define AHB_DMA_TX_PRI_CH0_M (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S) -#define AHB_DMA_TX_PRI_CH0_V 0x0000000FU -#define AHB_DMA_TX_PRI_CH0_S 0 - -/** AHB_DMA_OUT_PERI_SEL_CH0_REG register - * Peripheral selection register of TX channel 0 - */ -#define AHB_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x100) -/** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 0. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ -#define AHB_DMA_PERI_OUT_SEL_CH0 0x0000003FU -#define AHB_DMA_PERI_OUT_SEL_CH0_M (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S) -#define AHB_DMA_PERI_OUT_SEL_CH0_V 0x0000003FU -#define AHB_DMA_PERI_OUT_SEL_CH0_S 0 - -/** AHB_DMA_IN_CONF0_CH1_REG register - * Configuration register 0 of RX channel 1 - */ -#define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130) -/** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. - */ -#define AHB_DMA_IN_RST_CH1 (BIT(0)) -#define AHB_DMA_IN_RST_CH1_M (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S) -#define AHB_DMA_IN_RST_CH1_V 0x00000001U -#define AHB_DMA_IN_RST_CH1_S 0 -/** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define AHB_DMA_IN_LOOP_TEST_CH1 (BIT(1)) -#define AHB_DMA_IN_LOOP_TEST_CH1_M (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S) -#define AHB_DMA_IN_LOOP_TEST_CH1_V 0x00000001U -#define AHB_DMA_IN_LOOP_TEST_CH1_S 1 -/** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 1 to read - * descriptors. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_INDSCR_BURST_EN_CH1 (BIT(2)) -#define AHB_DMA_INDSCR_BURST_EN_CH1_M (AHB_DMA_INDSCR_BURST_EN_CH1_V << AHB_DMA_INDSCR_BURST_EN_CH1_S) -#define AHB_DMA_INDSCR_BURST_EN_CH1_V 0x00000001U -#define AHB_DMA_INDSCR_BURST_EN_CH1_S 2 -/** AHB_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_MEM_TRANS_EN_CH1 (BIT(4)) -#define AHB_DMA_MEM_TRANS_EN_CH1_M (AHB_DMA_MEM_TRANS_EN_CH1_V << AHB_DMA_MEM_TRANS_EN_CH1_S) -#define AHB_DMA_MEM_TRANS_EN_CH1_V 0x00000001U -#define AHB_DMA_MEM_TRANS_EN_CH1_S 4 -/** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel1. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_IN_ETM_EN_CH1 (BIT(5)) -#define AHB_DMA_IN_ETM_EN_CH1_M (AHB_DMA_IN_ETM_EN_CH1_V << AHB_DMA_IN_ETM_EN_CH1_S) -#define AHB_DMA_IN_ETM_EN_CH1_V 0x00000001U -#define AHB_DMA_IN_ETM_EN_CH1_S 5 -/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S) -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V 0x00000003U -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S 6 - -/** AHB_DMA_IN_CONF1_CH1_REG register - * Configuration register 1 of RX channel 1 - */ -#define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x134) -/** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 1. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_IN_CHECK_OWNER_CH1 (BIT(12)) -#define AHB_DMA_IN_CHECK_OWNER_CH1_M (AHB_DMA_IN_CHECK_OWNER_CH1_V << AHB_DMA_IN_CHECK_OWNER_CH1_S) -#define AHB_DMA_IN_CHECK_OWNER_CH1_V 0x00000001U -#define AHB_DMA_IN_CHECK_OWNER_CH1_S 12 - -/** AHB_DMA_INFIFO_STATUS_CH1_REG register - * Receive FIFO status of RX channel 1 - */ -#define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138) -/** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ -#define AHB_DMA_INFIFO_FULL_CH1 (BIT(0)) -#define AHB_DMA_INFIFO_FULL_CH1_M (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S) -#define AHB_DMA_INFIFO_FULL_CH1_V 0x00000001U -#define AHB_DMA_INFIFO_FULL_CH1_S 0 -/** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ -#define AHB_DMA_INFIFO_EMPTY_CH1 (BIT(1)) -#define AHB_DMA_INFIFO_EMPTY_CH1_M (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S) -#define AHB_DMA_INFIFO_EMPTY_CH1_V 0x00000001U -#define AHB_DMA_INFIFO_EMPTY_CH1_S 1 -/** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 1 - */ -#define AHB_DMA_INFIFO_CNT_CH1 0x0000007FU -#define AHB_DMA_INFIFO_CNT_CH1_M (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S) -#define AHB_DMA_INFIFO_CNT_CH1_V 0x0000007FU -#define AHB_DMA_INFIFO_CNT_CH1_S 8 -/** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S) -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S 23 -/** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S) -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S 24 -/** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S) -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S 25 -/** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S) -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S 26 -/** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; - * reserved - */ -#define AHB_DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) -#define AHB_DMA_IN_BUF_HUNGRY_CH1_M (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S) -#define AHB_DMA_IN_BUF_HUNGRY_CH1_V 0x00000001U -#define AHB_DMA_IN_BUF_HUNGRY_CH1_S 27 - -/** AHB_DMA_IN_POP_CH1_REG register - * Receive FIFO status of RX channel 1 - */ -#define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c) -/** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ -#define AHB_DMA_INFIFO_RDATA_CH1 0x00000FFFU -#define AHB_DMA_INFIFO_RDATA_CH1_M (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S) -#define AHB_DMA_INFIFO_RDATA_CH1_V 0x00000FFFU -#define AHB_DMA_INFIFO_RDATA_CH1_S 0 -/** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ -#define AHB_DMA_INFIFO_POP_CH1 (BIT(12)) -#define AHB_DMA_INFIFO_POP_CH1_M (AHB_DMA_INFIFO_POP_CH1_V << AHB_DMA_INFIFO_POP_CH1_S) -#define AHB_DMA_INFIFO_POP_CH1_V 0x00000001U -#define AHB_DMA_INFIFO_POP_CH1_S 12 - -/** AHB_DMA_IN_LINK_CH1_REG register - * Receive FIFO status of RX channel 1 - */ -#define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140) -/** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ -#define AHB_DMA_INLINK_AUTO_RET_CH1 (BIT(0)) -#define AHB_DMA_INLINK_AUTO_RET_CH1_M (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S) -#define AHB_DMA_INLINK_AUTO_RET_CH1_V 0x00000001U -#define AHB_DMA_INLINK_AUTO_RET_CH1_S 0 -/** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ -#define AHB_DMA_INLINK_STOP_CH1 (BIT(1)) -#define AHB_DMA_INLINK_STOP_CH1_M (AHB_DMA_INLINK_STOP_CH1_V << AHB_DMA_INLINK_STOP_CH1_S) -#define AHB_DMA_INLINK_STOP_CH1_V 0x00000001U -#define AHB_DMA_INLINK_STOP_CH1_S 1 -/** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_INLINK_START_CH1 (BIT(2)) -#define AHB_DMA_INLINK_START_CH1_M (AHB_DMA_INLINK_START_CH1_V << AHB_DMA_INLINK_START_CH1_S) -#define AHB_DMA_INLINK_START_CH1_V 0x00000001U -#define AHB_DMA_INLINK_START_CH1_S 2 -/** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 1 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ -#define AHB_DMA_INLINK_RESTART_CH1 (BIT(3)) -#define AHB_DMA_INLINK_RESTART_CH1_M (AHB_DMA_INLINK_RESTART_CH1_V << AHB_DMA_INLINK_RESTART_CH1_S) -#define AHB_DMA_INLINK_RESTART_CH1_V 0x00000001U -#define AHB_DMA_INLINK_RESTART_CH1_S 3 -/** AHB_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ -#define AHB_DMA_INLINK_PARK_CH1 (BIT(4)) -#define AHB_DMA_INLINK_PARK_CH1_M (AHB_DMA_INLINK_PARK_CH1_V << AHB_DMA_INLINK_PARK_CH1_S) -#define AHB_DMA_INLINK_PARK_CH1_V 0x00000001U -#define AHB_DMA_INLINK_PARK_CH1_S 4 - -/** AHB_DMA_IN_STATE_CH1_REG register - * Receive status of RX channel 1 - */ -#define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144) -/** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * reserved - */ -#define AHB_DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define AHB_DMA_INLINK_DSCR_ADDR_CH1_M (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S) -#define AHB_DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define AHB_DMA_INLINK_DSCR_ADDR_CH1_S 0 -/** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define AHB_DMA_IN_DSCR_STATE_CH1 0x00000003U -#define AHB_DMA_IN_DSCR_STATE_CH1_M (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S) -#define AHB_DMA_IN_DSCR_STATE_CH1_V 0x00000003U -#define AHB_DMA_IN_DSCR_STATE_CH1_S 18 -/** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ -#define AHB_DMA_IN_STATE_CH1 0x00000007U -#define AHB_DMA_IN_STATE_CH1_M (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S) -#define AHB_DMA_IN_STATE_CH1_V 0x00000007U -#define AHB_DMA_IN_STATE_CH1_S 20 - -/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Receive descriptor address when EOF occurs on RX channel 1 - */ -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x148) -/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_M (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S) -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 - -/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Receive descriptor address when errors occur of RX channel 1 - */ -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c) -/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S) -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 - -/** AHB_DMA_IN_DSCR_CH1_REG register - * Current receive descriptor address of RX channel 1 - */ -#define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150) -/** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ -#define AHB_DMA_INLINK_DSCR_CH1 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_CH1_M (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S) -#define AHB_DMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_CH1_S 0 - -/** AHB_DMA_IN_DSCR_BF0_CH1_REG register - * The last receive descriptor address of RX channel 1 - */ -#define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154) -/** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ -#define AHB_DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF0_CH1_M (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S) -#define AHB_DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF0_CH1_S 0 - -/** AHB_DMA_IN_DSCR_BF1_CH1_REG register - * The second-to-last receive descriptor address of RX channel 1 - */ -#define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158) -/** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ -#define AHB_DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF1_CH1_M (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S) -#define AHB_DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF1_CH1_S 0 - -/** AHB_DMA_IN_PERI_CH1_REG register - * Priority register of RX channel 1 - */ -#define AHB_DMA_IN_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) -/** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 1.The larger of the value, the higher of the - * priority.. - */ -#define AHB_DMA_RX_PRI_CH1 0x0000000FU -#define AHB_DMA_RX_PRI_CH1_M (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S) -#define AHB_DMA_RX_PRI_CH1_V 0x0000000FU -#define AHB_DMA_RX_PRI_CH1_S 0 - -/** AHB_DMA_IN_PERI_SEL_CH1_REG register - * Peripheral selection register of RX channel 1 - */ -#define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x160) -/** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 1. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ -#define AHB_DMA_PERI_IN_SEL_CH1 0x0000003FU -#define AHB_DMA_PERI_IN_SEL_CH1_M (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S) -#define AHB_DMA_PERI_IN_SEL_CH1_V 0x0000003FU -#define AHB_DMA_PERI_IN_SEL_CH1_S 0 - -/** AHB_DMA_OUT_CONF0_CH1_REG register - * Configuration register 0 of TX channel 1 - */ -#define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190) -/** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ -#define AHB_DMA_OUT_RST_CH1 (BIT(0)) -#define AHB_DMA_OUT_RST_CH1_M (AHB_DMA_OUT_RST_CH1_V << AHB_DMA_OUT_RST_CH1_S) -#define AHB_DMA_OUT_RST_CH1_V 0x00000001U -#define AHB_DMA_OUT_RST_CH1_S 0 -/** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_LOOP_TEST_CH1 (BIT(1)) -#define AHB_DMA_OUT_LOOP_TEST_CH1_M (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S) -#define AHB_DMA_OUT_LOOP_TEST_CH1_V 0x00000001U -#define AHB_DMA_OUT_LOOP_TEST_CH1_S 1 -/** AHB_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) -#define AHB_DMA_OUT_AUTO_WRBACK_CH1_M (AHB_DMA_OUT_AUTO_WRBACK_CH1_V << AHB_DMA_OUT_AUTO_WRBACK_CH1_S) -#define AHB_DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U -#define AHB_DMA_OUT_AUTO_WRBACK_CH1_S 2 -/** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ -#define AHB_DMA_OUT_EOF_MODE_CH1 (BIT(3)) -#define AHB_DMA_OUT_EOF_MODE_CH1_M (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S) -#define AHB_DMA_OUT_EOF_MODE_CH1_V 0x00000001U -#define AHB_DMA_OUT_EOF_MODE_CH1_S 3 -/** AHB_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 1 reading - * descriptors. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) -#define AHB_DMA_OUTDSCR_BURST_EN_CH1_M (AHB_DMA_OUTDSCR_BURST_EN_CH1_V << AHB_DMA_OUTDSCR_BURST_EN_CH1_S) -#define AHB_DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U -#define AHB_DMA_OUTDSCR_BURST_EN_CH1_S 4 -/** AHB_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 1. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_ETM_EN_CH1 (BIT(6)) -#define AHB_DMA_OUT_ETM_EN_CH1_M (AHB_DMA_OUT_ETM_EN_CH1_V << AHB_DMA_OUT_ETM_EN_CH1_S) -#define AHB_DMA_OUT_ETM_EN_CH1_V 0x00000001U -#define AHB_DMA_OUT_ETM_EN_CH1_S 6 -/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S) -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V 0x00000003U -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S 8 - -/** AHB_DMA_OUT_CONF1_CH1_REG register - * Configuration register 1 of TX channel 1 - */ -#define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x194) -/** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 1. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) -#define AHB_DMA_OUT_CHECK_OWNER_CH1_M (AHB_DMA_OUT_CHECK_OWNER_CH1_V << AHB_DMA_OUT_CHECK_OWNER_CH1_S) -#define AHB_DMA_OUT_CHECK_OWNER_CH1_V 0x00000001U -#define AHB_DMA_OUT_CHECK_OWNER_CH1_S 12 - -/** AHB_DMA_OUTFIFO_STATUS_CH1_REG register - * Receive FIFO status of RX channel 1 - */ -#define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198) -/** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ -#define AHB_DMA_OUTFIFO_FULL_CH1 (BIT(0)) -#define AHB_DMA_OUTFIFO_FULL_CH1_M (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S) -#define AHB_DMA_OUTFIFO_FULL_CH1_V 0x00000001U -#define AHB_DMA_OUTFIFO_FULL_CH1_S 0 -/** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ -#define AHB_DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) -#define AHB_DMA_OUTFIFO_EMPTY_CH1_M (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S) -#define AHB_DMA_OUTFIFO_EMPTY_CH1_V 0x00000001U -#define AHB_DMA_OUTFIFO_EMPTY_CH1_S 1 -/** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 1 - */ -#define AHB_DMA_OUTFIFO_CNT_CH1 0x0000007FU -#define AHB_DMA_OUTFIFO_CNT_CH1_M (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S) -#define AHB_DMA_OUTFIFO_CNT_CH1_V 0x0000007FU -#define AHB_DMA_OUTFIFO_CNT_CH1_S 8 -/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S) -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 -/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S) -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 -/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S) -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 -/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S) -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 - -/** AHB_DMA_OUT_PUSH_CH1_REG register - * Push control register of TX channel 1 - */ -#define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c) -/** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ -#define AHB_DMA_OUTFIFO_WDATA_CH1 0x000001FFU -#define AHB_DMA_OUTFIFO_WDATA_CH1_M (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S) -#define AHB_DMA_OUTFIFO_WDATA_CH1_V 0x000001FFU -#define AHB_DMA_OUTFIFO_WDATA_CH1_S 0 -/** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ -#define AHB_DMA_OUTFIFO_PUSH_CH1 (BIT(9)) -#define AHB_DMA_OUTFIFO_PUSH_CH1_M (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S) -#define AHB_DMA_OUTFIFO_PUSH_CH1_V 0x00000001U -#define AHB_DMA_OUTFIFO_PUSH_CH1_S 9 - -/** AHB_DMA_OUT_LINK_CH1_REG register - * Push control register of TX channel 1 - */ -#define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0) -/** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ -#define AHB_DMA_OUTLINK_STOP_CH1 (BIT(0)) -#define AHB_DMA_OUTLINK_STOP_CH1_M (AHB_DMA_OUTLINK_STOP_CH1_V << AHB_DMA_OUTLINK_STOP_CH1_S) -#define AHB_DMA_OUTLINK_STOP_CH1_V 0x00000001U -#define AHB_DMA_OUTLINK_STOP_CH1_S 0 -/** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUTLINK_START_CH1 (BIT(1)) -#define AHB_DMA_OUTLINK_START_CH1_M (AHB_DMA_OUTLINK_START_CH1_V << AHB_DMA_OUTLINK_START_CH1_S) -#define AHB_DMA_OUTLINK_START_CH1_V 0x00000001U -#define AHB_DMA_OUTLINK_START_CH1_S 1 -/** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 1 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ -#define AHB_DMA_OUTLINK_RESTART_CH1 (BIT(2)) -#define AHB_DMA_OUTLINK_RESTART_CH1_M (AHB_DMA_OUTLINK_RESTART_CH1_V << AHB_DMA_OUTLINK_RESTART_CH1_S) -#define AHB_DMA_OUTLINK_RESTART_CH1_V 0x00000001U -#define AHB_DMA_OUTLINK_RESTART_CH1_S 2 -/** AHB_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ -#define AHB_DMA_OUTLINK_PARK_CH1 (BIT(3)) -#define AHB_DMA_OUTLINK_PARK_CH1_M (AHB_DMA_OUTLINK_PARK_CH1_V << AHB_DMA_OUTLINK_PARK_CH1_S) -#define AHB_DMA_OUTLINK_PARK_CH1_V 0x00000001U -#define AHB_DMA_OUTLINK_PARK_CH1_S 3 - -/** AHB_DMA_OUT_STATE_CH1_REG register - * Transmit status of TX channel 1 - */ -#define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4) -/** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S) -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S 0 -/** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_DSCR_STATE_CH1 0x00000003U -#define AHB_DMA_OUT_DSCR_STATE_CH1_M (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S) -#define AHB_DMA_OUT_DSCR_STATE_CH1_V 0x00000003U -#define AHB_DMA_OUT_DSCR_STATE_CH1_S 18 -/** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_STATE_CH1 0x00000007U -#define AHB_DMA_OUT_STATE_CH1_M (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S) -#define AHB_DMA_OUT_STATE_CH1_V 0x00000007U -#define AHB_DMA_OUT_STATE_CH1_S 20 - -/** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register - * Transmit descriptor address when EOF occurs on TX channel 1 - */ -#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a8) -/** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ -#define AHB_DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_M (AHB_DMA_OUT_EOF_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_DES_ADDR_CH1_S) -#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S 0 - -/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register - * The last transmit descriptor address when EOF occurs on TX channel 1 - */ -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1ac) -/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S) -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 - -/** AHB_DMA_OUT_DSCR_CH1_REG register - * Current transmit descriptor address of TX channel 1 - */ -#define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0) -/** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_CH1_M (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S) -#define AHB_DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_CH1_S 0 - -/** AHB_DMA_OUT_DSCR_BF0_CH1_REG register - * The last transmit descriptor address of TX channel 1 - */ -#define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4) -/** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S) -#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S 0 - -/** AHB_DMA_OUT_DSCR_BF1_CH1_REG register - * The second-to-last transmit descriptor address of TX channel 1 - */ -#define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8) -/** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S) -#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S 0 - -/** AHB_DMA_OUT_PERI_CH1_REG register - * Priority register of TX channel 1 - */ -#define AHB_DMA_OUT_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) -/** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 1.The larger of the value, the higher of the - * priority.. - */ -#define AHB_DMA_TX_PRI_CH1 0x0000000FU -#define AHB_DMA_TX_PRI_CH1_M (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S) -#define AHB_DMA_TX_PRI_CH1_V 0x0000000FU -#define AHB_DMA_TX_PRI_CH1_S 0 - -/** AHB_DMA_OUT_PERI_SEL_CH1_REG register - * Peripheral selection register of TX channel 1 - */ -#define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c0) -/** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 1. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ -#define AHB_DMA_PERI_OUT_SEL_CH1 0x0000003FU -#define AHB_DMA_PERI_OUT_SEL_CH1_M (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S) -#define AHB_DMA_PERI_OUT_SEL_CH1_V 0x0000003FU -#define AHB_DMA_PERI_OUT_SEL_CH1_S 0 - -/** AHB_DMA_IN_CONF0_CH2_REG register - * Configuration register 0 of RX channel 2 - */ -#define AHB_DMA_IN_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f0) -/** AHB_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer. - */ -#define AHB_DMA_IN_RST_CH2 (BIT(0)) -#define AHB_DMA_IN_RST_CH2_M (AHB_DMA_IN_RST_CH2_V << AHB_DMA_IN_RST_CH2_S) -#define AHB_DMA_IN_RST_CH2_V 0x00000001U -#define AHB_DMA_IN_RST_CH2_S 0 -/** AHB_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define AHB_DMA_IN_LOOP_TEST_CH2 (BIT(1)) -#define AHB_DMA_IN_LOOP_TEST_CH2_M (AHB_DMA_IN_LOOP_TEST_CH2_V << AHB_DMA_IN_LOOP_TEST_CH2_S) -#define AHB_DMA_IN_LOOP_TEST_CH2_V 0x00000001U -#define AHB_DMA_IN_LOOP_TEST_CH2_S 1 -/** AHB_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 2 to read - * descriptors. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_INDSCR_BURST_EN_CH2 (BIT(2)) -#define AHB_DMA_INDSCR_BURST_EN_CH2_M (AHB_DMA_INDSCR_BURST_EN_CH2_V << AHB_DMA_INDSCR_BURST_EN_CH2_S) -#define AHB_DMA_INDSCR_BURST_EN_CH2_V 0x00000001U -#define AHB_DMA_INDSCR_BURST_EN_CH2_S 2 -/** AHB_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_MEM_TRANS_EN_CH2 (BIT(4)) -#define AHB_DMA_MEM_TRANS_EN_CH2_M (AHB_DMA_MEM_TRANS_EN_CH2_V << AHB_DMA_MEM_TRANS_EN_CH2_S) -#define AHB_DMA_MEM_TRANS_EN_CH2_V 0x00000001U -#define AHB_DMA_MEM_TRANS_EN_CH2_S 4 -/** AHB_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel2. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_IN_ETM_EN_CH2 (BIT(5)) -#define AHB_DMA_IN_ETM_EN_CH2_M (AHB_DMA_IN_ETM_EN_CH2_V << AHB_DMA_IN_ETM_EN_CH2_S) -#define AHB_DMA_IN_ETM_EN_CH2_V 0x00000001U -#define AHB_DMA_IN_ETM_EN_CH2_S 5 -/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel2. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 0x00000003U -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S) -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V 0x00000003U -#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S 6 - -/** AHB_DMA_IN_CONF1_CH2_REG register - * Configuration register 1 of RX channel 2 - */ -#define AHB_DMA_IN_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f4) -/** AHB_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 2. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_IN_CHECK_OWNER_CH2 (BIT(12)) -#define AHB_DMA_IN_CHECK_OWNER_CH2_M (AHB_DMA_IN_CHECK_OWNER_CH2_V << AHB_DMA_IN_CHECK_OWNER_CH2_S) -#define AHB_DMA_IN_CHECK_OWNER_CH2_V 0x00000001U -#define AHB_DMA_IN_CHECK_OWNER_CH2_S 12 - -/** AHB_DMA_INFIFO_STATUS_CH2_REG register - * Receive FIFO status of RX channel 2 - */ -#define AHB_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f8) -/** AHB_DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ -#define AHB_DMA_INFIFO_FULL_CH2 (BIT(0)) -#define AHB_DMA_INFIFO_FULL_CH2_M (AHB_DMA_INFIFO_FULL_CH2_V << AHB_DMA_INFIFO_FULL_CH2_S) -#define AHB_DMA_INFIFO_FULL_CH2_V 0x00000001U -#define AHB_DMA_INFIFO_FULL_CH2_S 0 -/** AHB_DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ -#define AHB_DMA_INFIFO_EMPTY_CH2 (BIT(1)) -#define AHB_DMA_INFIFO_EMPTY_CH2_M (AHB_DMA_INFIFO_EMPTY_CH2_V << AHB_DMA_INFIFO_EMPTY_CH2_S) -#define AHB_DMA_INFIFO_EMPTY_CH2_V 0x00000001U -#define AHB_DMA_INFIFO_EMPTY_CH2_S 1 -/** AHB_DMA_INFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 2 - */ -#define AHB_DMA_INFIFO_CNT_CH2 0x0000007FU -#define AHB_DMA_INFIFO_CNT_CH2_M (AHB_DMA_INFIFO_CNT_CH2_V << AHB_DMA_INFIFO_CNT_CH2_S) -#define AHB_DMA_INFIFO_CNT_CH2_V 0x0000007FU -#define AHB_DMA_INFIFO_CNT_CH2_S 8 -/** AHB_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S) -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S 23 -/** AHB_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S) -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S 24 -/** AHB_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S) -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S 25 -/** AHB_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; - * reserved - */ -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S) -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S 26 -/** AHB_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; - * reserved - */ -#define AHB_DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) -#define AHB_DMA_IN_BUF_HUNGRY_CH2_M (AHB_DMA_IN_BUF_HUNGRY_CH2_V << AHB_DMA_IN_BUF_HUNGRY_CH2_S) -#define AHB_DMA_IN_BUF_HUNGRY_CH2_V 0x00000001U -#define AHB_DMA_IN_BUF_HUNGRY_CH2_S 27 - -/** AHB_DMA_IN_POP_CH2_REG register - * Receive FIFO status of RX channel 2 - */ -#define AHB_DMA_IN_POP_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1fc) -/** AHB_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ -#define AHB_DMA_INFIFO_RDATA_CH2 0x00000FFFU -#define AHB_DMA_INFIFO_RDATA_CH2_M (AHB_DMA_INFIFO_RDATA_CH2_V << AHB_DMA_INFIFO_RDATA_CH2_S) -#define AHB_DMA_INFIFO_RDATA_CH2_V 0x00000FFFU -#define AHB_DMA_INFIFO_RDATA_CH2_S 0 -/** AHB_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ -#define AHB_DMA_INFIFO_POP_CH2 (BIT(12)) -#define AHB_DMA_INFIFO_POP_CH2_M (AHB_DMA_INFIFO_POP_CH2_V << AHB_DMA_INFIFO_POP_CH2_S) -#define AHB_DMA_INFIFO_POP_CH2_V 0x00000001U -#define AHB_DMA_INFIFO_POP_CH2_S 12 - -/** AHB_DMA_IN_LINK_CH2_REG register - * Receive FIFO status of RX channel 2 - */ -#define AHB_DMA_IN_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x200) -/** AHB_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ -#define AHB_DMA_INLINK_AUTO_RET_CH2 (BIT(0)) -#define AHB_DMA_INLINK_AUTO_RET_CH2_M (AHB_DMA_INLINK_AUTO_RET_CH2_V << AHB_DMA_INLINK_AUTO_RET_CH2_S) -#define AHB_DMA_INLINK_AUTO_RET_CH2_V 0x00000001U -#define AHB_DMA_INLINK_AUTO_RET_CH2_S 0 -/** AHB_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 2 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ -#define AHB_DMA_INLINK_STOP_CH2 (BIT(1)) -#define AHB_DMA_INLINK_STOP_CH2_M (AHB_DMA_INLINK_STOP_CH2_V << AHB_DMA_INLINK_STOP_CH2_S) -#define AHB_DMA_INLINK_STOP_CH2_V 0x00000001U -#define AHB_DMA_INLINK_STOP_CH2_S 1 -/** AHB_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 2 for data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_INLINK_START_CH2 (BIT(2)) -#define AHB_DMA_INLINK_START_CH2_M (AHB_DMA_INLINK_START_CH2_V << AHB_DMA_INLINK_START_CH2_S) -#define AHB_DMA_INLINK_START_CH2_V 0x00000001U -#define AHB_DMA_INLINK_START_CH2_S 2 -/** AHB_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 2 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ -#define AHB_DMA_INLINK_RESTART_CH2 (BIT(3)) -#define AHB_DMA_INLINK_RESTART_CH2_M (AHB_DMA_INLINK_RESTART_CH2_V << AHB_DMA_INLINK_RESTART_CH2_S) -#define AHB_DMA_INLINK_RESTART_CH2_V 0x00000001U -#define AHB_DMA_INLINK_RESTART_CH2_S 3 -/** AHB_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ -#define AHB_DMA_INLINK_PARK_CH2 (BIT(4)) -#define AHB_DMA_INLINK_PARK_CH2_M (AHB_DMA_INLINK_PARK_CH2_V << AHB_DMA_INLINK_PARK_CH2_S) -#define AHB_DMA_INLINK_PARK_CH2_V 0x00000001U -#define AHB_DMA_INLINK_PARK_CH2_S 4 - -/** AHB_DMA_IN_STATE_CH2_REG register - * Receive status of RX channel 2 - */ -#define AHB_DMA_IN_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x204) -/** AHB_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * reserved - */ -#define AHB_DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define AHB_DMA_INLINK_DSCR_ADDR_CH2_M (AHB_DMA_INLINK_DSCR_ADDR_CH2_V << AHB_DMA_INLINK_DSCR_ADDR_CH2_S) -#define AHB_DMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define AHB_DMA_INLINK_DSCR_ADDR_CH2_S 0 -/** AHB_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define AHB_DMA_IN_DSCR_STATE_CH2 0x00000003U -#define AHB_DMA_IN_DSCR_STATE_CH2_M (AHB_DMA_IN_DSCR_STATE_CH2_V << AHB_DMA_IN_DSCR_STATE_CH2_S) -#define AHB_DMA_IN_DSCR_STATE_CH2_V 0x00000003U -#define AHB_DMA_IN_DSCR_STATE_CH2_S 18 -/** AHB_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ -#define AHB_DMA_IN_STATE_CH2 0x00000007U -#define AHB_DMA_IN_STATE_CH2_M (AHB_DMA_IN_STATE_CH2_V << AHB_DMA_IN_STATE_CH2_S) -#define AHB_DMA_IN_STATE_CH2_V 0x00000007U -#define AHB_DMA_IN_STATE_CH2_S 20 - -/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register - * Receive descriptor address when EOF occurs on RX channel 2 - */ -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x208) -/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_M (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S) -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 - -/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register - * Receive descriptor address when errors occur of RX channel 2 - */ -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20c) -/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S) -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 - -/** AHB_DMA_IN_DSCR_CH2_REG register - * Current receive descriptor address of RX channel 2 - */ -#define AHB_DMA_IN_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x210) -/** AHB_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ -#define AHB_DMA_INLINK_DSCR_CH2 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_CH2_M (AHB_DMA_INLINK_DSCR_CH2_V << AHB_DMA_INLINK_DSCR_CH2_S) -#define AHB_DMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_CH2_S 0 - -/** AHB_DMA_IN_DSCR_BF0_CH2_REG register - * The last receive descriptor address of RX channel 2 - */ -#define AHB_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x214) -/** AHB_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ -#define AHB_DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF0_CH2_M (AHB_DMA_INLINK_DSCR_BF0_CH2_V << AHB_DMA_INLINK_DSCR_BF0_CH2_S) -#define AHB_DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF0_CH2_S 0 - -/** AHB_DMA_IN_DSCR_BF1_CH2_REG register - * The second-to-last receive descriptor address of RX channel 2 - */ -#define AHB_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x218) -/** AHB_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ -#define AHB_DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF1_CH2_M (AHB_DMA_INLINK_DSCR_BF1_CH2_V << AHB_DMA_INLINK_DSCR_BF1_CH2_S) -#define AHB_DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_DSCR_BF1_CH2_S 0 - -/** AHB_DMA_IN_PERI_CH2_REG register - * Priority register of RX channel 2 - */ -#define AHB_DMA_IN_PERI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x21c) -/** AHB_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 2.The larger of the value, the higher of the - * priority.. - */ -#define AHB_DMA_RX_PRI_CH2 0x0000000FU -#define AHB_DMA_RX_PRI_CH2_M (AHB_DMA_RX_PRI_CH2_V << AHB_DMA_RX_PRI_CH2_S) -#define AHB_DMA_RX_PRI_CH2_V 0x0000000FU -#define AHB_DMA_RX_PRI_CH2_S 0 - -/** AHB_DMA_IN_PERI_SEL_CH2_REG register - * Peripheral selection register of RX channel 2 - */ -#define AHB_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x220) -/** AHB_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 2. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ -#define AHB_DMA_PERI_IN_SEL_CH2 0x0000003FU -#define AHB_DMA_PERI_IN_SEL_CH2_M (AHB_DMA_PERI_IN_SEL_CH2_V << AHB_DMA_PERI_IN_SEL_CH2_S) -#define AHB_DMA_PERI_IN_SEL_CH2_V 0x0000003FU -#define AHB_DMA_PERI_IN_SEL_CH2_S 0 - -/** AHB_DMA_OUT_CONF0_CH2_REG register - * Configuration register 0 of TX channel 2 - */ -#define AHB_DMA_OUT_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x250) -/** AHB_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ -#define AHB_DMA_OUT_RST_CH2 (BIT(0)) -#define AHB_DMA_OUT_RST_CH2_M (AHB_DMA_OUT_RST_CH2_V << AHB_DMA_OUT_RST_CH2_S) -#define AHB_DMA_OUT_RST_CH2_V 0x00000001U -#define AHB_DMA_OUT_RST_CH2_S 0 -/** AHB_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_LOOP_TEST_CH2 (BIT(1)) -#define AHB_DMA_OUT_LOOP_TEST_CH2_M (AHB_DMA_OUT_LOOP_TEST_CH2_V << AHB_DMA_OUT_LOOP_TEST_CH2_S) -#define AHB_DMA_OUT_LOOP_TEST_CH2_V 0x00000001U -#define AHB_DMA_OUT_LOOP_TEST_CH2_S 1 -/** AHB_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) -#define AHB_DMA_OUT_AUTO_WRBACK_CH2_M (AHB_DMA_OUT_AUTO_WRBACK_CH2_V << AHB_DMA_OUT_AUTO_WRBACK_CH2_S) -#define AHB_DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U -#define AHB_DMA_OUT_AUTO_WRBACK_CH2_S 2 -/** AHB_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 2 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 2 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ -#define AHB_DMA_OUT_EOF_MODE_CH2 (BIT(3)) -#define AHB_DMA_OUT_EOF_MODE_CH2_M (AHB_DMA_OUT_EOF_MODE_CH2_V << AHB_DMA_OUT_EOF_MODE_CH2_S) -#define AHB_DMA_OUT_EOF_MODE_CH2_V 0x00000001U -#define AHB_DMA_OUT_EOF_MODE_CH2_S 3 -/** AHB_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 2 reading - * descriptors. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) -#define AHB_DMA_OUTDSCR_BURST_EN_CH2_M (AHB_DMA_OUTDSCR_BURST_EN_CH2_V << AHB_DMA_OUTDSCR_BURST_EN_CH2_S) -#define AHB_DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U -#define AHB_DMA_OUTDSCR_BURST_EN_CH2_S 4 -/** AHB_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 2. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_ETM_EN_CH2 (BIT(6)) -#define AHB_DMA_OUT_ETM_EN_CH2_M (AHB_DMA_OUT_ETM_EN_CH2_V << AHB_DMA_OUT_ETM_EN_CH2_S) -#define AHB_DMA_OUT_ETM_EN_CH2_V 0x00000001U -#define AHB_DMA_OUT_ETM_EN_CH2_S 6 -/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel2. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 0x00000003U -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S) -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V 0x00000003U -#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S 8 - -/** AHB_DMA_OUT_CONF1_CH2_REG register - * Configuration register 1 of TX channel 2 - */ -#define AHB_DMA_OUT_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x254) -/** AHB_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 2. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) -#define AHB_DMA_OUT_CHECK_OWNER_CH2_M (AHB_DMA_OUT_CHECK_OWNER_CH2_V << AHB_DMA_OUT_CHECK_OWNER_CH2_S) -#define AHB_DMA_OUT_CHECK_OWNER_CH2_V 0x00000001U -#define AHB_DMA_OUT_CHECK_OWNER_CH2_S 12 - -/** AHB_DMA_OUTFIFO_STATUS_CH2_REG register - * Receive FIFO status of RX channel 2 - */ -#define AHB_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x258) -/** AHB_DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ -#define AHB_DMA_OUTFIFO_FULL_CH2 (BIT(0)) -#define AHB_DMA_OUTFIFO_FULL_CH2_M (AHB_DMA_OUTFIFO_FULL_CH2_V << AHB_DMA_OUTFIFO_FULL_CH2_S) -#define AHB_DMA_OUTFIFO_FULL_CH2_V 0x00000001U -#define AHB_DMA_OUTFIFO_FULL_CH2_S 0 -/** AHB_DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ -#define AHB_DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) -#define AHB_DMA_OUTFIFO_EMPTY_CH2_M (AHB_DMA_OUTFIFO_EMPTY_CH2_V << AHB_DMA_OUTFIFO_EMPTY_CH2_S) -#define AHB_DMA_OUTFIFO_EMPTY_CH2_V 0x00000001U -#define AHB_DMA_OUTFIFO_EMPTY_CH2_S 1 -/** AHB_DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 2 - */ -#define AHB_DMA_OUTFIFO_CNT_CH2 0x0000007FU -#define AHB_DMA_OUTFIFO_CNT_CH2_M (AHB_DMA_OUTFIFO_CNT_CH2_V << AHB_DMA_OUTFIFO_CNT_CH2_S) -#define AHB_DMA_OUTFIFO_CNT_CH2_V 0x0000007FU -#define AHB_DMA_OUTFIFO_CNT_CH2_S 8 -/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S) -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 -/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S) -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 -/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S) -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 -/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; - * reserved - */ -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S) -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 - -/** AHB_DMA_OUT_PUSH_CH2_REG register - * Push control register of TX channel 2 - */ -#define AHB_DMA_OUT_PUSH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x25c) -/** AHB_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ -#define AHB_DMA_OUTFIFO_WDATA_CH2 0x000001FFU -#define AHB_DMA_OUTFIFO_WDATA_CH2_M (AHB_DMA_OUTFIFO_WDATA_CH2_V << AHB_DMA_OUTFIFO_WDATA_CH2_S) -#define AHB_DMA_OUTFIFO_WDATA_CH2_V 0x000001FFU -#define AHB_DMA_OUTFIFO_WDATA_CH2_S 0 -/** AHB_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ -#define AHB_DMA_OUTFIFO_PUSH_CH2 (BIT(9)) -#define AHB_DMA_OUTFIFO_PUSH_CH2_M (AHB_DMA_OUTFIFO_PUSH_CH2_V << AHB_DMA_OUTFIFO_PUSH_CH2_S) -#define AHB_DMA_OUTFIFO_PUSH_CH2_V 0x00000001U -#define AHB_DMA_OUTFIFO_PUSH_CH2_S 9 - -/** AHB_DMA_OUT_LINK_CH2_REG register - * Push control register of TX channel 2 - */ -#define AHB_DMA_OUT_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x260) -/** AHB_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 2 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ -#define AHB_DMA_OUTLINK_STOP_CH2 (BIT(0)) -#define AHB_DMA_OUTLINK_STOP_CH2_M (AHB_DMA_OUTLINK_STOP_CH2_V << AHB_DMA_OUTLINK_STOP_CH2_S) -#define AHB_DMA_OUTLINK_STOP_CH2_V 0x00000001U -#define AHB_DMA_OUTLINK_STOP_CH2_S 0 -/** AHB_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 2 for data transfer. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_OUTLINK_START_CH2 (BIT(1)) -#define AHB_DMA_OUTLINK_START_CH2_M (AHB_DMA_OUTLINK_START_CH2_V << AHB_DMA_OUTLINK_START_CH2_S) -#define AHB_DMA_OUTLINK_START_CH2_V 0x00000001U -#define AHB_DMA_OUTLINK_START_CH2_S 1 -/** AHB_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 2 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ -#define AHB_DMA_OUTLINK_RESTART_CH2 (BIT(2)) -#define AHB_DMA_OUTLINK_RESTART_CH2_M (AHB_DMA_OUTLINK_RESTART_CH2_V << AHB_DMA_OUTLINK_RESTART_CH2_S) -#define AHB_DMA_OUTLINK_RESTART_CH2_V 0x00000001U -#define AHB_DMA_OUTLINK_RESTART_CH2_S 2 -/** AHB_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ -#define AHB_DMA_OUTLINK_PARK_CH2 (BIT(3)) -#define AHB_DMA_OUTLINK_PARK_CH2_M (AHB_DMA_OUTLINK_PARK_CH2_V << AHB_DMA_OUTLINK_PARK_CH2_S) -#define AHB_DMA_OUTLINK_PARK_CH2_V 0x00000001U -#define AHB_DMA_OUTLINK_PARK_CH2_S 3 - -/** AHB_DMA_OUT_STATE_CH2_REG register - * Transmit status of TX channel 2 - */ -#define AHB_DMA_OUT_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x264) -/** AHB_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S) -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S 0 -/** AHB_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_DSCR_STATE_CH2 0x00000003U -#define AHB_DMA_OUT_DSCR_STATE_CH2_M (AHB_DMA_OUT_DSCR_STATE_CH2_V << AHB_DMA_OUT_DSCR_STATE_CH2_S) -#define AHB_DMA_OUT_DSCR_STATE_CH2_V 0x00000003U -#define AHB_DMA_OUT_DSCR_STATE_CH2_S 18 -/** AHB_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define AHB_DMA_OUT_STATE_CH2 0x00000007U -#define AHB_DMA_OUT_STATE_CH2_M (AHB_DMA_OUT_STATE_CH2_V << AHB_DMA_OUT_STATE_CH2_S) -#define AHB_DMA_OUT_STATE_CH2_V 0x00000007U -#define AHB_DMA_OUT_STATE_CH2_S 20 - -/** AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG register - * Transmit descriptor address when EOF occurs on TX channel 2 - */ -#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x268) -/** AHB_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ -#define AHB_DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_M (AHB_DMA_OUT_EOF_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_DES_ADDR_CH2_S) -#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_S 0 - -/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register - * The last transmit descriptor address when EOF occurs on TX channel 2 - */ -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x26c) -/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S) -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 - -/** AHB_DMA_OUT_DSCR_CH2_REG register - * Current transmit descriptor address of TX channel 2 - */ -#define AHB_DMA_OUT_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x270) -/** AHB_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_CH2_M (AHB_DMA_OUTLINK_DSCR_CH2_V << AHB_DMA_OUTLINK_DSCR_CH2_S) -#define AHB_DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_CH2_S 0 - -/** AHB_DMA_OUT_DSCR_BF0_CH2_REG register - * The last transmit descriptor address of TX channel 2 - */ -#define AHB_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x274) -/** AHB_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_M (AHB_DMA_OUTLINK_DSCR_BF0_CH2_V << AHB_DMA_OUTLINK_DSCR_BF0_CH2_S) -#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_S 0 - -/** AHB_DMA_OUT_DSCR_BF1_CH2_REG register - * The second-to-last transmit descriptor address of TX channel 2 - */ -#define AHB_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x278) -/** AHB_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ -#define AHB_DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_M (AHB_DMA_OUTLINK_DSCR_BF1_CH2_V << AHB_DMA_OUTLINK_DSCR_BF1_CH2_S) -#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_S 0 - -/** AHB_DMA_OUT_PERI_CH2_REG register - * Priority register of TX channel 2 - */ -#define AHB_DMA_OUT_PERI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x27c) -/** AHB_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 2.The larger of the value, the higher of the - * priority.. - */ -#define AHB_DMA_TX_PRI_CH2 0x0000000FU -#define AHB_DMA_TX_PRI_CH2_M (AHB_DMA_TX_PRI_CH2_V << AHB_DMA_TX_PRI_CH2_S) -#define AHB_DMA_TX_PRI_CH2_V 0x0000000FU -#define AHB_DMA_TX_PRI_CH2_S 0 - -/** AHB_DMA_OUT_PERI_SEL_CH2_REG register - * Peripheral selection register of TX channel 2 - */ -#define AHB_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x280) -/** AHB_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 2. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - * \ - */ -#define AHB_DMA_PERI_OUT_SEL_CH2 0x0000003FU -#define AHB_DMA_PERI_OUT_SEL_CH2_M (AHB_DMA_PERI_OUT_SEL_CH2_V << AHB_DMA_PERI_OUT_SEL_CH2_S) -#define AHB_DMA_PERI_OUT_SEL_CH2_V 0x0000003FU -#define AHB_DMA_PERI_OUT_SEL_CH2_S 0 - -/** AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG register - * TX channel 0 arbitration weight configuration register - */ -#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) -/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel0 - */ -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S) -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S 0 - -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG register - * TX channel 0 weight arbitration optimization enable register - */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S) -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S 0 - -/** AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG register - * TX channel 1 arbitration weight configuration register - */ -#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) -/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel1 - */ -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S) -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S 0 - -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG register - * TX channel 1 weight arbitration optimization enable register - */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S) -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S 0 - -/** AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG register - * TX channel 2 arbitration weight configuration register - */ -#define AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x32c) -/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel2 - */ -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S) -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S 0 - -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG register - * TX channel 2 weight arbitration optimization enable register - */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x330) -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S) -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S 0 - -/** AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG register - * RX channel 0 arbitration weight configuration register - */ -#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) -/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel0 - */ -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S) -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S 0 - -/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG register - * RX channel 0 weight arbitration optimization enable register - */ -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) -/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S) -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S 0 - -/** AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG register - * RX channel 1 arbitration weight configuration register - */ -#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) -/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel1 - */ -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S) -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S 0 - -/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG register - * RX channel 1 weight arbitration optimization enable register - */ -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) -/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S) -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S 0 - -/** AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG register - * RX channel 2 arbitration weight configuration register - */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a4) -/** AHB_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel2 - */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH2 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_M (AHB_DMA_RX_CH_ARB_WEIGH_CH2_V << AHB_DMA_RX_CH_ARB_WEIGH_CH2_S) -#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_V 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_S 0 - -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG register - * RX channel 2 weight arbitration optimization enable register - */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a8) -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S 0 - -/** AHB_DMA_IN_LINK_ADDR_CH0_REG register - * Link list descriptor address configuration of RX channel 0 - */ -#define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac) -/** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ -#define AHB_DMA_INLINK_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_INLINK_ADDR_CH0_M (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S) -#define AHB_DMA_INLINK_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_ADDR_CH0_S 0 - -/** AHB_DMA_IN_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of RX channel 1 - */ -#define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0) -/** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ -#define AHB_DMA_INLINK_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_INLINK_ADDR_CH1_M (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S) -#define AHB_DMA_INLINK_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_ADDR_CH1_S 0 - -/** AHB_DMA_IN_LINK_ADDR_CH2_REG register - * Link list descriptor address configuration of RX channel 2 - */ -#define AHB_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b4) -/** AHB_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ -#define AHB_DMA_INLINK_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_INLINK_ADDR_CH2_M (AHB_DMA_INLINK_ADDR_CH2_V << AHB_DMA_INLINK_ADDR_CH2_S) -#define AHB_DMA_INLINK_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_INLINK_ADDR_CH2_S 0 - -/** AHB_DMA_OUT_LINK_ADDR_CH0_REG register - * Link list descriptor address configuration of TX channel 0 - */ -#define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3b8) -/** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ -#define AHB_DMA_OUTLINK_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_ADDR_CH0_M (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S) -#define AHB_DMA_OUTLINK_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_ADDR_CH0_S 0 - -/** AHB_DMA_OUT_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of TX channel 1 - */ -#define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc) -/** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ -#define AHB_DMA_OUTLINK_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_ADDR_CH1_M (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S) -#define AHB_DMA_OUTLINK_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_ADDR_CH1_S 0 - -/** AHB_DMA_OUT_LINK_ADDR_CH2_REG register - * Link list descriptor address configuration of TX channel 2 - */ -#define AHB_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3c0) -/** AHB_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ -#define AHB_DMA_OUTLINK_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_ADDR_CH2_M (AHB_DMA_OUTLINK_ADDR_CH2_V << AHB_DMA_OUTLINK_ADDR_CH2_S) -#define AHB_DMA_OUTLINK_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_OUTLINK_ADDR_CH2_S 0 - -/** AHB_DMA_INTR_MEM_START_ADDR_REG register - * Accessible address space start address configuration register - */ -#define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c4) -/** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * Accessible address space start address configuration register - */ -#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU -#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S) -#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V 0xFFFFFFFFU -#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S 0 - -/** AHB_DMA_INTR_MEM_END_ADDR_REG register - * Accessible address space end address configuration register - */ -#define AHB_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c8) -/** AHB_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the end address of accessible address space. - */ -#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR 0xFFFFFFFFU -#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_M (AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S) -#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V 0xFFFFFFFFU -#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S 0 - -/** AHB_DMA_ARB_TIMEOUT_TX_REG register - * TX arbitration timeout configuration register - */ -#define AHB_DMA_ARB_TIMEOUT_TX_REG (DR_REG_AHB_DMA_BASE + 0x3cc) -/** AHB_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. - */ -#define AHB_DMA_ARB_TIMEOUT_TX 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_TX_M (AHB_DMA_ARB_TIMEOUT_TX_V << AHB_DMA_ARB_TIMEOUT_TX_S) -#define AHB_DMA_ARB_TIMEOUT_TX_V 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_TX_S 0 - -/** AHB_DMA_ARB_TIMEOUT_RX_REG register - * RX arbitration timeout configuration register - */ -#define AHB_DMA_ARB_TIMEOUT_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d0) -/** AHB_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. - */ -#define AHB_DMA_ARB_TIMEOUT_RX 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_RX_M (AHB_DMA_ARB_TIMEOUT_RX_V << AHB_DMA_ARB_TIMEOUT_RX_S) -#define AHB_DMA_ARB_TIMEOUT_RX_V 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_RX_S 0 - -/** AHB_DMA_WEIGHT_EN_TX_REG register - * TX weight arbitration enable register - */ -#define AHB_DMA_WEIGHT_EN_TX_REG (DR_REG_AHB_DMA_BASE + 0x3d4) -/** AHB_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for TX. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_WEIGHT_EN_TX (BIT(0)) -#define AHB_DMA_WEIGHT_EN_TX_M (AHB_DMA_WEIGHT_EN_TX_V << AHB_DMA_WEIGHT_EN_TX_S) -#define AHB_DMA_WEIGHT_EN_TX_V 0x00000001U -#define AHB_DMA_WEIGHT_EN_TX_S 0 - -/** AHB_DMA_WEIGHT_EN_RX_REG register - * RX weight arbitration enable register - */ -#define AHB_DMA_WEIGHT_EN_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d8) -/** AHB_DMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for RX. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_WEIGHT_EN_RX (BIT(0)) -#define AHB_DMA_WEIGHT_EN_RX_M (AHB_DMA_WEIGHT_EN_RX_V << AHB_DMA_WEIGHT_EN_RX_S) -#define AHB_DMA_WEIGHT_EN_RX_V 0x00000001U -#define AHB_DMA_WEIGHT_EN_RX_S 0 - -/** AHB_DMA_ARB_TIMEOUT_REG register - * TX arbitration timeout configuration register - */ -#define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x3dc) -/** AHB_DMA_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot. Measurement unit: AHB bus clock cycle. - */ -#define AHB_DMA_ARB_TIMEOUT_NUM 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_NUM_M (AHB_DMA_ARB_TIMEOUT_NUM_V << AHB_DMA_ARB_TIMEOUT_NUM_S) -#define AHB_DMA_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_NUM_S 0 - -/** AHB_DMA_WEIGHT_EN_REG register - * TX weight arbitration enable register - */ -#define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x400) -/** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration. - * 0: Disable - * 1: Enable - */ -#define AHB_DMA_WEIGHT_EN (BIT(0)) -#define AHB_DMA_WEIGHT_EN_M (AHB_DMA_WEIGHT_EN_V << AHB_DMA_WEIGHT_EN_S) -#define AHB_DMA_WEIGHT_EN_V 0x00000001U -#define AHB_DMA_WEIGHT_EN_S 0 - -/** AHB_DMA_MODULE_CLK_EN_REG register - * Module clock force on register - */ -#define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x404) -/** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [2:0]; default: 7; - * Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n: - * 0 : Not force on ahb_apb_sync n clock - * 1 : Force on ahb_apb_sync n clock - */ -#define AHB_DMA_AHB_APB_SYNC_CLK_EN 0x00000007U -#define AHB_DMA_AHB_APB_SYNC_CLK_EN_M (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S) -#define AHB_DMA_AHB_APB_SYNC_CLK_EN_V 0x00000007U -#define AHB_DMA_AHB_APB_SYNC_CLK_EN_S 0 -/** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [5:3]; default: 7; - * Configures whether to force on out_dscr 2~0 module clock. For bit n: - * 0 : Not force on out_dscr n clock - * 1 : Force on out_dscr n clock - */ -#define AHB_DMA_OUT_DSCR_CLK_EN 0x00000007U -#define AHB_DMA_OUT_DSCR_CLK_EN_M (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S) -#define AHB_DMA_OUT_DSCR_CLK_EN_V 0x00000007U -#define AHB_DMA_OUT_DSCR_CLK_EN_S 3 -/** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [8:6]; default: 7; - * Configures whether to force on out_ctrl 2~0 module clock. For bit n: - * 0 : Not force on out_ctrl n clock - * 1 : Force on out_ctrl n clock - */ -#define AHB_DMA_OUT_CTRL_CLK_EN 0x00000007U -#define AHB_DMA_OUT_CTRL_CLK_EN_M (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S) -#define AHB_DMA_OUT_CTRL_CLK_EN_V 0x00000007U -#define AHB_DMA_OUT_CTRL_CLK_EN_S 6 -/** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [11:9]; default: 7; - * Configures whether to force on in_dscr 2~0 module clock. For bit n: - * 0 : Not force on in_dscr n clock - * 1 : Force on in_dscr n clock - */ -#define AHB_DMA_IN_DSCR_CLK_EN 0x00000007U -#define AHB_DMA_IN_DSCR_CLK_EN_M (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S) -#define AHB_DMA_IN_DSCR_CLK_EN_V 0x00000007U -#define AHB_DMA_IN_DSCR_CLK_EN_S 9 -/** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [14:12]; default: 7; - * Configures whether to force on in_ctrl 2~0 module clock. For bit n: - * 0 : Not force on in_ctrl n clock - * 1 : Force on in_ctrl n clock - */ -#define AHB_DMA_IN_CTRL_CLK_EN 0x00000007U -#define AHB_DMA_IN_CTRL_CLK_EN_M (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S) -#define AHB_DMA_IN_CTRL_CLK_EN_V 0x00000007U -#define AHB_DMA_IN_CTRL_CLK_EN_S 12 -/** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 0; - * Configures whether to force on cmd_arb module clock. - * 0 : Not force on cmd_arb clock - * 1 : Force on cmd_arb clock - */ -#define AHB_DMA_CMD_ARB_CLK_EN (BIT(27)) -#define AHB_DMA_CMD_ARB_CLK_EN_M (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S) -#define AHB_DMA_CMD_ARB_CLK_EN_V 0x00000001U -#define AHB_DMA_CMD_ARB_CLK_EN_S 27 -/** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 0; - * Configures whether to force on ahbinf module clock. - * 0 : Not force on ahbinf clock - * 1 : Force on ahbinf clock - */ -#define AHB_DMA_AHBINF_CLK_EN (BIT(28)) -#define AHB_DMA_AHBINF_CLK_EN_M (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S) -#define AHB_DMA_AHBINF_CLK_EN_V 0x00000001U -#define AHB_DMA_AHBINF_CLK_EN_S 28 - -/** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register - * AHB response error status 0 register - */ -#define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x408) -/** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents the address of the AHB response error. - */ -#define AHB_DMA_AHBINF_RESP_ERR_ADDR 0xFFFFFFFFU -#define AHB_DMA_AHBINF_RESP_ERR_ADDR_M (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S) -#define AHB_DMA_AHBINF_RESP_ERR_ADDR_V 0xFFFFFFFFU -#define AHB_DMA_AHBINF_RESP_ERR_ADDR_S 0 - -/** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register - * AHB response error status 1 register - */ -#define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x40c) -/** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0; - * Represents the AHB response error is write request. - */ -#define AHB_DMA_AHBINF_RESP_ERR_WR (BIT(0)) -#define AHB_DMA_AHBINF_RESP_ERR_WR_M (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S) -#define AHB_DMA_AHBINF_RESP_ERR_WR_V 0x00000001U -#define AHB_DMA_AHBINF_RESP_ERR_WR_S 0 -/** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [4:1]; default: 15; - * Represents the AHB response error request id. - */ -#define AHB_DMA_AHBINF_RESP_ERR_ID 0x0000000FU -#define AHB_DMA_AHBINF_RESP_ERR_ID_M (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S) -#define AHB_DMA_AHBINF_RESP_ERR_ID_V 0x0000000FU -#define AHB_DMA_AHBINF_RESP_ERR_ID_S 1 -/** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [7:5]; default: 0; - * Represents the AHB response error request channel id.bit[2]=1:TX channel. - * bit[2]=0:RX channel. - */ -#define AHB_DMA_AHBINF_RESP_ERR_CH_ID 0x00000007U -#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S) -#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_V 0x00000007U -#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_S 5 - -/** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register - * RX_done Inlink descriptor address of RX channel 0 - */ -#define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x410) -/** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ -#define AHB_DMA_IN_DONE_DES_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_IN_DONE_DES_ADDR_CH0_M (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S) -#define AHB_DMA_IN_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_IN_DONE_DES_ADDR_CH0_S 0 - -/** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register - * TX done outlink descriptor address of TX channel 0 - */ -#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x414) -/** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ -#define AHB_DMA_OUT_DONE_DES_ADDR_CH0 0xFFFFFFFFU -#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_M (AHB_DMA_OUT_DONE_DES_ADDR_CH0_V << AHB_DMA_OUT_DONE_DES_ADDR_CH0_S) -#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_V 0xFFFFFFFFU -#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_S 0 - -/** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register - * RX_done Inlink descriptor address of RX channel 1 - */ -#define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x418) -/** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ -#define AHB_DMA_IN_DONE_DES_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_IN_DONE_DES_ADDR_CH1_M (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S) -#define AHB_DMA_IN_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_IN_DONE_DES_ADDR_CH1_S 0 - -/** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register - * TX done outlink descriptor address of TX channel 1 - */ -#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x41c) -/** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ -#define AHB_DMA_OUT_DONE_DES_ADDR_CH1 0xFFFFFFFFU -#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_M (AHB_DMA_OUT_DONE_DES_ADDR_CH1_V << AHB_DMA_OUT_DONE_DES_ADDR_CH1_S) -#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU -#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_S 0 - -/** AHB_DMA_IN_DONE_DES_ADDR_CH2_REG register - * RX_done Inlink descriptor address of RX channel 2 - */ -#define AHB_DMA_IN_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x420) -/** AHB_DMA_IN_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ -#define AHB_DMA_IN_DONE_DES_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_IN_DONE_DES_ADDR_CH2_M (AHB_DMA_IN_DONE_DES_ADDR_CH2_V << AHB_DMA_IN_DONE_DES_ADDR_CH2_S) -#define AHB_DMA_IN_DONE_DES_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_IN_DONE_DES_ADDR_CH2_S 0 - -/** AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG register - * TX done outlink descriptor address of TX channel 2 - */ -#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x424) -/** AHB_DMA_OUT_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ -#define AHB_DMA_OUT_DONE_DES_ADDR_CH2 0xFFFFFFFFU -#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_M (AHB_DMA_OUT_DONE_DES_ADDR_CH2_V << AHB_DMA_OUT_DONE_DES_ADDR_CH2_S) -#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_V 0xFFFFFFFFU -#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/ahb_dma_struct.h b/components/soc/esp32c5/register/soc/ahb_dma_struct.h index e452b274f8..9818c003e9 100644 --- a/components/soc/esp32c5/register/soc/ahb_dma_struct.h +++ b/components/soc/esp32c5/register/soc/ahb_dma_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,297 +12,329 @@ extern "C" { /** Group: Interrupt Registers */ /** Type of in_int_raw_chn register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel n */ typedef union { struct { /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_raw:1; /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_raw:1; /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_raw:1; /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_raw:1; /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_raw:1; /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_raw:1; /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_raw:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_raw:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_raw_chn_reg_t; + +/** Group: Status Registers */ /** Type of in_int_st_chn register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel n */ typedef union { struct { /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_st:1; /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_st:1; /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_st:1; /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_st:1; /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_st:1; /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_st:1; /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_st:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_st:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_st_chn_reg_t; /** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel n */ typedef union { struct { /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CHn_INT. + * Write 1 to enable AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_ena:1; /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_ena:1; /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_ena:1; /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CHn_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_ena:1; /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_ena:1; /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CHn_INT. + * Write 1 to enable AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_ena:1; /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CHn_INT. + * Write 1 to enable AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_ena:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_ena:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_ena_chn_reg_t; /** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel n */ typedef union { struct { /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CHn_INT. + * Write 1 to clear AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_clr:1; /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_clr:1; /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_clr:1; /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CHn_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_clr:1; /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_clr:1; /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CHn_INT. + * Write 1 to clear AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_clr:1; /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CHn_INT. + * Write 1 to clear AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_clr:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_clr:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_clr_chn_reg_t; /** Type of out_int_raw_chn register - * Raw interrupt status of TX channel 0 + * //Raw interrupt status of TX channel n */ typedef union { struct { /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_raw:1; /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_raw:1; /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_raw:1; /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_raw:1; /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_raw:1; /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_raw:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_raw:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_raw_chn_reg_t; /** Type of out_int_st_chn register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel n */ typedef union { struct { /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_st:1; /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_st:1; /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_st:1; /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_st:1; /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_st:1; /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_st:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_st:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_st_chn_reg_t; /** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel n */ typedef union { struct { /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_ena:1; /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_ena:1; /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_ena:1; /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_ena:1; /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CHn_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_ena:1; /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CHn_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_ena:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_ena:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_ena_chn_reg_t; /** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel n */ typedef union { struct { /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_clr:1; /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_clr:1; /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_clr:1; /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_clr:1; /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CHn_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_clr:1; /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CHn_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_clr:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_clr:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_clr_chn_reg_t; - -/** Group: Debug Registers */ /** Type of ahb_test register - * reserved + * only for test */ typedef union { struct { @@ -320,26 +352,26 @@ typedef union { uint32_t val; } ahb_dma_ahb_test_reg_t; - -/** Group: Configuration Registers */ /** Type of misc_conf register - * Miscellaneous register + * reserved */ typedef union { struct { /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM. + * Write 1 and then 0 to reset the internal AHB FSM */ uint32_t ahbm_rst_inter:1; uint32_t reserved_1:1; /** arb_pri_dis : R/W; bitpos: [2]; default: 0; - * Configures whether or not to disable the fixed-priority channel arbitration.\\0: - * Enable\\1: Disable\\ + * Configures whether to disable the fixed-priority channel arbitration. + * 0: Enable + * 1: Disable */ uint32_t arb_pri_dis:1; /** clk_en : R/W; bitpos: [3]; default: 0; - * Configures clock gating.\\0: Support clock only when the application writes - * registers.\\ 1: Always force the clock on for registers.\\ + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ uint32_t clk_en:1; uint32_t reserved_4:28; @@ -347,38 +379,58 @@ typedef union { uint32_t val; } ahb_dma_misc_conf_reg_t; +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 2410220; + * Version control register + */ + uint32_t date:32; + }; + uint32_t val; +} ahb_dma_date_reg_t; + /** Type of in_conf0_chn register - * Configuration register 0 of RX channel 0 + * Configuration register 0 of RX channel n */ typedef union { struct { /** in_rst_chn : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset AHB_DMA channel n RX FSM and RX FIFO pointer. */ uint32_t in_rst_chn:1; /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; - * Reserved. + * reserved */ uint32_t in_loop_test_chn:1; /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable INCR burst transfer for RX channel n to read - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for RX channel n to read + * descriptors. + * 0: Disable + * 1: Enable */ uint32_t indscr_burst_en_chn:1; uint32_t reserved_3:1; /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable */ uint32_t mem_trans_en_chn:1; /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ETM control for RX channeln.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for RX channeln. + * 0: Disable + * 1: Enable */ uint32_t in_etm_en_chn:1; /** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures max burst size for Rx channeln. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ uint32_t in_data_burst_mode_sel_chn:2; uint32_t reserved_8:24; @@ -393,8 +445,9 @@ typedef union { struct { uint32_t reserved_0:12; /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for RX channel n.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for RX channel n. + * 0: Disable + * 1: Enable */ uint32_t in_check_owner_chn:1; uint32_t reserved_13:19; @@ -402,368 +455,26 @@ typedef union { uint32_t val; } ahb_dma_in_conf1_chn_reg_t; -/** Type of in_pop_chn register - * Pop control register of RX channel 0 - */ -typedef union { - struct { - /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ - uint32_t infifo_rdata_chn:12; - /** infifo_pop_chn : WT; bitpos: [12]; default: 0; - * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: - * Pop\\ - */ - uint32_t infifo_pop_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_pop_chn_reg_t; - -/** Type of in_link_chn register - * Linked list descriptor configuration and control register of RX channel 0 - */ -typedef union { - struct { - /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1; - * Configures whether or not to return to current receive descriptor's address when - * there are some errors in current receiving data.\\0: Not return\\1: Return\\ - */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : WT; bitpos: [1]; default: 0; - * Configures whether or not to stop AHB_DMA's RX channel n from receiving data.\\0: - * Invalid. No effect\\1: Stop\\ - */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable AHB_DMA's RX channel n for data transfer.\\0: - * Disable\\1: Enable\\ - */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : WT; bitpos: [3]; default: 0; - * Configures whether or not to restart RX channel n for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ - */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ - */ - uint32_t inlink_park_chn:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} ahb_dma_in_link_chn_reg_t; - -/** Type of out_conf1_chn register - * Configuration register 1 of TX channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for TX channel n.\\0: - * Disable\\1: Enable\\ - */ - uint32_t out_check_owner_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_out_conf1_chn_reg_t; - -/** Type of out_push_chn register - * Push control register of TX channel 0 - */ -typedef union { - struct { - /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ - uint32_t outfifo_wdata_chn:9; - /** outfifo_push_chn : WT; bitpos: [9]; default: 0; - * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No - * effect\\1: Push\\ - */ - uint32_t outfifo_push_chn:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_push_chn_reg_t; - -/** Type of out_link_chn register - * Linked list descriptor configuration and control register of TX channel 0 - */ -typedef union { - struct { - /** outlink_stop_chn : WT; bitpos: [0]; default: 0; - * Configures whether or not to stop AHB_DMA's TX channel n from transmitting - * data.\\0: Invalid. No effect\\1: Stop\\ - */ - uint32_t outlink_stop_chn:1; - /** outlink_start_chn : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable AHB_DMA's TX channel n for data transfer.\\0: - * Disable\\1: Enable\\ - */ - uint32_t outlink_start_chn:1; - /** outlink_restart_chn : WT; bitpos: [2]; default: 0; - * Configures whether or not to restart TX channel n for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ - */ - uint32_t outlink_restart_chn:1; - /** outlink_park_chn : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ - */ - uint32_t outlink_park_chn:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_link_chn_reg_t; - -/** Type of out_conf0_chn register - * Configuration register 0 of TX channel 1 - */ -typedef union { - struct { - /** out_rst_chn : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel n TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ - */ - uint32_t out_rst_chn:1; - /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t out_loop_test_chn:1; - /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ - */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel n is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel n is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ - */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel n reading - * descriptors.\\0: Disable\\1: Enable\\ - */ - uint32_t outdscr_burst_en_chn:1; - uint32_t reserved_5:1; - /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel n.\\0: Disable\\1: - * Enable\\ - */ - uint32_t out_etm_en_chn:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ - */ - uint32_t out_data_burst_mode_sel_chn:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_chn_reg_t; - -/** Type of tx_ch_arb_weigh_chn register - * TX channel 0 arbitration weight configuration register - */ -typedef union { - struct { - /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channeln - */ - uint32_t tx_ch_arb_weigh_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_tx_ch_arb_weigh_chn_reg_t; - -/** Type of tx_arb_weigh_opt_dir_chn register - * TX channel 0 weight arbitration optimization enable register - */ -typedef union { - struct { - /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t tx_arb_weigh_opt_dir_chn:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t; - -/** Type of rx_ch_arb_weigh_chn register - * RX channel 0 arbitration weight configuration register - */ -typedef union { - struct { - /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channeln - */ - uint32_t rx_ch_arb_weigh_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_rx_ch_arb_weigh_chn_reg_t; - -/** Type of rx_arb_weigh_opt_dir_chn register - * RX channel 0 weight arbitration optimization enable register - */ -typedef union { - struct { - /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rx_arb_weigh_opt_dir_chn:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t; - -/** Type of in_link_addr_chn register - * Link list descriptor address configuration of RX channel 0 - */ -typedef union { - struct { - /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t inlink_addr_chn:32; - }; - uint32_t val; -} ahb_dma_in_link_addr_chn_reg_t; - -/** Type of out_link_addr_chn register - * Link list descriptor address configuration of TX channel 0 - */ -typedef union { - struct { - /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t outlink_addr_chn:32; - }; - uint32_t val; -} ahb_dma_out_link_addr_chn_reg_t; - -/** Type of intr_mem_start_addr register - * Accessible address space start address configuration register - */ -typedef union { - struct { - /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0; - * Configures the start address of accessible address space. - */ - uint32_t access_intr_mem_start_addr:32; - }; - uint32_t val; -} ahb_dma_intr_mem_start_addr_reg_t; - -/** Type of intr_mem_end_addr register - * Accessible address space end address configuration register - */ -typedef union { - struct { - /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the end address of accessible address space. - */ - uint32_t access_intr_mem_end_addr:32; - }; - uint32_t val; -} ahb_dma_intr_mem_end_addr_reg_t; - -/** Type of arb_timeout_tx register - * TX arbitration timeout configuration register - */ -typedef union { - struct { - /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. - */ - uint32_t arb_timeout_tx:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} ahb_dma_arb_timeout_tx_reg_t; - -/** Type of arb_timeout_rx register - * RX arbitration timeout configuration register - */ -typedef union { - struct { - /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. - */ - uint32_t arb_timeout_rx:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} ahb_dma_arb_timeout_rx_reg_t; - -/** Type of weight_en_tx register - * TX weight arbitration enable register - */ -typedef union { - struct { - /** weight_en_tx : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for TX.\\0: Disable\\1: Enable\\ - */ - uint32_t weight_en_tx:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_weight_en_tx_reg_t; - -/** Type of weight_en_rx register - * RX weight arbitration enable register - */ -typedef union { - struct { - /** weight_en_rx : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for RX.\\0: Disable\\1: Enable\\ - */ - uint32_t weight_en_rx:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_weight_en_rx_reg_t; - - -/** Group: Version Registers */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 36770448; - * Version control register. - */ - uint32_t date:32; - }; - uint32_t val; -} ahb_dma_date_reg_t; - - -/** Group: Status Registers */ /** Type of infifo_status_chn register - * Receive FIFO status of RX channel 0 + * Receive FIFO status of RX channel n */ typedef union { struct { /** infifo_full_chn : RO; bitpos: [0]; default: 1; - * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full */ uint32_t infifo_full_chn:1; /** infifo_empty_chn : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty */ uint32_t infifo_empty_chn:1; uint32_t reserved_2:6; /** infifo_cnt_chn : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel n. + * Represents the number of data bytes in L1 RX FIFO for RX channel n */ uint32_t infifo_cnt_chn:7; uint32_t reserved_15:8; @@ -792,14 +503,75 @@ typedef union { uint32_t val; } ahb_dma_infifo_status_chn_reg_t; +/** Type of in_pop_chn register + * Receive FIFO status of RX channel n + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * Represents the data popped from AHB_DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Configures whether to pop data from AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Pop + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Receive FIFO status of RX channel n + */ +typedef union { + struct { + /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1; + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. + * 0: Not return + * 1: Return + * . + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [1]; default: 0; + * Configures whether to stop AHB_DMA's RX channel n from receiving data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [2]; default: 0; + * Configures whether to enable AHB_DMA's RX channel n for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [3]; default: 0; + * Configures whether to restart RX channel n for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [4]; default: 1; + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} ahb_dma_in_link_chn_reg_t; + /** Type of in_state_chn register - * Receive status of RX channel 0 + * Receive status of RX channel n */ typedef union { struct { /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * reserved */ uint32_t inlink_dscr_addr_chn:18; /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; @@ -807,7 +579,8 @@ typedef union { */ uint32_t in_dscr_state_chn:2; /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. */ uint32_t in_state_chn:3; uint32_t reserved_23:9; @@ -816,7 +589,7 @@ typedef union { } ahb_dma_in_state_chn_reg_t; /** Type of in_suc_eof_des_addr_chn register - * Receive descriptor address when EOF occurs on RX channel 0 + * Receive descriptor address when EOF occurs on RX channel n */ typedef union { struct { @@ -830,7 +603,7 @@ typedef union { } ahb_dma_in_suc_eof_des_addr_chn_reg_t; /** Type of in_err_eof_des_addr_chn register - * Receive descriptor address when errors occur of RX channel 0 + * Receive descriptor address when errors occur of RX channel n */ typedef union { struct { @@ -844,7 +617,7 @@ typedef union { } ahb_dma_in_err_eof_des_addr_chn_reg_t; /** Type of in_dscr_chn register - * Current receive descriptor address of RX channel 0 + * Current receive descriptor address of RX channel n */ typedef union { struct { @@ -858,7 +631,7 @@ typedef union { } ahb_dma_in_dscr_chn_reg_t; /** Type of in_dscr_bf0_chn register - * The last receive descriptor address of RX channel 0 + * The last receive descriptor address of RX channel n */ typedef union { struct { @@ -872,7 +645,7 @@ typedef union { } ahb_dma_in_dscr_bf0_chn_reg_t; /** Type of in_dscr_bf1_chn register - * The second-to-last receive descriptor address of RX channel 0 + * The second-to-last receive descriptor address of RX channel n */ typedef union { struct { @@ -885,39 +658,161 @@ typedef union { uint32_t val; } ahb_dma_in_dscr_bf1_chn_reg_t; +/** Type of in_pri_chn register + * Priority register of RX channel n + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel n.The larger of the value, the higher of the + * priority.. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_in_pri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection register of RX channel n + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel n. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_in_peri_sel_chn_reg_t; + +/** Type of out_conf0_chn register + * Configuration register 0 of TX channel n + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * Configures the reset state of AHB_DMA channel n TX FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel n is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel n is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel n reading + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t outdscr_burst_en_chn:1; + uint32_t reserved_5:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel n. + * 0: Disable + * 1: Enable + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:1; + /** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0; + * Configures max burst size for TX channeln. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 + */ + uint32_t out_data_burst_mode_sel_chn:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_conf0_chn_reg_t; + +/** Type of out_conf1_chn register + * Configuration register 1 of TX channel n + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Configures whether to enable owner bit check for TX channel n. + * 0: Disable + * 1: Enable + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} ahb_dma_out_conf1_chn_reg_t; + /** Type of outfifo_status_chn register - * Transmit FIFO status of TX channel 0 + * Receive FIFO status of RX channel n */ typedef union { struct { /** outfifo_full_chn : RO; bitpos: [0]; default: 0; - * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full */ uint32_t outfifo_full_chn:1; /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty */ uint32_t outfifo_empty_chn:1; uint32_t reserved_2:6; /** outfifo_cnt_chn : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel n. + * Represents the number of data bytes in L1 TX FIFO for TX channel n */ uint32_t outfifo_cnt_chn:7; uint32_t reserved_15:8; /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ uint32_t out_remain_under_1b_chn:1; /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ uint32_t out_remain_under_2b_chn:1; /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ uint32_t out_remain_under_3b_chn:1; /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ uint32_t out_remain_under_4b_chn:1; uint32_t reserved_27:5; @@ -925,8 +820,62 @@ typedef union { uint32_t val; } ahb_dma_outfifo_status_chn_reg_t; +/** Type of out_push_chn register + * Push control register of TX channel n + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Configures the data that need to be pushed into AHB_DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Push control register of TX channel n + */ +typedef union { + struct { + /** outlink_stop_chn : WT; bitpos: [0]; default: 0; + * Configures whether to stop AHB_DMA's TX channel n from transmitting data. + * 0: Invalid. No effect + * 1: Stop + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [1]; default: 0; + * Configures whether to enable AHB_DMA's TX channel n for data transfer. + * 0: Disable + * 1: Enable + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [2]; default: 0; + * Configures whether to restart TX channel n for AHB_DMA transfer. + * 0: Invalid. No effect + * 1: Restart + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [3]; default: 1; + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_out_link_chn_reg_t; + /** Type of out_state_chn register - * Transmit status of TX channel 0 + * Transmit status of TX channel n */ typedef union { struct { @@ -949,7 +898,7 @@ typedef union { } ahb_dma_out_state_chn_reg_t; /** Type of out_eof_des_addr_chn register - * Transmit descriptor address when EOF occurs on TX channel 0 + * Transmit descriptor address when EOF occurs on TX channel n */ typedef union { struct { @@ -963,7 +912,7 @@ typedef union { } ahb_dma_out_eof_des_addr_chn_reg_t; /** Type of out_eof_bfr_des_addr_chn register - * The last transmit descriptor address when EOF occurs on TX channel 0 + * The last transmit descriptor address when EOF occurs on TX channel n */ typedef union { struct { @@ -977,7 +926,7 @@ typedef union { } ahb_dma_out_eof_bfr_des_addr_chn_reg_t; /** Type of out_dscr_chn register - * Current transmit descriptor address of TX channel 0 + * Current transmit descriptor address of TX channel n */ typedef union { struct { @@ -991,7 +940,7 @@ typedef union { } ahb_dma_out_dscr_chn_reg_t; /** Type of out_dscr_bf0_chn register - * The last transmit descriptor address of TX channel 0 + * The last transmit descriptor address of TX channel n */ typedef union { struct { @@ -1005,7 +954,7 @@ typedef union { } ahb_dma_out_dscr_bf0_chn_reg_t; /** Type of out_dscr_bf1_chn register - * The second-to-last transmit descriptor address of TX channel 0 + * The second-to-last transmit descriptor address of TX channel n */ typedef union { struct { @@ -1018,31 +967,14 @@ typedef union { uint32_t val; } ahb_dma_out_dscr_bf1_chn_reg_t; - -/** Group: Priority Registers */ -/** Type of in_pri_chn register - * Priority register of RX channel 0 - */ -typedef union { - struct { - /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel n.The larger of the value, the higher of the - * priority. - */ - uint32_t rx_pri_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_pri_chn_reg_t; - /** Type of out_pri_chn register - * Priority register of TX channel 0 + * Priority register of TX channel n */ typedef union { struct { /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; * Configures the priority of TX channel n.The larger of the value, the higher of the - * priority. + * priority.. */ uint32_t tx_pri_chn:4; uint32_t reserved_4:28; @@ -1050,33 +982,27 @@ typedef union { uint32_t val; } ahb_dma_out_pri_chn_reg_t; - -/** Group: Peripheral Select Registers */ -/** Type of in_peri_sel_chn register - * Peripheral selection register of RX channel 0 - */ -typedef union { - struct { - /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ - */ - uint32_t peri_in_sel_chn:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_chn_reg_t; - /** Type of out_peri_sel_chn register - * Peripheral selection register of TX channel 0 + * Peripheral selection register of TX channel n */ typedef union { struct { /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to TX channel n. + * 0: Dummy + * 1: SPI2 + * 2: UHCI0 + * 3: I2S0 + * 4: Dummy + * 5: Dummy + * 6: AES + * 7: SHA + * 8: ADC_DAC + * 9: PARL_IO + * 10: CH0 M2M (auto selected by hw) + * 11: CH1 M2M (auto selected by hw) + * 12: CH2 M2M (auto selected by hw) + * 13~15: Dummy */ uint32_t peri_out_sel_chn:6; uint32_t reserved_6:26; @@ -1084,6 +1010,259 @@ typedef union { uint32_t val; } ahb_dma_out_peri_sel_chn_reg_t; +/** Type of tx_ch_arb_weight_chn register + * TX channel n arbitration weight configuration register + */ +typedef union { + struct { + /** tx_arb_weight_value_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channeln + */ + uint32_t tx_arb_weight_value_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_tx_ch_arb_weight_chn_reg_t; + +/** Type of tx_arb_weight_opt_dis_chn register + * TX channel n weight arbitration optimization enable register + */ +typedef union { + struct { + /** tx_arb_weight_opt_dis_chn : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t tx_arb_weight_opt_dis_chn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_tx_arb_weight_opt_dis_chn_reg_t; + +/** Type of rx_ch_arb_weight_chn register + * RX channel n arbitration weight configuration register + */ +typedef union { + struct { + /** rx_arb_weight_value_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channeln + */ + uint32_t rx_arb_weight_value_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_rx_ch_arb_weight_chn_reg_t; + +/** Type of rx_arb_weight_opt_dis_chn register + * RX channel n weight arbitration optimization enable register + */ +typedef union { + struct { + /** rx_arb_weight_opt_dis_chn : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t rx_arb_weight_opt_dis_chn:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_rx_arb_weight_opt_dis_chn_reg_t; + +/** Type of in_link_addr_chn register + * Link list descriptor address configuration of RX channel n + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address + */ + uint32_t inlink_addr_chn:32; + }; + uint32_t val; +} ahb_dma_in_link_addr_chn_reg_t; + +/** Type of out_link_addr_chn register + * Link list descriptor address configuration of TX channel n + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; + * Configures the 32 bits of the first receive descriptor's address. + */ + uint32_t outlink_addr_chn:32; + }; + uint32_t val; +} ahb_dma_out_link_addr_chn_reg_t; + +/** Type of intr_mem_start_addr register + * Accessible address space start address configuration register + */ +typedef union { + struct { + /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Accessible address space start address configuration register + */ + uint32_t access_intr_mem_start_addr:32; + }; + uint32_t val; +} ahb_dma_intr_mem_start_addr_reg_t; + +/** Type of intr_mem_end_addr register + * Accessible address space end address configuration register + */ +typedef union { + struct { + /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the end address of accessible address space. + */ + uint32_t access_intr_mem_end_addr:32; + }; + uint32_t val; +} ahb_dma_intr_mem_end_addr_reg_t; + +/** Type of arb_timeout register + * TX arbitration timeout configuration register + */ +typedef union { + struct { + /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot. Measurement unit: AHB bus clock cycle. + */ + uint32_t arb_timeout_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} ahb_dma_arb_timeout_reg_t; + +/** Type of weight_en register + * TX weight arbitration enable register + */ +typedef union { + struct { + /** weight_en : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration. + * 0: Disable + * 1: Enable + */ + uint32_t weight_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_weight_en_reg_t; + +/** Type of module_clk_en register + * Module clock force on register + */ +typedef union { + struct { + /** ahb_apb_sync_clk_en : R/W; bitpos: [2:0]; default: 7; + * Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n: + * 0 : Not force on ahb_apb_sync n clock + * 1 : Force on ahb_apb_sync n clock + */ + uint32_t ahb_apb_sync_clk_en:3; + /** out_dscr_clk_en : R/W; bitpos: [5:3]; default: 7; + * Configures whether to force on out_dscr 2~0 module clock. For bit n: + * 0 : Not force on out_dscr n clock + * 1 : Force on out_dscr n clock + */ + uint32_t out_dscr_clk_en:3; + /** out_ctrl_clk_en : R/W; bitpos: [8:6]; default: 7; + * Configures whether to force on out_ctrl 2~0 module clock. For bit n: + * 0 : Not force on out_ctrl n clock + * 1 : Force on out_ctrl n clock + */ + uint32_t out_ctrl_clk_en:3; + /** in_dscr_clk_en : R/W; bitpos: [11:9]; default: 7; + * Configures whether to force on in_dscr 2~0 module clock. For bit n: + * 0 : Not force on in_dscr n clock + * 1 : Force on in_dscr n clock + */ + uint32_t in_dscr_clk_en:3; + /** in_ctrl_clk_en : R/W; bitpos: [14:12]; default: 7; + * Configures whether to force on in_ctrl 2~0 module clock. For bit n: + * 0 : Not force on in_ctrl n clock + * 1 : Force on in_ctrl n clock + */ + uint32_t in_ctrl_clk_en:3; + uint32_t reserved_15:12; + /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0; + * Configures whether to force on cmd_arb module clock. + * 0 : Not force on cmd_arb clock + * 1 : Force on cmd_arb clock + */ + uint32_t cmd_arb_clk_en:1; + /** ahbinf_clk_en : R/W; bitpos: [28]; default: 0; + * Configures whether to force on ahbinf module clock. + * 0 : Not force on ahbinf clock + * 1 : Force on ahbinf clock + */ + uint32_t ahbinf_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} ahb_dma_module_clk_en_reg_t; + +/** Type of ahbinf_resp_err_status0 register + * AHB response error status 0 register + */ +typedef union { + struct { + /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0; + * Represents the address of the AHB response error. + */ + uint32_t ahbinf_resp_err_addr:32; + }; + uint32_t val; +} ahb_dma_ahbinf_resp_err_status0_reg_t; + +/** Type of ahbinf_resp_err_status1 register + * AHB response error status 1 register + */ +typedef union { + struct { + /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0; + * Represents the AHB response error is write request. + */ + uint32_t ahbinf_resp_err_wr:1; + /** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15; + * Represents the AHB response error request id. + */ + uint32_t ahbinf_resp_err_id:4; + /** ahbinf_resp_err_ch_id : RO; bitpos: [7:5]; default: 0; + * Represents the AHB response error request channel id.bit[2]=1:TX channel. + * bit[2]=0:RX channel. + */ + uint32_t ahbinf_resp_err_ch_id:3; + uint32_t reserved_8:24; + }; + uint32_t val; +} ahb_dma_ahbinf_resp_err_status1_reg_t; + +/** Type of in_done_des_addr_chn register + * RX_done Inlink descriptor address of RX channel n + */ +typedef union { + struct { + /** in_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ + uint32_t in_done_des_addr_chn:32; + }; + uint32_t val; +} ahb_dma_in_done_des_addr_chn_reg_t; + +/** Type of out_done_des_addr_chn register + * TX done outlink descriptor address of TX channel n + */ +typedef union { + struct { + /** out_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ + uint32_t out_done_des_addr_chn:32; + }; + uint32_t val; +} ahb_dma_out_done_des_addr_chn_reg_t; + typedef struct { volatile ahb_dma_in_int_raw_chn_reg_t raw; volatile ahb_dma_in_int_st_chn_reg_t st; @@ -1139,16 +1318,21 @@ typedef struct { typedef struct { uint32_t reserved[8]; - ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh; - ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt; + ahb_dma_rx_ch_arb_weight_chn_reg_t ch_arb_weight; + ahb_dma_rx_arb_weight_opt_dis_chn_reg_t arb_weight_opt; } ahb_dma_in_crc_arb_chn_reg_t; typedef struct { uint32_t reserved[8]; - ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh; - ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt; + ahb_dma_tx_ch_arb_weight_chn_reg_t ch_arb_weight; + ahb_dma_tx_arb_weight_opt_dis_chn_reg_t arb_weight_opt; } ahb_dma_out_crc_arb_chn_reg_t; +typedef struct { + ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr; + ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr; +} ahb_dma_done_des_addr_chn_reg_t; + typedef struct { volatile ahb_dma_in_int_chn_reg_t in_intr[3]; volatile ahb_dma_out_int_chn_reg_t out_intr[3]; @@ -1164,16 +1348,20 @@ typedef struct { volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[3]; volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr; volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr; - volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx; - volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx; - volatile ahb_dma_weight_en_tx_reg_t weight_en_tx; - volatile ahb_dma_weight_en_rx_reg_t weight_en_rx; + uint32_t reserved_3cc[4]; + volatile ahb_dma_arb_timeout_reg_t arb_timeout; + uint32_t reserved_3e0[8]; + volatile ahb_dma_weight_en_reg_t weight_en; + volatile ahb_dma_module_clk_en_reg_t module_clk_en; + volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0; + volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1; + volatile ahb_dma_done_des_addr_chn_reg_t done_des_addr[3]; } ahb_dma_dev_t; extern ahb_dma_dev_t AHB_DMA; #ifndef __cplusplus -_Static_assert(sizeof(ahb_dma_dev_t) == 0x3dc, "Invalid size of ahb_dma_dev_t structure"); +_Static_assert(sizeof(ahb_dma_dev_t) == 0x428, "Invalid size of ahb_dma_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h b/components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h deleted file mode 100644 index 0f168341aa..0000000000 --- a/components/soc/esp32c5/register/soc/ahb_dma_struct_eco2.h +++ /dev/null @@ -1,3574 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Interrupt Registers */ -/** Type of in_int_raw_ch0 register - * Raw interrupt status of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_raw:1; - /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_raw:1; - /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_raw:1; - /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_raw:1; - /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_raw:1; - /** infifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_raw:1; - /** infifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_raw:1; - /** in_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_raw:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_raw_ch0_reg_t; - - -/** Group: Status Registers */ -/** Type of in_int_st_ch0 register - * Masked interrupt status of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_st:1; - /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_st:1; - /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_st:1; - /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_st:1; - /** in_dscr_empty_ch0_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_st:1; - /** infifo_ovf_ch0_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_st:1; - /** infifo_udf_ch0_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_st:1; - /** in_ahbinf_resp_err_ch0_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_st:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_st_ch0_reg_t; - -/** Type of in_int_ena_ch0 register - * Interrupt enable bits of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_ena:1; - /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_ena:1; - /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_ena:1; - /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_ena:1; - /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_ena:1; - /** infifo_ovf_ch0_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_ena:1; - /** infifo_udf_ch0_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_ena:1; - /** in_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_ena_ch0_reg_t; - -/** Type of in_int_clr_ch0 register - * Interrupt clear bits of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_clr:1; - /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_clr:1; - /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_clr:1; - /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_clr:1; - /** in_dscr_empty_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_clr:1; - /** infifo_ovf_ch0_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_clr:1; - /** infifo_udf_ch0_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_clr:1; - /** in_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_clr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_clr_ch0_reg_t; - -/** Type of in_int_raw_ch1 register - * Raw interrupt status of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_raw:1; - /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_raw:1; - /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_raw:1; - /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_raw:1; - /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_raw:1; - /** infifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_raw:1; - /** infifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_raw:1; - /** in_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_raw:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_raw_ch1_reg_t; - -/** Type of in_int_st_ch1 register - * Masked interrupt status of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_st:1; - /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_st:1; - /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_st:1; - /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_st:1; - /** in_dscr_empty_ch1_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_st:1; - /** infifo_ovf_ch1_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_st:1; - /** infifo_udf_ch1_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_st:1; - /** in_ahbinf_resp_err_ch1_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_st:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_st_ch1_reg_t; - -/** Type of in_int_ena_ch1 register - * Interrupt enable bits of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_ena:1; - /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_ena:1; - /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_ena:1; - /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_ena:1; - /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_ena:1; - /** infifo_ovf_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_ena:1; - /** infifo_udf_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_ena:1; - /** in_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_ena_ch1_reg_t; - -/** Type of in_int_clr_ch1 register - * Interrupt clear bits of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_clr:1; - /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_clr:1; - /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_clr:1; - /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_clr:1; - /** in_dscr_empty_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_clr:1; - /** infifo_ovf_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_clr:1; - /** infifo_udf_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_clr:1; - /** in_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_clr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_clr_ch1_reg_t; - -/** Type of in_int_raw_ch2 register - * Raw interrupt status of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_raw:1; - /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_raw:1; - /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_raw:1; - /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_raw:1; - /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_raw:1; - /** infifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_raw:1; - /** infifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_raw:1; - /** in_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_raw:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_raw_ch2_reg_t; - -/** Type of in_int_st_ch2 register - * Masked interrupt status of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_st:1; - /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_st:1; - /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_st:1; - /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_st:1; - /** in_dscr_empty_ch2_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_st:1; - /** infifo_ovf_ch2_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_st:1; - /** infifo_udf_ch2_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_st:1; - /** in_ahbinf_resp_err_ch2_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_st:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_st_ch2_reg_t; - -/** Type of in_int_ena_ch2 register - * Interrupt enable bits of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_ena:1; - /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_ena:1; - /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_ena:1; - /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_ena:1; - /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_ena:1; - /** infifo_ovf_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_ena:1; - /** infifo_udf_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_ena:1; - /** in_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_ena_ch2_reg_t; - -/** Type of in_int_clr_ch2 register - * Interrupt clear bits of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_clr:1; - /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_clr:1; - /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_clr:1; - /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_clr:1; - /** in_dscr_empty_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_clr:1; - /** infifo_ovf_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_clr:1; - /** infifo_udf_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_clr:1; - /** in_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_clr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_clr_ch2_reg_t; - -/** Type of out_int_raw_ch0 register - * //Raw interrupt status of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_raw:1; - /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_raw:1; - /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_raw:1; - /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_raw:1; - /** outfifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_raw:1; - /** outfifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_raw:1; - /** out_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_raw:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_raw_ch0_reg_t; - -/** Type of out_int_st_ch0 register - * Masked interrupt status of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_st:1; - /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_st:1; - /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_st:1; - /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_st:1; - /** outfifo_ovf_ch0_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_st:1; - /** outfifo_udf_ch0_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_st:1; - /** out_ahbinf_resp_err_ch0_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_st:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_st_ch0_reg_t; - -/** Type of out_int_ena_ch0 register - * Interrupt enable bits of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_ena:1; - /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_ena:1; - /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_ena:1; - /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_ena:1; - /** outfifo_ovf_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_ena:1; - /** outfifo_udf_ch0_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_ena:1; - /** out_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_ena:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_ena_ch0_reg_t; - -/** Type of out_int_clr_ch0 register - * Interrupt clear bits of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_clr:1; - /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_clr:1; - /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_clr:1; - /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_clr:1; - /** outfifo_ovf_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_clr:1; - /** outfifo_udf_ch0_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_clr:1; - /** out_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_clr:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_clr_ch0_reg_t; - -/** Type of out_int_raw_ch1 register - * //Raw interrupt status of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_raw:1; - /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_raw:1; - /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_raw:1; - /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_raw:1; - /** outfifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_raw:1; - /** outfifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_raw:1; - /** out_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_raw:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_raw_ch1_reg_t; - -/** Type of out_int_st_ch1 register - * Masked interrupt status of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_st:1; - /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_st:1; - /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_st:1; - /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_st:1; - /** outfifo_ovf_ch1_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_st:1; - /** outfifo_udf_ch1_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_st:1; - /** out_ahbinf_resp_err_ch1_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_st:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_st_ch1_reg_t; - -/** Type of out_int_ena_ch1 register - * Interrupt enable bits of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_ena:1; - /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_ena:1; - /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_ena:1; - /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_ena:1; - /** outfifo_ovf_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_ena:1; - /** outfifo_udf_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_ena:1; - /** out_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_ena:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_ena_ch1_reg_t; - -/** Type of out_int_clr_ch1 register - * Interrupt clear bits of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_clr:1; - /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_clr:1; - /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_clr:1; - /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_clr:1; - /** outfifo_ovf_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_clr:1; - /** outfifo_udf_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_clr:1; - /** out_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_clr:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_clr_ch1_reg_t; - -/** Type of out_int_raw_ch2 register - * //Raw interrupt status of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_raw:1; - /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_raw:1; - /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_raw:1; - /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_raw:1; - /** outfifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_raw:1; - /** outfifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_raw:1; - /** out_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_raw:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_raw_ch2_reg_t; - -/** Type of out_int_st_ch2 register - * Masked interrupt status of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_st:1; - /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_st:1; - /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_st:1; - /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_st:1; - /** outfifo_ovf_ch2_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_st:1; - /** outfifo_udf_ch2_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_st:1; - /** out_ahbinf_resp_err_ch2_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_st:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_st_ch2_reg_t; - -/** Type of out_int_ena_ch2 register - * Interrupt enable bits of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_ena:1; - /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_ena:1; - /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_ena:1; - /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_ena:1; - /** outfifo_ovf_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_ena:1; - /** outfifo_udf_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_ena:1; - /** out_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_ena:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_ena_ch2_reg_t; - -/** Type of out_int_clr_ch2 register - * Interrupt clear bits of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_clr:1; - /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_clr:1; - /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_clr:1; - /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_clr:1; - /** outfifo_ovf_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_clr:1; - /** outfifo_udf_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_clr:1; - /** out_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_clr:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_clr_ch2_reg_t; - -/** Type of ahb_test register - * only for test - */ -typedef union { - struct { - /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; - * reserved - */ - uint32_t ahb_testmode:3; - uint32_t reserved_3:1; - /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; - * reserved - */ - uint32_t ahb_testaddr:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_ahb_test_reg_t; - -/** Type of misc_conf register - * reserved - */ -typedef union { - struct { - /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM - */ - uint32_t ahbm_rst_inter:1; - uint32_t reserved_1:1; - /** arb_pri_dis : R/W; bitpos: [2]; default: 0; - * Configures whether to disable the fixed-priority channel arbitration. - * 0: Enable - * 1: Disable - */ - uint32_t arb_pri_dis:1; - /** clk_en : R/W; bitpos: [3]; default: 0; - * Configures clock gating. - * 0: Support clock only when the application writes registers. - * 1: Always force the clock on for registers. - */ - uint32_t clk_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_misc_conf_reg_t; - -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 2410220; - * Version control register - */ - uint32_t date:32; - }; - uint32_t val; -} ahb_dma_date_reg_t; - -/** Type of in_conf0_ch0 register - * Configuration register 0 of RX channel 0 - */ -typedef union { - struct { - /** in_rst_ch0 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. - */ - uint32_t in_rst_ch0:1; - /** in_loop_test_ch0 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_ch0:1; - /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 0 to read - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t indscr_burst_en_ch0:1; - uint32_t reserved_3:1; - /** mem_trans_en_ch0 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t mem_trans_en_ch0:1; - /** in_etm_en_ch0 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel0. - * 0: Disable - * 1: Enable - */ - uint32_t in_etm_en_ch0:1; - /** in_data_burst_mode_sel_ch0 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t in_data_burst_mode_sel_ch0:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_conf0_ch0_reg_t; - -/** Type of in_conf1_ch0 register - * Configuration register 1 of RX channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_ch0 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 0. - * 0: Disable - * 1: Enable - */ - uint32_t in_check_owner_ch0:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_conf1_ch0_reg_t; - -/** Type of infifo_status_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** infifo_full_ch0 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t infifo_full_ch0:1; - /** infifo_empty_ch0 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t infifo_empty_ch0:1; - uint32_t reserved_2:6; - /** infifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 0 - */ - uint32_t infifo_cnt_ch0:7; - uint32_t reserved_15:8; - /** in_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_ch0:1; - /** in_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_ch0:1; - /** in_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_ch0:1; - /** in_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_ch0:1; - /** in_buf_hungry_ch0 : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_ch0:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} ahb_dma_infifo_status_ch0_reg_t; - -/** Type of in_pop_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** infifo_rdata_ch0 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ - uint32_t infifo_rdata_ch0:12; - /** infifo_pop_ch0 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ - uint32_t infifo_pop_ch0:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_pop_ch0_reg_t; - -/** Type of in_link_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** inlink_auto_ret_ch0 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ - uint32_t inlink_auto_ret_ch0:1; - /** inlink_stop_ch0 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t inlink_stop_ch0:1; - /** inlink_start_ch0 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t inlink_start_ch0:1; - /** inlink_restart_ch0 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 0 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t inlink_restart_ch0:1; - /** inlink_park_ch0 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t inlink_park_ch0:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} ahb_dma_in_link_ch0_reg_t; - -/** Type of in_state_ch0 register - * Receive status of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; - * reserved - */ - uint32_t inlink_dscr_addr_ch0:18; - /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_ch0:2; - /** in_state_ch0 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ - uint32_t in_state_ch0:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_in_state_ch0_reg_t; - -/** Type of in_suc_eof_des_addr_ch0 register - * Receive descriptor address when EOF occurs on RX channel 0 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_suc_eof_des_addr_ch0_reg_t; - -/** Type of in_err_eof_des_addr_ch0 register - * Receive descriptor address when errors occur of RX channel 0 - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ - uint32_t in_err_eof_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_err_eof_des_addr_ch0_reg_t; - -/** Type of in_dscr_ch0 register - * Current receive descriptor address of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ - uint32_t inlink_dscr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_dscr_ch0_reg_t; - -/** Type of in_dscr_bf0_ch0 register - * The last receive descriptor address of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ - uint32_t inlink_dscr_bf0_ch0:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf0_ch0_reg_t; - -/** Type of in_dscr_bf1_ch0 register - * The second-to-last receive descriptor address of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ - uint32_t inlink_dscr_bf1_ch0:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf1_ch0_reg_t; - -/** Type of in_peri_ch0 register - * Priority register of RX channel 0 - */ -typedef union { - struct { - /** rx_pri_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 0.The larger of the value, the higher of the - * priority.. - */ - uint32_t rx_pri_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_peri_ch0_reg_t; - -/** Type of in_peri_sel_ch0 register - * Peripheral selection register of RX channel 0 - */ -typedef union { - struct { - /** peri_in_sel_ch0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 0. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ - uint32_t peri_in_sel_ch0:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_ch0_reg_t; - -/** Type of out_conf0_ch0 register - * Configuration register 0 of TX channel 0 - */ -typedef union { - struct { - /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ - uint32_t out_rst_ch0:1; - /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_ch0:1; - /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ - uint32_t out_auto_wrback_ch0:1; - /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ - uint32_t out_eof_mode_ch0:1; - /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 0 reading - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t outdscr_burst_en_ch0:1; - uint32_t reserved_5:1; - /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 0. - * 0: Disable - * 1: Enable - */ - uint32_t out_etm_en_ch0:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t out_data_burst_mode_sel_ch0:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_ch0_reg_t; - -/** Type of out_conf1_ch0 register - * Configuration register 1 of TX channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_ch0 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 0. - * 0: Disable - * 1: Enable - */ - uint32_t out_check_owner_ch0:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_out_conf1_ch0_reg_t; - -/** Type of outfifo_status_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** outfifo_full_ch0 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t outfifo_full_ch0:1; - /** outfifo_empty_ch0 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t outfifo_empty_ch0:1; - uint32_t reserved_2:6; - /** outfifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 0 - */ - uint32_t outfifo_cnt_ch0:7; - uint32_t reserved_15:8; - /** out_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_ch0:1; - /** out_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_ch0:1; - /** out_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_ch0:1; - /** out_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_ch0:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ahb_dma_outfifo_status_ch0_reg_t; - -/** Type of out_push_ch0 register - * Push control register of TX channel 0 - */ -typedef union { - struct { - /** outfifo_wdata_ch0 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ - uint32_t outfifo_wdata_ch0:9; - /** outfifo_push_ch0 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ - uint32_t outfifo_push_ch0:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_push_ch0_reg_t; - -/** Type of out_link_ch0 register - * Push control register of TX channel 0 - */ -typedef union { - struct { - /** outlink_stop_ch0 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t outlink_stop_ch0:1; - /** outlink_start_ch0 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t outlink_start_ch0:1; - /** outlink_restart_ch0 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 0 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t outlink_restart_ch0:1; - /** outlink_park_ch0 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t outlink_park_ch0:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_link_ch0_reg_t; - -/** Type of out_state_ch0 register - * Transmit status of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ - uint32_t outlink_dscr_addr_ch0:18; - /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_ch0:2; - /** out_state_ch0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_ch0:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_out_state_ch0_reg_t; - -/** Type of out_eof_des_addr_ch0 register - * Transmit descriptor address when EOF occurs on TX channel 0 - */ -typedef union { - struct { - /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_eof_des_addr_ch0_reg_t; - -/** Type of out_eof_bfr_des_addr_ch0 register - * The last transmit descriptor address when EOF occurs on TX channel 0 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_eof_bfr_des_addr_ch0_reg_t; - -/** Type of out_dscr_ch0 register - * Current transmit descriptor address of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ - uint32_t outlink_dscr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_dscr_ch0_reg_t; - -/** Type of out_dscr_bf0_ch0 register - * The last transmit descriptor address of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ - uint32_t outlink_dscr_bf0_ch0:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf0_ch0_reg_t; - -/** Type of out_dscr_bf1_ch0 register - * The second-to-last transmit descriptor address of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ - uint32_t outlink_dscr_bf1_ch0:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf1_ch0_reg_t; - -/** Type of out_peri_ch0 register - * Priority register of TX channel 0 - */ -typedef union { - struct { - /** tx_pri_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 0.The larger of the value, the higher of the - * priority.. - */ - uint32_t tx_pri_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_peri_ch0_reg_t; - -/** Type of out_peri_sel_ch0 register - * Peripheral selection register of TX channel 0 - */ -typedef union { - struct { - /** peri_out_sel_ch0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 0. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ - uint32_t peri_out_sel_ch0:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_out_peri_sel_ch0_reg_t; - -/** Type of in_conf0_ch1 register - * Configuration register 0 of RX channel 1 - */ -typedef union { - struct { - /** in_rst_ch1 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. - */ - uint32_t in_rst_ch1:1; - /** in_loop_test_ch1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_ch1:1; - /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 1 to read - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t indscr_burst_en_ch1:1; - uint32_t reserved_3:1; - /** mem_trans_en_ch1 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t mem_trans_en_ch1:1; - /** in_etm_en_ch1 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel1. - * 0: Disable - * 1: Enable - */ - uint32_t in_etm_en_ch1:1; - /** in_data_burst_mode_sel_ch1 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t in_data_burst_mode_sel_ch1:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_conf0_ch1_reg_t; - -/** Type of in_conf1_ch1 register - * Configuration register 1 of RX channel 1 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_ch1 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 1. - * 0: Disable - * 1: Enable - */ - uint32_t in_check_owner_ch1:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_conf1_ch1_reg_t; - -/** Type of infifo_status_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** infifo_full_ch1 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t infifo_full_ch1:1; - /** infifo_empty_ch1 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t infifo_empty_ch1:1; - uint32_t reserved_2:6; - /** infifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 1 - */ - uint32_t infifo_cnt_ch1:7; - uint32_t reserved_15:8; - /** in_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_ch1:1; - /** in_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_ch1:1; - /** in_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_ch1:1; - /** in_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_ch1:1; - /** in_buf_hungry_ch1 : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_ch1:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} ahb_dma_infifo_status_ch1_reg_t; - -/** Type of in_pop_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** infifo_rdata_ch1 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ - uint32_t infifo_rdata_ch1:12; - /** infifo_pop_ch1 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ - uint32_t infifo_pop_ch1:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_pop_ch1_reg_t; - -/** Type of in_link_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** inlink_auto_ret_ch1 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ - uint32_t inlink_auto_ret_ch1:1; - /** inlink_stop_ch1 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t inlink_stop_ch1:1; - /** inlink_start_ch1 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t inlink_start_ch1:1; - /** inlink_restart_ch1 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 1 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t inlink_restart_ch1:1; - /** inlink_park_ch1 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t inlink_park_ch1:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} ahb_dma_in_link_ch1_reg_t; - -/** Type of in_state_ch1 register - * Receive status of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * reserved - */ - uint32_t inlink_dscr_addr_ch1:18; - /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_ch1:2; - /** in_state_ch1 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ - uint32_t in_state_ch1:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_in_state_ch1_reg_t; - -/** Type of in_suc_eof_des_addr_ch1 register - * Receive descriptor address when EOF occurs on RX channel 1 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_suc_eof_des_addr_ch1_reg_t; - -/** Type of in_err_eof_des_addr_ch1 register - * Receive descriptor address when errors occur of RX channel 1 - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ - uint32_t in_err_eof_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_err_eof_des_addr_ch1_reg_t; - -/** Type of in_dscr_ch1 register - * Current receive descriptor address of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ - uint32_t inlink_dscr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_dscr_ch1_reg_t; - -/** Type of in_dscr_bf0_ch1 register - * The last receive descriptor address of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ - uint32_t inlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf0_ch1_reg_t; - -/** Type of in_dscr_bf1_ch1 register - * The second-to-last receive descriptor address of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ - uint32_t inlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf1_ch1_reg_t; - -/** Type of in_peri_ch1 register - * Priority register of RX channel 1 - */ -typedef union { - struct { - /** rx_pri_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 1.The larger of the value, the higher of the - * priority.. - */ - uint32_t rx_pri_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_peri_ch1_reg_t; - -/** Type of in_peri_sel_ch1 register - * Peripheral selection register of RX channel 1 - */ -typedef union { - struct { - /** peri_in_sel_ch1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 1. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ - uint32_t peri_in_sel_ch1:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_ch1_reg_t; - -/** Type of out_conf0_ch1 register - * Configuration register 0 of TX channel 1 - */ -typedef union { - struct { - /** out_rst_ch1 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ - uint32_t out_rst_ch1:1; - /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_ch1:1; - /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ - uint32_t out_auto_wrback_ch1:1; - /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ - uint32_t out_eof_mode_ch1:1; - /** outdscr_burst_en_ch1 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 1 reading - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t outdscr_burst_en_ch1:1; - uint32_t reserved_5:1; - /** out_etm_en_ch1 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 1. - * 0: Disable - * 1: Enable - */ - uint32_t out_etm_en_ch1:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_ch1 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t out_data_burst_mode_sel_ch1:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_ch1_reg_t; - -/** Type of out_conf1_ch1 register - * Configuration register 1 of TX channel 1 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_ch1 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 1. - * 0: Disable - * 1: Enable - */ - uint32_t out_check_owner_ch1:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_out_conf1_ch1_reg_t; - -/** Type of outfifo_status_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** outfifo_full_ch1 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t outfifo_full_ch1:1; - /** outfifo_empty_ch1 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t outfifo_empty_ch1:1; - uint32_t reserved_2:6; - /** outfifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 1 - */ - uint32_t outfifo_cnt_ch1:7; - uint32_t reserved_15:8; - /** out_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_ch1:1; - /** out_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_ch1:1; - /** out_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_ch1:1; - /** out_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_ch1:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ahb_dma_outfifo_status_ch1_reg_t; - -/** Type of out_push_ch1 register - * Push control register of TX channel 1 - */ -typedef union { - struct { - /** outfifo_wdata_ch1 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ - uint32_t outfifo_wdata_ch1:9; - /** outfifo_push_ch1 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ - uint32_t outfifo_push_ch1:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_push_ch1_reg_t; - -/** Type of out_link_ch1 register - * Push control register of TX channel 1 - */ -typedef union { - struct { - /** outlink_stop_ch1 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t outlink_stop_ch1:1; - /** outlink_start_ch1 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t outlink_start_ch1:1; - /** outlink_restart_ch1 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 1 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t outlink_restart_ch1:1; - /** outlink_park_ch1 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t outlink_park_ch1:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_link_ch1_reg_t; - -/** Type of out_state_ch1 register - * Transmit status of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ - uint32_t outlink_dscr_addr_ch1:18; - /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_ch1:2; - /** out_state_ch1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_ch1:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_out_state_ch1_reg_t; - -/** Type of out_eof_des_addr_ch1 register - * Transmit descriptor address when EOF occurs on TX channel 1 - */ -typedef union { - struct { - /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_eof_des_addr_ch1_reg_t; - -/** Type of out_eof_bfr_des_addr_ch1 register - * The last transmit descriptor address when EOF occurs on TX channel 1 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_eof_bfr_des_addr_ch1_reg_t; - -/** Type of out_dscr_ch1 register - * Current transmit descriptor address of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ - uint32_t outlink_dscr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_dscr_ch1_reg_t; - -/** Type of out_dscr_bf0_ch1 register - * The last transmit descriptor address of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ - uint32_t outlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf0_ch1_reg_t; - -/** Type of out_dscr_bf1_ch1 register - * The second-to-last transmit descriptor address of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ - uint32_t outlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf1_ch1_reg_t; - -/** Type of out_peri_ch1 register - * Priority register of TX channel 1 - */ -typedef union { - struct { - /** tx_pri_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 1.The larger of the value, the higher of the - * priority.. - */ - uint32_t tx_pri_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_peri_ch1_reg_t; - -/** Type of out_peri_sel_ch1 register - * Peripheral selection register of TX channel 1 - */ -typedef union { - struct { - /** peri_out_sel_ch1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 1. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ - uint32_t peri_out_sel_ch1:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_out_peri_sel_ch1_reg_t; - -/** Type of in_conf0_ch2 register - * Configuration register 0 of RX channel 2 - */ -typedef union { - struct { - /** in_rst_ch2 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer. - */ - uint32_t in_rst_ch2:1; - /** in_loop_test_ch2 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_ch2:1; - /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 2 to read - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t indscr_burst_en_ch2:1; - uint32_t reserved_3:1; - /** mem_trans_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t mem_trans_en_ch2:1; - /** in_etm_en_ch2 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel2. - * 0: Disable - * 1: Enable - */ - uint32_t in_etm_en_ch2:1; - /** in_data_burst_mode_sel_ch2 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel2. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t in_data_burst_mode_sel_ch2:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_conf0_ch2_reg_t; - -/** Type of in_conf1_ch2 register - * Configuration register 1 of RX channel 2 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_ch2 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 2. - * 0: Disable - * 1: Enable - */ - uint32_t in_check_owner_ch2:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_conf1_ch2_reg_t; - -/** Type of infifo_status_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** infifo_full_ch2 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t infifo_full_ch2:1; - /** infifo_empty_ch2 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t infifo_empty_ch2:1; - uint32_t reserved_2:6; - /** infifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 2 - */ - uint32_t infifo_cnt_ch2:7; - uint32_t reserved_15:8; - /** in_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_ch2:1; - /** in_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_ch2:1; - /** in_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_ch2:1; - /** in_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_ch2:1; - /** in_buf_hungry_ch2 : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_ch2:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} ahb_dma_infifo_status_ch2_reg_t; - -/** Type of in_pop_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** infifo_rdata_ch2 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ - uint32_t infifo_rdata_ch2:12; - /** infifo_pop_ch2 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ - uint32_t infifo_pop_ch2:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_pop_ch2_reg_t; - -/** Type of in_link_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** inlink_auto_ret_ch2 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ - uint32_t inlink_auto_ret_ch2:1; - /** inlink_stop_ch2 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 2 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t inlink_stop_ch2:1; - /** inlink_start_ch2 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 2 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t inlink_start_ch2:1; - /** inlink_restart_ch2 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 2 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t inlink_restart_ch2:1; - /** inlink_park_ch2 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t inlink_park_ch2:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} ahb_dma_in_link_ch2_reg_t; - -/** Type of in_state_ch2 register - * Receive status of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * reserved - */ - uint32_t inlink_dscr_addr_ch2:18; - /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_ch2:2; - /** in_state_ch2 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ - uint32_t in_state_ch2:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_in_state_ch2_reg_t; - -/** Type of in_suc_eof_des_addr_ch2 register - * Receive descriptor address when EOF occurs on RX channel 2 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_suc_eof_des_addr_ch2_reg_t; - -/** Type of in_err_eof_des_addr_ch2 register - * Receive descriptor address when errors occur of RX channel 2 - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ - uint32_t in_err_eof_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_err_eof_des_addr_ch2_reg_t; - -/** Type of in_dscr_ch2 register - * Current receive descriptor address of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ - uint32_t inlink_dscr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_dscr_ch2_reg_t; - -/** Type of in_dscr_bf0_ch2 register - * The last receive descriptor address of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ - uint32_t inlink_dscr_bf0_ch2:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf0_ch2_reg_t; - -/** Type of in_dscr_bf1_ch2 register - * The second-to-last receive descriptor address of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ - uint32_t inlink_dscr_bf1_ch2:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf1_ch2_reg_t; - -/** Type of in_peri_ch2 register - * Priority register of RX channel 2 - */ -typedef union { - struct { - /** rx_pri_ch2 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 2.The larger of the value, the higher of the - * priority.. - */ - uint32_t rx_pri_ch2:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_peri_ch2_reg_t; - -/** Type of in_peri_sel_ch2 register - * Peripheral selection register of RX channel 2 - */ -typedef union { - struct { - /** peri_in_sel_ch2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 2. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - */ - uint32_t peri_in_sel_ch2:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_ch2_reg_t; - -/** Type of out_conf0_ch2 register - * Configuration register 0 of TX channel 2 - */ -typedef union { - struct { - /** out_rst_ch2 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ - uint32_t out_rst_ch2:1; - /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_ch2:1; - /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ - uint32_t out_auto_wrback_ch2:1; - /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 2 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 2 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ - uint32_t out_eof_mode_ch2:1; - /** outdscr_burst_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 2 reading - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t outdscr_burst_en_ch2:1; - uint32_t reserved_5:1; - /** out_etm_en_ch2 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 2. - * 0: Disable - * 1: Enable - */ - uint32_t out_etm_en_ch2:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_ch2 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel2. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t out_data_burst_mode_sel_ch2:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_ch2_reg_t; - -/** Type of out_conf1_ch2 register - * Configuration register 1 of TX channel 2 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_ch2 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 2. - * 0: Disable - * 1: Enable - */ - uint32_t out_check_owner_ch2:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_out_conf1_ch2_reg_t; - -/** Type of outfifo_status_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** outfifo_full_ch2 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t outfifo_full_ch2:1; - /** outfifo_empty_ch2 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t outfifo_empty_ch2:1; - uint32_t reserved_2:6; - /** outfifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 2 - */ - uint32_t outfifo_cnt_ch2:7; - uint32_t reserved_15:8; - /** out_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_ch2:1; - /** out_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_ch2:1; - /** out_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_ch2:1; - /** out_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_ch2:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ahb_dma_outfifo_status_ch2_reg_t; - -/** Type of out_push_ch2 register - * Push control register of TX channel 2 - */ -typedef union { - struct { - /** outfifo_wdata_ch2 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ - uint32_t outfifo_wdata_ch2:9; - /** outfifo_push_ch2 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ - uint32_t outfifo_push_ch2:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_push_ch2_reg_t; - -/** Type of out_link_ch2 register - * Push control register of TX channel 2 - */ -typedef union { - struct { - /** outlink_stop_ch2 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 2 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t outlink_stop_ch2:1; - /** outlink_start_ch2 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 2 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t outlink_start_ch2:1; - /** outlink_restart_ch2 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 2 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t outlink_restart_ch2:1; - /** outlink_park_ch2 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t outlink_park_ch2:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_link_ch2_reg_t; - -/** Type of out_state_ch2 register - * Transmit status of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ - uint32_t outlink_dscr_addr_ch2:18; - /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_ch2:2; - /** out_state_ch2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_ch2:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_out_state_ch2_reg_t; - -/** Type of out_eof_des_addr_ch2 register - * Transmit descriptor address when EOF occurs on TX channel 2 - */ -typedef union { - struct { - /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_eof_des_addr_ch2_reg_t; - -/** Type of out_eof_bfr_des_addr_ch2 register - * The last transmit descriptor address when EOF occurs on TX channel 2 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_eof_bfr_des_addr_ch2_reg_t; - -/** Type of out_dscr_ch2 register - * Current transmit descriptor address of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ - uint32_t outlink_dscr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_dscr_ch2_reg_t; - -/** Type of out_dscr_bf0_ch2 register - * The last transmit descriptor address of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ - uint32_t outlink_dscr_bf0_ch2:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf0_ch2_reg_t; - -/** Type of out_dscr_bf1_ch2 register - * The second-to-last transmit descriptor address of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ - uint32_t outlink_dscr_bf1_ch2:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf1_ch2_reg_t; - -/** Type of out_peri_ch2 register - * Priority register of TX channel 2 - */ -typedef union { - struct { - /** tx_pri_ch2 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 2.The larger of the value, the higher of the - * priority.. - */ - uint32_t tx_pri_ch2:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_peri_ch2_reg_t; - -/** Type of out_peri_sel_ch2 register - * Peripheral selection register of TX channel 2 - */ -typedef union { - struct { - /** peri_out_sel_ch2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 2. - * 0: Dummy - * 1: SPI2 - * 2: UHCI0 - * 3: I2S0 - * 4: Dummy - * 5: Dummy - * 6: AES - * 7: SHA - * 8: ADC_DAC - * 9: PARL_IO - * 10: Dummy - * 11~15: Dummy - * \ - */ - uint32_t peri_out_sel_ch2:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_out_peri_sel_ch2_reg_t; - -/** Type of tx_ch_arb_weight_ch0 register - * TX channel 0 arbitration weight configuration register - */ -typedef union { - struct { - /** tx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel0 - */ - uint32_t tx_arb_weight_value_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_tx_ch_arb_weight_ch0_reg_t; - -/** Type of tx_arb_weight_opt_dir_ch0 register - * TX channel 0 weight arbitration optimization enable register - */ -typedef union { - struct { - /** tx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t tx_arb_weight_opt_dis_ch0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t; - -/** Type of tx_ch_arb_weight_ch1 register - * TX channel 1 arbitration weight configuration register - */ -typedef union { - struct { - /** tx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel1 - */ - uint32_t tx_arb_weight_value_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_tx_ch_arb_weight_ch1_reg_t; - -/** Type of tx_arb_weight_opt_dir_ch1 register - * TX channel 1 weight arbitration optimization enable register - */ -typedef union { - struct { - /** tx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t tx_arb_weight_opt_dis_ch1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t; - -/** Type of tx_ch_arb_weight_ch2 register - * TX channel 2 arbitration weight configuration register - */ -typedef union { - struct { - /** tx_arb_weight_value_ch2 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel2 - */ - uint32_t tx_arb_weight_value_ch2:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_tx_ch_arb_weight_ch2_reg_t; - -/** Type of tx_arb_weight_opt_dir_ch2 register - * TX channel 2 weight arbitration optimization enable register - */ -typedef union { - struct { - /** tx_arb_weight_opt_dis_ch2 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t tx_arb_weight_opt_dis_ch2:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t; - -/** Type of rx_ch_arb_weight_ch0 register - * RX channel 0 arbitration weight configuration register - */ -typedef union { - struct { - /** rx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel0 - */ - uint32_t rx_arb_weight_value_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_rx_ch_arb_weight_ch0_reg_t; - -/** Type of rx_arb_weight_opt_dir_ch0 register - * RX channel 0 weight arbitration optimization enable register - */ -typedef union { - struct { - /** rx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rx_arb_weight_opt_dis_ch0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t; - -/** Type of rx_ch_arb_weight_ch1 register - * RX channel 1 arbitration weight configuration register - */ -typedef union { - struct { - /** rx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel1 - */ - uint32_t rx_arb_weight_value_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_rx_ch_arb_weight_ch1_reg_t; - -/** Type of rx_arb_weight_opt_dir_ch1 register - * RX channel 1 weight arbitration optimization enable register - */ -typedef union { - struct { - /** rx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rx_arb_weight_opt_dis_ch1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t; - -/** Type of in_link_addr_ch0 register - * Link list descriptor address configuration of RX channel 0 - */ -typedef union { - struct { - /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ - uint32_t inlink_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_link_addr_ch0_reg_t; - -/** Type of in_link_addr_ch1 register - * Link list descriptor address configuration of RX channel 1 - */ -typedef union { - struct { - /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ - uint32_t inlink_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_link_addr_ch1_reg_t; - -/** Type of in_link_addr_ch2 register - * Link list descriptor address configuration of RX channel 2 - */ -typedef union { - struct { - /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ - uint32_t inlink_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_link_addr_ch2_reg_t; - -/** Type of out_link_addr_ch0 register - * Link list descriptor address configuration of TX channel 0 - */ -typedef union { - struct { - /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t outlink_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_link_addr_ch0_reg_t; - -/** Type of out_link_addr_ch1 register - * Link list descriptor address configuration of TX channel 1 - */ -typedef union { - struct { - /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t outlink_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_link_addr_ch1_reg_t; - -/** Type of out_link_addr_ch2 register - * Link list descriptor address configuration of TX channel 2 - */ -typedef union { - struct { - /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t outlink_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_link_addr_ch2_reg_t; - -/** Type of intr_mem_start_addr register - * Accessible address space start address configuration register - */ -typedef union { - struct { - /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0; - * Accessible address space start address configuration register - */ - uint32_t access_intr_mem_start_addr:32; - }; - uint32_t val; -} ahb_dma_intr_mem_start_addr_reg_t; - -/** Type of intr_mem_end_addr register - * Accessible address space end address configuration register - */ -typedef union { - struct { - /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the end address of accessible address space. - */ - uint32_t access_intr_mem_end_addr:32; - }; - uint32_t val; -} ahb_dma_intr_mem_end_addr_reg_t; - -/** Type of arb_timeout register - * TX arbitration timeout configuration register - */ -typedef union { - struct { - /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot. Measurement unit: AHB bus clock cycle. - */ - uint32_t arb_timeout_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} ahb_dma_arb_timeout_reg_t; - -/** Type of weight_en register - * TX weight arbitration enable register - */ -typedef union { - struct { - /** weight_en : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration. - * 0: Disable - * 1: Enable - */ - uint32_t weight_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_weight_en_reg_t; - -/** Type of module_clk_en register - * Module clock force on register - */ -typedef union { - struct { - /** ahb_apb_sync_clk_en : R/W; bitpos: [2:0]; default: 7; - * Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n: - * 0 : Not force on ahb_apb_sync n clock - * 1 : Force on ahb_apb_sync n clock - */ - uint32_t ahb_apb_sync_clk_en:3; - /** out_dscr_clk_en : R/W; bitpos: [5:3]; default: 7; - * Configures whether to force on out_dscr 2~0 module clock. For bit n: - * 0 : Not force on out_dscr n clock - * 1 : Force on out_dscr n clock - */ - uint32_t out_dscr_clk_en:3; - /** out_ctrl_clk_en : R/W; bitpos: [8:6]; default: 7; - * Configures whether to force on out_ctrl 2~0 module clock. For bit n: - * 0 : Not force on out_ctrl n clock - * 1 : Force on out_ctrl n clock - */ - uint32_t out_ctrl_clk_en:3; - /** in_dscr_clk_en : R/W; bitpos: [11:9]; default: 7; - * Configures whether to force on in_dscr 2~0 module clock. For bit n: - * 0 : Not force on in_dscr n clock - * 1 : Force on in_dscr n clock - */ - uint32_t in_dscr_clk_en:3; - /** in_ctrl_clk_en : R/W; bitpos: [14:12]; default: 7; - * Configures whether to force on in_ctrl 2~0 module clock. For bit n: - * 0 : Not force on in_ctrl n clock - * 1 : Force on in_ctrl n clock - */ - uint32_t in_ctrl_clk_en:3; - uint32_t reserved_15:12; - /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0; - * Configures whether to force on cmd_arb module clock. - * 0 : Not force on cmd_arb clock - * 1 : Force on cmd_arb clock - */ - uint32_t cmd_arb_clk_en:1; - /** ahbinf_clk_en : R/W; bitpos: [28]; default: 0; - * Configures whether to force on ahbinf module clock. - * 0 : Not force on ahbinf clock - * 1 : Force on ahbinf clock - */ - uint32_t ahbinf_clk_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} ahb_dma_module_clk_en_reg_t; - -/** Type of ahbinf_resp_err_status0 register - * AHB response error status 0 register - */ -typedef union { - struct { - /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0; - * Represents the address of the AHB response error. - */ - uint32_t ahbinf_resp_err_addr:32; - }; - uint32_t val; -} ahb_dma_ahbinf_resp_err_status0_reg_t; - -/** Type of ahbinf_resp_err_status1 register - * AHB response error status 1 register - */ -typedef union { - struct { - /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0; - * Represents the AHB response error is write request. - */ - uint32_t ahbinf_resp_err_wr:1; - /** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15; - * Represents the AHB response error request id. - */ - uint32_t ahbinf_resp_err_id:4; - /** ahbinf_resp_err_ch_id : RO; bitpos: [7:5]; default: 0; - * Represents the AHB response error request channel id.bit[2]=1:TX channel. - * bit[2]=0:RX channel. - */ - uint32_t ahbinf_resp_err_ch_id:3; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_ahbinf_resp_err_status1_reg_t; - -/** Type of in_done_des_addr_ch0 register - * RX_done Inlink descriptor address of RX channel 0 - */ -typedef union { - struct { - /** in_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ - uint32_t in_done_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_done_des_addr_ch0_reg_t; - -/** Type of out_done_des_addr_ch0 register - * TX done outlink descriptor address of TX channel 0 - */ -typedef union { - struct { - /** out_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ - uint32_t out_done_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_done_des_addr_ch0_reg_t; - -/** Type of in_done_des_addr_ch1 register - * RX_done Inlink descriptor address of RX channel 1 - */ -typedef union { - struct { - /** in_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ - uint32_t in_done_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_done_des_addr_ch1_reg_t; - -/** Type of out_done_des_addr_ch1 register - * TX done outlink descriptor address of TX channel 1 - */ -typedef union { - struct { - /** out_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ - uint32_t out_done_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_done_des_addr_ch1_reg_t; - -/** Type of in_done_des_addr_ch2 register - * RX_done Inlink descriptor address of RX channel 2 - */ -typedef union { - struct { - /** in_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ - uint32_t in_done_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_done_des_addr_ch2_reg_t; - -/** Type of out_done_des_addr_ch2 register - * TX done outlink descriptor address of TX channel 2 - */ -typedef union { - struct { - /** out_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ - uint32_t out_done_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_done_des_addr_ch2_reg_t; - - -/** Group: Configuration Registers */ -/** Type of rx_ch_arb_weigh_chn register - * RX channel 2 arbitration weight configuration register - */ -typedef union { - struct { - /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channeln - */ - uint32_t rx_ch_arb_weigh_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_rx_ch_arb_weigh_chn_reg_t; - -/** Type of rx_arb_weigh_opt_dir_chn register - * RX channel 2 weight arbitration optimization enable register - */ -typedef union { - struct { - /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rx_arb_weigh_opt_dir_chn:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t; - -/** Type of arb_timeout_tx register - * TX arbitration timeout configuration register - */ -typedef union { - struct { - /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. - */ - uint32_t arb_timeout_tx:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} ahb_dma_arb_timeout_tx_reg_t; - -/** Type of arb_timeout_rx register - * RX arbitration timeout configuration register - */ -typedef union { - struct { - /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. - */ - uint32_t arb_timeout_rx:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} ahb_dma_arb_timeout_rx_reg_t; - -/** Type of weight_en_tx register - * TX weight arbitration enable register - */ -typedef union { - struct { - /** weight_en_tx : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for TX. - * 0: Disable - * 1: Enable - */ - uint32_t weight_en_tx:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_weight_en_tx_reg_t; - -/** Type of weight_en_rx register - * RX weight arbitration enable register - */ -typedef union { - struct { - /** weight_en_rx : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for RX. - * 0: Disable - * 1: Enable - */ - uint32_t weight_en_rx:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_weight_en_rx_reg_t; - - -typedef struct { - volatile ahb_dma_in_int_raw_ch0_reg_t in_int_raw_ch0; - volatile ahb_dma_in_int_st_ch0_reg_t in_int_st_ch0; - volatile ahb_dma_in_int_ena_ch0_reg_t in_int_ena_ch0; - volatile ahb_dma_in_int_clr_ch0_reg_t in_int_clr_ch0; - volatile ahb_dma_in_int_raw_ch1_reg_t in_int_raw_ch1; - volatile ahb_dma_in_int_st_ch1_reg_t in_int_st_ch1; - volatile ahb_dma_in_int_ena_ch1_reg_t in_int_ena_ch1; - volatile ahb_dma_in_int_clr_ch1_reg_t in_int_clr_ch1; - volatile ahb_dma_in_int_raw_ch2_reg_t in_int_raw_ch2; - volatile ahb_dma_in_int_st_ch2_reg_t in_int_st_ch2; - volatile ahb_dma_in_int_ena_ch2_reg_t in_int_ena_ch2; - volatile ahb_dma_in_int_clr_ch2_reg_t in_int_clr_ch2; - volatile ahb_dma_out_int_raw_ch0_reg_t out_int_raw_ch0; - volatile ahb_dma_out_int_st_ch0_reg_t out_int_st_ch0; - volatile ahb_dma_out_int_ena_ch0_reg_t out_int_ena_ch0; - volatile ahb_dma_out_int_clr_ch0_reg_t out_int_clr_ch0; - volatile ahb_dma_out_int_raw_ch1_reg_t out_int_raw_ch1; - volatile ahb_dma_out_int_st_ch1_reg_t out_int_st_ch1; - volatile ahb_dma_out_int_ena_ch1_reg_t out_int_ena_ch1; - volatile ahb_dma_out_int_clr_ch1_reg_t out_int_clr_ch1; - volatile ahb_dma_out_int_raw_ch2_reg_t out_int_raw_ch2; - volatile ahb_dma_out_int_st_ch2_reg_t out_int_st_ch2; - volatile ahb_dma_out_int_ena_ch2_reg_t out_int_ena_ch2; - volatile ahb_dma_out_int_clr_ch2_reg_t out_int_clr_ch2; - volatile ahb_dma_ahb_test_reg_t ahb_test; - volatile ahb_dma_misc_conf_reg_t misc_conf; - volatile ahb_dma_date_reg_t date; - uint32_t reserved_06c; - volatile ahb_dma_in_conf0_ch0_reg_t in_conf0_ch0; - volatile ahb_dma_in_conf1_ch0_reg_t in_conf1_ch0; - volatile ahb_dma_infifo_status_ch0_reg_t infifo_status_ch0; - volatile ahb_dma_in_pop_ch0_reg_t in_pop_ch0; - volatile ahb_dma_in_link_ch0_reg_t in_link_ch0; - volatile ahb_dma_in_state_ch0_reg_t in_state_ch0; - volatile ahb_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0; - volatile ahb_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0; - volatile ahb_dma_in_dscr_ch0_reg_t in_dscr_ch0; - volatile ahb_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0; - volatile ahb_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0; - volatile ahb_dma_in_peri_ch0_reg_t in_peri_ch0; - volatile ahb_dma_in_peri_sel_ch0_reg_t in_peri_sel_ch0; - uint32_t reserved_0a4[11]; - volatile ahb_dma_out_conf0_ch0_reg_t out_conf0_ch0; - volatile ahb_dma_out_conf1_ch0_reg_t out_conf1_ch0; - volatile ahb_dma_outfifo_status_ch0_reg_t outfifo_status_ch0; - volatile ahb_dma_out_push_ch0_reg_t out_push_ch0; - volatile ahb_dma_out_link_ch0_reg_t out_link_ch0; - volatile ahb_dma_out_state_ch0_reg_t out_state_ch0; - volatile ahb_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0; - volatile ahb_dma_out_eof_bfr_des_addr_ch0_reg_t out_eof_bfr_des_addr_ch0; - volatile ahb_dma_out_dscr_ch0_reg_t out_dscr_ch0; - volatile ahb_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0; - volatile ahb_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0; - volatile ahb_dma_out_peri_ch0_reg_t out_peri_ch0; - volatile ahb_dma_out_peri_sel_ch0_reg_t out_peri_sel_ch0; - uint32_t reserved_104[11]; - volatile ahb_dma_in_conf0_ch1_reg_t in_conf0_ch1; - volatile ahb_dma_in_conf1_ch1_reg_t in_conf1_ch1; - volatile ahb_dma_infifo_status_ch1_reg_t infifo_status_ch1; - volatile ahb_dma_in_pop_ch1_reg_t in_pop_ch1; - volatile ahb_dma_in_link_ch1_reg_t in_link_ch1; - volatile ahb_dma_in_state_ch1_reg_t in_state_ch1; - volatile ahb_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1; - volatile ahb_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1; - volatile ahb_dma_in_dscr_ch1_reg_t in_dscr_ch1; - volatile ahb_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1; - volatile ahb_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1; - volatile ahb_dma_in_peri_ch1_reg_t in_peri_ch1; - volatile ahb_dma_in_peri_sel_ch1_reg_t in_peri_sel_ch1; - uint32_t reserved_164[11]; - volatile ahb_dma_out_conf0_ch1_reg_t out_conf0_ch1; - volatile ahb_dma_out_conf1_ch1_reg_t out_conf1_ch1; - volatile ahb_dma_outfifo_status_ch1_reg_t outfifo_status_ch1; - volatile ahb_dma_out_push_ch1_reg_t out_push_ch1; - volatile ahb_dma_out_link_ch1_reg_t out_link_ch1; - volatile ahb_dma_out_state_ch1_reg_t out_state_ch1; - volatile ahb_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1; - volatile ahb_dma_out_eof_bfr_des_addr_ch1_reg_t out_eof_bfr_des_addr_ch1; - volatile ahb_dma_out_dscr_ch1_reg_t out_dscr_ch1; - volatile ahb_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1; - volatile ahb_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1; - volatile ahb_dma_out_peri_ch1_reg_t out_peri_ch1; - volatile ahb_dma_out_peri_sel_ch1_reg_t out_peri_sel_ch1; - uint32_t reserved_1c4[11]; - volatile ahb_dma_in_conf0_ch2_reg_t in_conf0_ch2; - volatile ahb_dma_in_conf1_ch2_reg_t in_conf1_ch2; - volatile ahb_dma_infifo_status_ch2_reg_t infifo_status_ch2; - volatile ahb_dma_in_pop_ch2_reg_t in_pop_ch2; - volatile ahb_dma_in_link_ch2_reg_t in_link_ch2; - volatile ahb_dma_in_state_ch2_reg_t in_state_ch2; - volatile ahb_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2; - volatile ahb_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2; - volatile ahb_dma_in_dscr_ch2_reg_t in_dscr_ch2; - volatile ahb_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2; - volatile ahb_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2; - volatile ahb_dma_in_peri_ch2_reg_t in_peri_ch2; - volatile ahb_dma_in_peri_sel_ch2_reg_t in_peri_sel_ch2; - uint32_t reserved_224[11]; - volatile ahb_dma_out_conf0_ch2_reg_t out_conf0_ch2; - volatile ahb_dma_out_conf1_ch2_reg_t out_conf1_ch2; - volatile ahb_dma_outfifo_status_ch2_reg_t outfifo_status_ch2; - volatile ahb_dma_out_push_ch2_reg_t out_push_ch2; - volatile ahb_dma_out_link_ch2_reg_t out_link_ch2; - volatile ahb_dma_out_state_ch2_reg_t out_state_ch2; - volatile ahb_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2; - volatile ahb_dma_out_eof_bfr_des_addr_ch2_reg_t out_eof_bfr_des_addr_ch2; - volatile ahb_dma_out_dscr_ch2_reg_t out_dscr_ch2; - volatile ahb_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2; - volatile ahb_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2; - volatile ahb_dma_out_peri_ch2_reg_t out_peri_ch2; - volatile ahb_dma_out_peri_sel_ch2_reg_t out_peri_sel_ch2; - uint32_t reserved_284[22]; - volatile ahb_dma_tx_ch_arb_weight_ch0_reg_t tx_ch_arb_weight_ch0; - volatile ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t tx_arb_weight_opt_dir_ch0; - uint32_t reserved_2e4[8]; - volatile ahb_dma_tx_ch_arb_weight_ch1_reg_t tx_ch_arb_weight_ch1; - volatile ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t tx_arb_weight_opt_dir_ch1; - uint32_t reserved_30c[8]; - volatile ahb_dma_tx_ch_arb_weight_ch2_reg_t tx_ch_arb_weight_ch2; - volatile ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t tx_arb_weight_opt_dir_ch2; - uint32_t reserved_334[8]; - volatile ahb_dma_rx_ch_arb_weight_ch0_reg_t rx_ch_arb_weight_ch0; - volatile ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t rx_arb_weight_opt_dir_ch0; - uint32_t reserved_35c[8]; - volatile ahb_dma_rx_ch_arb_weight_ch1_reg_t rx_ch_arb_weight_ch1; - volatile ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t rx_arb_weight_opt_dir_ch1; - uint32_t reserved_384[8]; - volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch2; - volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch2; - volatile ahb_dma_in_link_addr_ch0_reg_t in_link_addr_ch0; - volatile ahb_dma_in_link_addr_ch1_reg_t in_link_addr_ch1; - volatile ahb_dma_in_link_addr_ch2_reg_t in_link_addr_ch2; - volatile ahb_dma_out_link_addr_ch0_reg_t out_link_addr_ch0; - volatile ahb_dma_out_link_addr_ch1_reg_t out_link_addr_ch1; - volatile ahb_dma_out_link_addr_ch2_reg_t out_link_addr_ch2; - volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr; - volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr; - volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx; - volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx; - volatile ahb_dma_weight_en_tx_reg_t weight_en_tx; - volatile ahb_dma_weight_en_rx_reg_t weight_en_rx; - volatile ahb_dma_arb_timeout_reg_t arb_timeout; - uint32_t reserved_3e0[8]; - volatile ahb_dma_weight_en_reg_t weight_en; - volatile ahb_dma_module_clk_en_reg_t module_clk_en; - volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0; - volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1; - volatile ahb_dma_in_done_des_addr_ch0_reg_t in_done_des_addr_ch0; - volatile ahb_dma_out_done_des_addr_ch0_reg_t out_done_des_addr_ch0; - volatile ahb_dma_in_done_des_addr_ch1_reg_t in_done_des_addr_ch1; - volatile ahb_dma_out_done_des_addr_ch1_reg_t out_done_des_addr_ch1; - volatile ahb_dma_in_done_des_addr_ch2_reg_t in_done_des_addr_ch2; - volatile ahb_dma_out_done_des_addr_ch2_reg_t out_done_des_addr_ch2; -} ahb_dma_dev_t; - -extern ahb_dma_dev_t AHB_DMA; - -#ifndef __cplusplus -_Static_assert(sizeof(ahb_dma_dev_t) == 0x428, "Invalid size of ahb_dma_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif