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Merge branch 'bugfix/esp32s2_ldscripts' into 'master'
esp32s2: LD script fixes/improvements and re-enable SystemView examples Closes IDF-1357, IDF-1354, and IDF-1346 See merge request espressif/esp-idf!7431
This commit is contained in:
Ivan Grokhotkov
@@ -244,6 +244,10 @@ menu "ESP32S2-specific"
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bool
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default "n"
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config ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
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bool
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default "n"
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config ESP32S2_TRAX
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bool "Use TRAX tracing feature"
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default "n"
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@@ -26,16 +26,16 @@
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#define RAM_IRAM_START 0x40020000
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#define RAM_DRAM_START 0x3FFB0000
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#define DATA_RAM_END 0x3FFF0000 /* start address of bootloader */
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#define DATA_RAM_END 0x3FFE4000 /* 2nd stage bootloader iram_loader_seg starts at block 15 */
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#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define IRAM_SIZE 0x18000
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#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE \
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+ IRAM_SIZE)
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#define DRAM_SIZE DATA_RAM_END - DRAM_ORG
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG
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MEMORY
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{
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@@ -44,8 +44,9 @@ MEMORY
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for CPU.*/
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iram0_0_seg (RX) : org = IRAM_ORG, len = IRAM_SIZE
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iram0_0_seg (RX) : org = IRAM_ORG, len = I_D_RAM_SIZE
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Even though the segment name is iram, it is actually mapped to flash
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*/
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iram0_2_seg (RX) : org = 0x40080020, len = 0x780000-0x20
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@@ -57,15 +58,18 @@ MEMORY
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header. Setting this offset makes it simple to meet the flash cache MMU's
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constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
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dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM_SIZE
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dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F000020, len = 0x3f0000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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@@ -84,11 +88,7 @@ MEMORY
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_static_data_end = _bss_end;
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/* Heap ends at top of dram0_0_seg
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ROM data mappings start from 0x3FFFC000,
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0x3FFF4000...0x3FFFC000 can be reserved for trace memory mapping
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*/
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_heap_end = 0x3FFFC000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM;
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_heap_end = 0x40000000;
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_data_seg_org = ORIGIN(rtc_data_seg);
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@@ -101,3 +101,15 @@ REGION_ALIAS("rtc_data_location", rtc_slow_seg );
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#else
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REGION_ALIAS("rtc_data_location", rtc_data_seg );
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#endif
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_code_seg", iram0_2_seg);
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#else
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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#else
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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@@ -164,8 +164,10 @@ SECTIONS
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_iram_end = ABSOLUTE(.);
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} > iram0_0_seg
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ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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"IRAM0 segment data does not fit.")
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.dram0_reserved_for_iram (NOLOAD):
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{
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. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
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} > dram0_0_seg
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.dram0.data :
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{
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@@ -243,9 +245,6 @@ SECTIONS
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_heap_start = ABSOLUTE(.);
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} > dram0_0_seg
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ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
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"DRAM segment data does not fit.")
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/* When modifying the alignment, update tls_section_alignment in pxPortInitialiseStack */
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.flash.rodata : ALIGN(0x10)
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{
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@@ -307,7 +306,7 @@ SECTIONS
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*(.tbss.*)
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_thread_local_end = ABSOLUTE(.);
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. = ALIGN(4);
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} >drom0_0_seg
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} >default_rodata_seg
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.flash.text :
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{
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@@ -329,5 +328,25 @@ SECTIONS
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the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} >iram0_2_seg
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} >default_code_seg
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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. = ALIGN (4);
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_iram_end = ABSOLUTE(.);
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} > iram0_0_seg
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/* Marks the end of data, bss and possibly rodata */
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.dram0.heap_start (NOLOAD) :
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{
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. = ALIGN (8);
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_heap_start = ABSOLUTE(.);
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} > dram0_0_seg
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}
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ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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"IRAM0 segment data does not fit.")
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ASSERT(((_heap_start - _data_start) <= LENGTH(dram0_0_seg)),
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"DRAM segment data does not fit.")
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