From 5056892b9bf6d493958c4bf9ed14cd8d67796a7c Mon Sep 17 00:00:00 2001
From: Xia Xiaotian <xiaxiaotian@espressif.com>
Date: Tue, 19 Jan 2021 19:36:06 +0800
Subject: [PATCH] esp_wifi: store PHY digital registers before disabling PHY
 and load           them after enabling PHY

---
 components/esp_wifi/include/phy.h           | 10 +++++++++
 components/esp_wifi/src/phy_init.c          | 24 +++++++++++++++++++++
 components/soc/esp32/include/soc/soc_caps.h |  4 ++++
 3 files changed, 38 insertions(+)

diff --git a/components/esp_wifi/include/phy.h b/components/esp_wifi/include/phy.h
index c1e4639369..55746ffecb 100644
--- a/components/esp_wifi/include/phy.h
+++ b/components/esp_wifi/include/phy.h
@@ -69,6 +69,16 @@ void phy_wakeup_init(void);
  */
 void phy_close_rf(void);
 
+/**
+ * @brief Store and load PHY digital registers.
+ *
+ * @param     backup_en  if backup_en is true, store PHY digital registers to memory. Otherwise load PHY digital registers from memory
+ * @param     mem_addr   Memory address to store and load PHY digital registers
+ *
+ * @return    memory size
+ */
+uint8_t phy_dig_reg_backup(bool backup_en, uint32_t *mem_addr);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_wifi/src/phy_init.c b/components/esp_wifi/src/phy_init.c
index 8b8052a313..4a1af3fa9c 100644
--- a/components/esp_wifi/src/phy_init.c
+++ b/components/esp_wifi/src/phy_init.c
@@ -34,6 +34,7 @@
 #include "esp_coexist_internal.h"
 #include "driver/periph_ctrl.h"
 #include "esp_private/wifi.h"
+#include "soc/soc_caps.h"
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/ets_sys.h"
@@ -65,6 +66,9 @@ static int64_t s_phy_rf_en_ts = 0;
 /* PHY spinlock for libphy.a */
 static DRAM_ATTR portMUX_TYPE s_phy_int_mux = portMUX_INITIALIZER_UNLOCKED;
 
+/* Memory to store PHY digital registers */
+static uint32_t* s_phy_digital_regs_mem = NULL;
+
 uint32_t IRAM_ATTR phy_enter_critical(void)
 {
     if (xPortInIsrContext()) {
@@ -122,6 +126,24 @@ IRAM_ATTR void esp_phy_common_clock_disable(void)
     wifi_bt_common_module_disable();
 }
 
+static inline void phy_digital_regs_store(void)
+{
+    if (s_phy_digital_regs_mem == NULL) {
+        s_phy_digital_regs_mem = (uint32_t *)malloc(SOC_PHY_DIG_REGS_MEM_SIZE);
+    }
+
+    if (s_phy_digital_regs_mem != NULL) {
+        phy_dig_reg_backup(true, s_phy_digital_regs_mem);
+    }
+}
+
+static inline void phy_digital_regs_load(void)
+{
+    if (s_phy_digital_regs_mem != NULL) {
+        phy_dig_reg_backup(false, s_phy_digital_regs_mem);
+    }
+}
+
 void esp_phy_enable(void)
 {
     _lock_acquire(&s_phy_access_lock);
@@ -142,6 +164,7 @@ void esp_phy_enable(void)
         }
         else {
             phy_wakeup_init();
+            phy_digital_regs_load();
         }
 
 #if CONFIG_IDF_TARGET_ESP32
@@ -159,6 +182,7 @@ void esp_phy_disable(void)
 
     s_phy_access_ref--;
     if (s_phy_access_ref == 0) {
+        phy_digital_regs_store();
         // Disable PHY and RF.
         phy_close_rf();
 #if CONFIG_IDF_TARGET_ESP32
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index bbc8e8f19f..5bb7b3a386 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -10,3 +10,7 @@
 #define SOC_BT_SUPPORTED 1
 #define SOC_SDIO_SLAVE_SUPPORTED    1
 #define SOC_CAN_SUPPORTED 1
+
+/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
+#define SOC_PHY_DIG_REGS_MEM_SIZE       (21*4)
+