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refactor(esp_tee): Disable the cache and interrupts in the TEE panic handler

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This commit is contained in:
Laukik Hase
2024-12-09 13:05:34 +05:30
parent cf8521abbb
commit 5063de64db
4 changed files with 22 additions and 7 deletions
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16
components/esp_tee/subproject/main/common/panic/esp_tee_panic.c
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@@ -10,6 +10,7 @@
#include "esp_macros.h" #include "esp_macros.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "esp_rom_uart.h" #include "esp_rom_uart.h"
#include "rom/cache.h"
#include "riscv/rv_utils.h" #include "riscv/rv_utils.h"
#include "riscv/rvruntime-frames.h" #include "riscv/rvruntime-frames.h"
@@ -18,6 +19,7 @@
#include "esp_tee.h" #include "esp_tee.h"
#include "esp_tee_apm_intr.h" #include "esp_tee_apm_intr.h"
#include "esp_tee_rv_utils.h"
#include "panic_helper.h" #include "panic_helper.h"
#define RV_FUNC_STK_SZ (32) #define RV_FUNC_STK_SZ (32)
@@ -26,12 +28,22 @@
static void tee_panic_end(void) static void tee_panic_end(void)
{ {
// make sure all the panic handler output is sent from UART FIFO // Disable interrupts
rv_utils_tee_intr_global_disable();
// Disable the cache
Cache_Disable_ICache();
// Clear the interrupt controller configurations
memset((void *)DR_REG_PLIC_MX_BASE, 0x00, (PLIC_MXINT_CLAIM_REG + 4 - DR_REG_PLIC_MX_BASE));
memset((void *)DR_REG_PLIC_UX_BASE, 0x00, (PLIC_UXINT_CLAIM_REG + 4 - DR_REG_PLIC_UX_BASE));
// Make sure all the panic handler output is sent from UART FIFO
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) { if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
} }
// generate core reset // Generate system reset
esp_rom_software_reset_system(); esp_rom_software_reset_system();
} }

2
components/esp_tee/subproject/main/common/panic/panic_helper_riscv.c
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@@ -117,9 +117,7 @@ void panic_print_isrcause(const void *f, int core)
static const char *pseudo_reason[] = { static const char *pseudo_reason[] = {
"Unknown reason", "Unknown reason",
"Interrupt wdt timeout on CPU0", "Interrupt wdt timeout on CPU0",
#if SOC_CPU_NUM > 1
"Interrupt wdt timeout on CPU1", "Interrupt wdt timeout on CPU1",
#endif
"Cache error", "Cache error",
}; };

1
components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in
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@@ -105,6 +105,7 @@ SECTIONS
*libtee_flash_mgr.a:*(.rodata .srodata .rodata.* .srodata.*) *libtee_flash_mgr.a:*(.rodata .srodata .rodata.* .srodata.*)
*libbootloader_support.a:bootloader_flash.*(.rodata .srodata .rodata.* .srodata.*) *libbootloader_support.a:bootloader_flash.*(.rodata .srodata .rodata.* .srodata.*)
*libmain.a:panic_helper_riscv.*(.rodata .srodata .rodata.* .srodata.*) *libmain.a:panic_helper_riscv.*(.rodata .srodata .rodata.* .srodata.*)
*libmain.a:esp_tee_apm_intr.c.*(.rodata .srodata .rodata.* .srodata.*)
_rodata_end = ABSOLUTE(.); _rodata_end = ABSOLUTE(.);
_tee_dram_end = ABSOLUTE(.); _tee_dram_end = ABSOLUTE(.);
} > dram_tee_seg } > dram_tee_seg

10
components/esp_tee/subproject/main/soc/esp32c6/include/esp_tee_rv_utils.h
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@@ -21,9 +21,6 @@
extern "C" { extern "C" {
#endif #endif
#define SET_BIT(t, n) (t |= (1UL << (n)))
#define CLR_BIT(t, n) (t &= ~(1UL << (n)))
FORCE_INLINE_ATTR void rv_utils_tee_intr_global_enable(void) FORCE_INLINE_ATTR void rv_utils_tee_intr_global_enable(void)
{ {
/* /*
@@ -50,6 +47,13 @@ FORCE_INLINE_ATTR void rv_utils_tee_intr_global_enable(void)
RV_SET_CSR(mstatus, MSTATUS_MIE); RV_SET_CSR(mstatus, MSTATUS_MIE);
} }
FORCE_INLINE_ATTR void rv_utils_tee_intr_global_disable(void)
{
RV_CLEAR_CSR(ustatus, USTATUS_UIE);
RV_CLEAR_CSR(mstatus, MSTATUS_UIE);
RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
}
FORCE_INLINE_ATTR void rv_utils_tee_intr_enable(uint32_t intr_mask) FORCE_INLINE_ATTR void rv_utils_tee_intr_enable(uint32_t intr_mask)
{ {
unsigned old_xstatus; unsigned old_xstatus;