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Merge branch 'fix/fix_submode_lost_in_reset_v5.4' into 'release/v5.4'

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fix(esp_hw_support): fix ESP_SLEEP_RTC_USE_RC_FAST_MODE submode lost in reset (v5.4)

See merge request espressif/esp-idf!41410
This commit is contained in:
Jiang Jiang Jian
2025-08-25 10:58:49 +08:00
parent e8486a1dd4 9298596ea7
commit 508441f986
6 changed files with 44 additions and 21 deletions
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8
components/esp_hw_support/port/esp32/rtc_clk.c
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@@ -284,12 +284,12 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
{ {
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
soc_rtc_slow_clk_src_t clk_src_before_switch = clk_ll_rtc_slow_get_src();
// Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256. // Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256.
if (clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch to RC_FAST_D256 if ((clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) && (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_USE_RC_FAST_MODE] == 0)) { // Switch to RC_FAST_D256
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true); esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true);
} else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch away from RC_FAST_D256 } else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, false); // This is the only user of ESP_SLEEP_RTC_USE_RC_FAST_MODE submode, so force disable it.
esp_sleep_sub_mode_force_disable(ESP_SLEEP_RTC_USE_RC_FAST_MODE);
} }
#endif #endif

8
components/esp_hw_support/port/esp32c2/rtc_clk.c
View File

@@ -74,12 +74,12 @@ bool rtc_clk_8md256_enabled(void)
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
{ {
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
soc_rtc_slow_clk_src_t clk_src_before_switch = clk_ll_rtc_slow_get_src();
// Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256. // Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256.
if (clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch to RC_FAST_D256 if ((clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) && (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_USE_RC_FAST_MODE] == 0)) { // Switch to RC_FAST_D256
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true); esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true);
} else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch away from RC_FAST_D256 } else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, false); // This is the only user of ESP_SLEEP_RTC_USE_RC_FAST_MODE submode, so force disable it.
esp_sleep_sub_mode_force_disable(ESP_SLEEP_RTC_USE_RC_FAST_MODE);
} }
#endif #endif

8
components/esp_hw_support/port/esp32c3/rtc_clk.c
View File

@@ -108,12 +108,12 @@ bool rtc_clk_8md256_enabled(void)
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
{ {
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
soc_rtc_slow_clk_src_t clk_src_before_switch = clk_ll_rtc_slow_get_src();
// Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256. // Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256.
if (clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch to RC_FAST_D256 if ((clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) && (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_USE_RC_FAST_MODE] == 0)) { // Switch to RC_FAST_D256
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true); esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true);
} else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch away from RC_FAST_D256 } else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, false); // This is the only user of ESP_SLEEP_RTC_USE_RC_FAST_MODE submode, so force disable it.
esp_sleep_sub_mode_force_disable(ESP_SLEEP_RTC_USE_RC_FAST_MODE);
} }
#endif #endif

8
components/esp_hw_support/port/esp32s2/rtc_clk.c
View File

@@ -187,12 +187,12 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
{ {
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
soc_rtc_slow_clk_src_t clk_src_before_switch = clk_ll_rtc_slow_get_src();
// Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256. // Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256.
if (clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch to RC_FAST_D256 if ((clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) && (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_USE_RC_FAST_MODE] == 0)) { // Switch to RC_FAST_D256
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true); esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true);
} else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch away from RC_FAST_D256 } else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, false); // This is the only user of ESP_SLEEP_RTC_USE_RC_FAST_MODE submode, so force disable it.
esp_sleep_sub_mode_force_disable(ESP_SLEEP_RTC_USE_RC_FAST_MODE);
} }
#endif #endif

8
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@@ -124,12 +124,12 @@ bool rtc_clk_8md256_enabled(void)
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
{ {
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
soc_rtc_slow_clk_src_t clk_src_before_switch = clk_ll_rtc_slow_get_src();
// Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256. // Keep the RTC8M_CLK on in sleep if RTC clock is rc_fast_d256.
if (clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch to RC_FAST_D256 if ((clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) && (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_USE_RC_FAST_MODE] == 0)) { // Switch to RC_FAST_D256
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true); esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, true);
} else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 && clk_src_before_switch == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { // Switch away from RC_FAST_D256 } else if (clk_src != SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_USE_RC_FAST_MODE, false); // This is the only user of ESP_SLEEP_RTC_USE_RC_FAST_MODE submode, so force disable it.
esp_sleep_sub_mode_force_disable(ESP_SLEEP_RTC_USE_RC_FAST_MODE);
} }
#endif #endif

25
components/esp_hw_support/test_apps/rtc_8md256/main/test_rtc_8md256.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -63,6 +63,29 @@ TEST_CASE_MULTIPLE_STAGES("Can use 8MD256 as RTC clock source in deepsleep (ente
request_core1_do_deepsleep, request_core1_do_deepsleep,
check_reset_reason_deep_sleep); check_reset_reason_deep_sleep);
static void do_cpu_reset(void)
{
esp_restart();
}
static void check_cpu_reset_and_do_system_reset(void)
{
TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
esp_rom_software_reset_system();
}
static void check_system_reset_and_do_deepsleep(void)
{
TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
test_deepsleep(false);
}
TEST_CASE_MULTIPLE_STAGES("Can use 8MD256 as RTC clock source in deepsleep after reset", "[pm]",
do_cpu_reset,
check_cpu_reset_and_do_system_reset,
check_system_reset_and_do_deepsleep,
check_reset_reason_deep_sleep);
static void test_lightsleep(bool force_rtc_periph) static void test_lightsleep(bool force_rtc_periph)
{ {
esp_sleep_enable_timer_wakeup(2000000); esp_sleep_enable_timer_wakeup(2000000);