From 50aee21d33117fd2c9229341d50c7d04974dacd7 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 18 Jul 2025 13:35:22 +0800 Subject: [PATCH] feat(spi_flash): Add basic support for esp32h4 --- .../src/bootloader_flash_config_esp32h4.c | 20 ++++++++--- .../esp32h21/include/hal/spimem_flash_ll.h | 10 +++--- components/hal/esp32h4/include/hal/mspi_ll.h | 17 +++++++++- .../hal/esp32h4/include/hal/spimem_flash_ll.h | 34 +++++++++++++------ .../soc/esp32h4/include/soc/clk_tree_defs.h | 2 +- .../spi_flash/esp32h4/Kconfig.flash_freq | 14 ++++---- .../esp_flash/main/test_esp_flash_def.h | 2 +- .../esp_flash/main/test_esp_flash_drv.c | 4 +-- 8 files changed, 70 insertions(+), 33 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c index f42b82c425..10e54d2c3d 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c @@ -25,6 +25,7 @@ #include "hal/mmu_ll.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" +#include "hal/mspi_ll.h" static const char *TAG = "boot.esp32h4"; @@ -84,6 +85,15 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); } +static void IRAM_ATTR bootloader_flash_clock_init(void) +{ + // // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK + // // (FPGA image fixed MSPI0/1 clock to 64MHz) + // clk_ll_xtal_x2_enable(); + // _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M); + _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F48M); +} + static void update_flash_config(const esp_image_header_t *bootloader_hdr) { uint32_t size; @@ -121,16 +131,16 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) const char *str; switch (bootloader_hdr->spi_speed) { case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "32MHz"; + str = "24MHz"; break; case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "16MHz"; + str = "12MHz"; break; case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "64MHz"; + str = "48MHz"; break; default: - str = "16MHz"; + str = "12MHz"; break; } ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); @@ -185,6 +195,7 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) static void IRAM_ATTR bootloader_init_flash_configure(void) { + bootloader_flash_clock_init(); bootloader_configure_spi_pins(1); bootloader_flash_cs_timing_config(); } @@ -267,6 +278,7 @@ void bootloader_flash_hardware_init(void) bootloader_configure_spi_pins(1); bootloader_flash_set_spi_mode(&hdr); bootloader_flash_clock_config(&hdr); + bootloader_flash_clock_init(); bootloader_flash_cs_timing_config(); bootloader_spi_flash_resume(); diff --git a/components/hal/esp32h21/include/hal/spimem_flash_ll.h b/components/hal/esp32h21/include/hal/spimem_flash_ll.h index 272d6c2aab..92f150b56a 100644 --- a/components/hal/esp32h21/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h21/include/hal/spimem_flash_ll.h @@ -603,14 +603,12 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_ */ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { - // dev->ctrl2.cs_hold_time = hold_n - 1; - // dev->user.cs_hold = (hold_n > 0? 1: 0); + // not supported on esp32h21 } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) { - // dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - // dev->ctrl2.cs_setup_time = cs_setup_time - 1; + // not supported on esp32h21 } /** @@ -626,7 +624,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) uint8_t clock_val = 0; switch (PCR.mspi_conf.mspi_clk_sel) { case 0: - clock_val = 32; + clock_val = 48; break; case 1: clock_val = 8; @@ -635,7 +633,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) clock_val = 64; break; case 3: - clock_val = 32; + clock_val = 48; break; default: HAL_ASSERT(false); diff --git a/components/hal/esp32h4/include/hal/mspi_ll.h b/components/hal/esp32h4/include/hal/mspi_ll.h index a27ffcfc97..cb52b979e3 100644 --- a/components/hal/esp32h4/include/hal/mspi_ll.h +++ b/components/hal/esp32h4/include/hal/mspi_ll.h @@ -46,7 +46,22 @@ __attribute__((always_inline)) static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src) { HAL_ASSERT(mspi_id == 0); - // TODO [ESP32H4] + switch (clk_src) { + case FLASH_CLK_SRC_XTAL: + PCR.mspi_clk_conf.mspi_func_clk_sel = 0; + break; + case FLASH_CLK_SRC_RC_FAST: + PCR.mspi_clk_conf.mspi_func_clk_sel = 1; + break; + // case FLASH_CLK_SRC_PLL_F64M: + // PCR.mspi_clk_conf.mspi_func_clk_sel = 2; + // break; + case FLASH_CLK_SRC_PLL_F48M: + PCR.mspi_clk_conf.mspi_func_clk_sel = 3; + break; + default: + HAL_ASSERT(false); + } } #ifdef __cplusplus diff --git a/components/hal/esp32h4/include/hal/spimem_flash_ll.h b/components/hal/esp32h4/include/hal/spimem_flash_ll.h index beecacae87..75a5604294 100644 --- a/components/hal/esp32h4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h4/include/hal/spimem_flash_ll.h @@ -28,8 +28,6 @@ #include "soc/pcr_struct.h" #include "esp_rom_sys.h" -//TODO: [ESP32H4] IDF-12388 inherited from verification branch, need check - #ifdef __cplusplus extern "C" { #endif @@ -522,11 +520,8 @@ static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen) { dev->user.usr_command = 1; - typeof(dev->user2) user2 = { - .usr_command_value = command, - .usr_command_bitlen = (bitlen - 1), - }; - dev->user2.val = user2.val; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user2, usr_command_value, command); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user2, usr_command_bitlen, (bitlen - 1)); } /** @@ -561,7 +556,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr) { dev->cache_fctrl.usr_addr_4byte = 0; - dev->rd_status.wb_mode = extra_addr; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr); } /** @@ -607,12 +602,12 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_ */ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { - //TODO: [ESP32H4] IDF-12388 + //not supported on esp32h4 } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) { - //TODO: [ESP32H4] IDF-12388 + //not supported on esp32h4 } /** @@ -625,7 +620,24 @@ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_ */ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) { - return 64; + uint8_t clock_val = 0; + switch (PCR.mspi_clk_conf.mspi_func_clk_sel) { + case 0: + clock_val = 48; + break; + case 1: + clock_val = 8; + break; + case 2: + clock_val = 64; + break; + case 3: + clock_val = 48; + break; + default: + HAL_ASSERT(false); + } + return clock_val; } /** diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index e70bc7122f..3944afd77f 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -257,7 +257,7 @@ typedef enum { FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ // FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */ - FLASH_CLK_SRC_REF_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ + FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ } soc_periph_flash_clk_src_t; diff --git a/components/spi_flash/esp32h4/Kconfig.flash_freq b/components/spi_flash/esp32h4/Kconfig.flash_freq index f173f3fd88..4100aa4b8f 100644 --- a/components/spi_flash/esp32h4/Kconfig.flash_freq +++ b/components/spi_flash/esp32h4/Kconfig.flash_freq @@ -1,10 +1,10 @@ choice ESPTOOLPY_FLASHFREQ prompt "Flash SPI speed" - default ESPTOOLPY_FLASHFREQ_32M - config ESPTOOLPY_FLASHFREQ_64M - bool "64 MHz" - config ESPTOOLPY_FLASHFREQ_32M - bool "32 MHz" - config ESPTOOLPY_FLASHFREQ_16M - bool "16 MHz" + default ESPTOOLPY_FLASHFREQ_48M + config ESPTOOLPY_FLASHFREQ_48M + bool "48 MHz" + config ESPTOOLPY_FLASHFREQ_24M + bool "24 MHz" + config ESPTOOLPY_FLASHFREQ_12M + bool "12 MHz" endchoice diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h index b1f5390dab..02fb9d4c03 100644 --- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h +++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h @@ -88,7 +88,7 @@ #define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP #define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS -#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 +#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 #define FSPI_PIN_NUM_MOSI 5 #define FSPI_PIN_NUM_MISO 0 diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c index bf46dac925..c59f0da12f 100644 --- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c +++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c @@ -597,8 +597,8 @@ TEST_CASE_MULTI_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_togg // This table could be chip specific in the future. #if CONFIG_IDF_TARGET_ESP32C2 -uint8_t flash_frequency_table[5] = {5, 10, 20, 40}; -#elif CONFIG_IDF_TARGET_ESP32H21 +uint8_t flash_frequency_table[4] = {5, 10, 20, 40}; +#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 uint8_t flash_frequency_table[4] = {6, 12, 24, 48}; #else uint8_t flash_frequency_table[6] = {5, 10, 20, 26, 40, 80};