From 512800891e7bb7dc41ce3d3b4ac1ec1db7e3d72c Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Thu, 1 Apr 2021 19:52:30 +0800 Subject: [PATCH] light sleep: add uart new final state machine support for esp32s3 --- components/hal/esp32s3/include/hal/uart_ll.h | 3 +++ components/soc/esp32s3/include/soc/uart_caps.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 24bc307cea..cbf53d454a 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -33,6 +33,9 @@ extern "C" { #define UART_LL_MIN_WAKEUP_THRESH (2) #define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask +#define UART_LL_FSM_IDLE (0x0) +#define UART_LL_FSM_TX_WAIT_SEND (0xf) + // Define UART interrupts typedef enum { UART_INTR_RXFIFO_FULL = (0x1 << 0), diff --git a/components/soc/esp32s3/include/soc/uart_caps.h b/components/soc/esp32s3/include/soc/uart_caps.h index 2024c7a2e5..30d219baac 100644 --- a/components/soc/esp32s3/include/soc/uart_caps.h +++ b/components/soc/esp32s3/include/soc/uart_caps.h @@ -23,6 +23,9 @@ extern "C" { #define SOC_UART_NUM (3) +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + #ifdef __cplusplus } #endif