diff --git a/components/app_trace/app_trace.c b/components/app_trace/app_trace.c
index 2895972b79..a914a33763 100644
--- a/components/app_trace/app_trace.c
+++ b/components/app_trace/app_trace.c
@@ -156,9 +156,12 @@
 
 #include <string.h>
 #include <sys/param.h>
+#include "sdkconfig.h"
 #include "soc/soc.h"
+#include "soc/dport_access.h"
+#if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
-#if CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2
 #include "soc/sensitive_reg.h"
 #endif
 #if __XTENSA__
diff --git a/components/app_trace/app_trace_util.c b/components/app_trace/app_trace_util.c
index 238fd60205..4fe94de89e 100644
--- a/components/app_trace/app_trace_util.c
+++ b/components/app_trace/app_trace_util.c
@@ -22,6 +22,8 @@
 #include "esp32s2/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
 #endif
 
 ///////////////////////////////////////////////////////////////////////////////
diff --git a/components/bootloader/subproject/main/CMakeLists.txt b/components/bootloader/subproject/main/CMakeLists.txt
index da00c55e11..651a94468d 100644
--- a/components/bootloader/subproject/main/CMakeLists.txt
+++ b/components/bootloader/subproject/main/CMakeLists.txt
@@ -2,7 +2,10 @@ idf_component_register(SRCS "bootloader_start.c"
                     REQUIRES bootloader bootloader_support)
 
 idf_build_get_property(target IDF_TARGET)
-set(scripts "ld/${target}/bootloader.ld"
-            "ld/${target}/bootloader.rom.ld")
+set(scripts "ld/${target}/bootloader.ld")
+
+if(NOT CONFIG_IDF_TARGET_ESP32C3)
+    list(APPEND scripts "ld/${target}/bootloader.rom.ld")
+endif()
 
 target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}")
diff --git a/components/bootloader_support/include/bootloader_common.h b/components/bootloader_support/include/bootloader_common.h
index baf36702c1..0723d19512 100644
--- a/components/bootloader_support/include/bootloader_common.h
+++ b/components/bootloader_support/include/bootloader_common.h
@@ -23,6 +23,8 @@
 #include "esp32s2/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/rtc.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h
index 33b92cc9cc..4dfd11b0be 100644
--- a/components/bootloader_support/include/esp_app_format.h
+++ b/components/bootloader_support/include/esp_app_format.h
@@ -23,6 +23,7 @@ typedef enum {
     ESP_CHIP_ID_ESP32 = 0x0000,  /*!< chip ID: ESP32 */
     ESP_CHIP_ID_ESP32S2 = 0x0002,  /*!< chip ID: ESP32-S2 */
     ESP_CHIP_ID_ESP32S3 = 0x0004, /*!< chip ID: ESP32-S3 */
+    ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
     ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;
 
diff --git a/components/bootloader_support/include/esp_flash_encrypt.h b/components/bootloader_support/include/esp_flash_encrypt.h
index ef3b802715..33e6aabed2 100644
--- a/components/bootloader_support/include/esp_flash_encrypt.h
+++ b/components/bootloader_support/include/esp_flash_encrypt.h
@@ -52,7 +52,7 @@ static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_e
     uint32_t flash_crypt_cnt = 0;
 #if CONFIG_IDF_TARGET_ESP32
     flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT);
-#elif CONFIG_IDF_TARGET_ESP32S2
+#else
     flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT);
 #endif
     /* __builtin_parity is in flash, so we calculate parity inline */
diff --git a/components/bootloader_support/include/esp_secure_boot.h b/components/bootloader_support/include/esp_secure_boot.h
index 0526391b37..3eb4db0165 100644
--- a/components/bootloader_support/include/esp_secure_boot.h
+++ b/components/bootloader_support/include/esp_secure_boot.h
@@ -22,6 +22,10 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/efuse.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/efuse.h"
 #endif
 
 typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c
index 7f373beaf5..db1a736d12 100644
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -14,19 +14,22 @@
 #include "sdkconfig.h"
 #include "soc/soc.h"
 #include "soc/rtc.h"
-#include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
 #include "soc/rtc_cntl_reg.h"
 
+#define CPU_RESET_REASON RTC_SW_CPU_RESET
+
 #ifdef CONFIG_IDF_TARGET_ESP32
+#include "soc/dport_reg.h"
 #include "esp32/rom/rtc.h"
+#undef CPU_RESET_REASON
 #define CPU_RESET_REASON SW_CPU_RESET
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/rtc.h"
-#define CPU_RESET_REASON RTC_SW_CPU_RESET
 #elif CONFIG_IDF_TARGET_ESP32S3
-#define CPU_RESET_REASON RTC_SW_CPU_RESET
 #include "esp32s3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/rtc.h"
 #endif
 #include "esp_rom_uart.h"
 
diff --git a/components/bootloader_support/src/bootloader_common.c b/components/bootloader_support/src/bootloader_common.c
index 94faff986a..2b2a289cd3 100644
--- a/components/bootloader_support/src/bootloader_common.c
+++ b/components/bootloader_support/src/bootloader_common.c
@@ -23,6 +23,8 @@
 #include "esp32s2/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
 #endif
 #include "esp_rom_crc.h"
 #include "esp_rom_gpio.h"
diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c
index c3f3fbb93f..905945309e 100644
--- a/components/bootloader_support/src/bootloader_flash.c
+++ b/components/bootloader_support/src/bootloader_flash.c
@@ -35,6 +35,8 @@
 #include "esp32s2/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
 #endif
 
 
@@ -89,8 +91,8 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool
     if (write_encrypted) {
 #if CONFIG_IDF_TARGET_ESP32
         return spi_flash_write_encrypted(dest_addr, src, size);
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
-        return SPI_Encrypt_Write(dest_addr, src, size);
+#else
+        return esp_rom_spiflash_write_encrypted(dest_addr, src, size);
 #endif
     } else {
         return spi_flash_write(dest_addr, src, size);
@@ -109,7 +111,6 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 
 #else
 /* Bootloader version, uses ROM functions only */
-#include "soc/dport_reg.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/spi_flash.h"
 #include "esp32/rom/cache.h"
@@ -121,6 +122,10 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 #include "esp32s3/rom/spi_flash.h"
 #include "esp32s3/rom/cache.h"
 #include "soc/cache_memory.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
+#include "esp32c3/rom/cache.h"
+#include "soc/cache_memory.h"
 #endif
 static const char *TAG = "bootloader_flash";
 
@@ -132,7 +137,9 @@ static const char *TAG = "bootloader_flash";
 #define MMU_SIZE          (0x320000)
 #define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
 #define FLASH_READ_VADDR MMU_BLOCK50_VADDR
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+
+#else // !CONFIG_IDF_TARGET_ESP32
+
 /* Use first 63 blocks in MMU for bootloader_mmap,
    63th block for bootloader_flash_read
 */
@@ -180,6 +187,9 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
 #elif CONFIG_IDF_TARGET_ESP32S3
     uint32_t autoload = Cache_Suspend_DCache();
     Cache_Invalidate_DCache_All();
+#elif CONFIG_IDF_TARGET_ESP32C3
+    uint32_t autoload = Cache_Suspend_ICache();
+    Cache_Invalidate_ICache_All();
 #endif
     ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x",
              src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned );
@@ -187,7 +197,7 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
     int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
 #elif CONFIG_IDF_TARGET_ESP32S2
     int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
-#elif CONFIG_IDF_TARGET_ESP32S3
+#else // S3, C3
     int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
 #endif
     if (e != 0) {
@@ -198,6 +208,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
         Cache_Resume_ICache(autoload);
 #elif CONFIG_IDF_TARGET_ESP32S3
         Cache_Resume_DCache(autoload);
+#elif CONFIG_IDF_TARGET_ESP32C3
+        Cache_Resume_ICache(autoload);
 #endif
         return NULL;
     }
@@ -207,6 +219,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
     Cache_Resume_ICache(autoload);
 #elif CONFIG_IDF_TARGET_ESP32S3
     Cache_Resume_DCache(autoload);
+#elif CONFIG_IDF_TARGET_ESP32C3
+    Cache_Resume_ICache(autoload);
 #endif
 
     mapped = true;
@@ -228,10 +242,14 @@ void bootloader_munmap(const void *mapping)
         Cache_Invalidate_ICache_All();
         Cache_MMU_Init();
 #elif CONFIG_IDF_TARGET_ESP32S3
-        //TODO, save the autoload value.
         Cache_Suspend_DCache();
         Cache_Invalidate_DCache_All();
         Cache_MMU_Init();
+#elif CONFIG_IDF_TARGET_ESP32C3
+        //TODO, save the autoload value.
+        Cache_Suspend_ICache();
+        Cache_Invalidate_ICache_All();
+        Cache_MMU_Init();
 #endif
         mapped = false;
         current_read_mapping = UINT32_MAX;
@@ -261,6 +279,8 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
     uint32_t autoload = Cache_Suspend_ICache();
 #elif CONFIG_IDF_TARGET_ESP32S3
     uint32_t autoload = Cache_Suspend_DCache();
+#elif CONFIG_IDF_TARGET_ESP32C3
+    uint32_t autoload = Cache_Suspend_ICache();
 #endif
     esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
 #if CONFIG_IDF_TARGET_ESP32
@@ -269,6 +289,8 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
     Cache_Resume_ICache(autoload);
 #elif CONFIG_IDF_TARGET_ESP32S3
     Cache_Resume_DCache(autoload);
+#elif CONFIG_IDF_TARGET_ESP32C3
+    Cache_Resume_ICache(autoload);
 #endif
 
     return spi_to_esp_err(r);
@@ -293,6 +315,9 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
 #elif CONFIG_IDF_TARGET_ESP32S3
             uint32_t autoload = Cache_Suspend_DCache();
             Cache_Invalidate_DCache_All();
+#elif CONFIG_IDF_TARGET_ESP32C3
+            uint32_t autoload = Cache_Suspend_ICache();
+            Cache_Invalidate_ICache_All();
 #endif
             ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
 #if CONFIG_IDF_TARGET_ESP32
@@ -301,6 +326,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
             int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
 #elif CONFIG_IDF_TARGET_ESP32S3
             int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
+#elif CONFIG_IDF_TARGET_ESP32C3
+            int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
 #endif
             if (e != 0) {
                 ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
@@ -310,6 +337,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
                 Cache_Resume_ICache(autoload);
 #elif CONFIG_IDF_TARGET_ESP32S3
                 Cache_Resume_DCache(autoload);
+#elif CONFIG_IDF_TARGET_ESP32C3
+                Cache_Resume_ICache(autoload);
 #endif
                 return ESP_FAIL;
             }
@@ -320,6 +349,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
             Cache_Resume_ICache(autoload);
 #elif CONFIG_IDF_TARGET_ESP32S3
             Cache_Resume_DCache(autoload);
+#elif CONFIG_IDF_TARGET_ESP32C3
+            Cache_Resume_ICache(autoload);
 #endif
         }
         map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at));
@@ -422,7 +453,7 @@ uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, u
     uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
 #if CONFIG_IDF_TARGET_ESP32
     SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else
     SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
 #endif
     SPIFLASH.user.usr_dummy = 0;
@@ -434,13 +465,13 @@ uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, u
     SPIFLASH.user.usr_miso = miso_len > 0;
 #if CONFIG_IDF_TARGET_ESP32
     SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else
     SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
 #endif
     SPIFLASH.user.usr_mosi = mosi_len > 0;
 #if CONFIG_IDF_TARGET_ESP32
     SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else
     SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
 #endif
     SPIFLASH.data_buf[0] = mosi_data;
diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index badbc8d3d6..46bab26849 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -22,6 +22,7 @@
 #include "esp_rom_sys.h"
 #include "esp_rom_uart.h"
 #if CONFIG_IDF_TARGET_ESP32
+#include "soc/dport_reg.h"
 #include "esp32/rom/cache.h"
 #include "esp32/rom/spi_flash.h"
 #include "esp32/rom/rtc.h"
@@ -40,14 +41,25 @@
 #include "esp32s3/rom/secure_boot.h"
 #include "soc/extmem_reg.h"
 #include "soc/cache_memory.h"
-#else
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/cache.h"
+#include "esp32c3/rom/efuse.h"
+#include "esp32c3/rom/ets_sys.h"
+#include "esp32c3/rom/spi_flash.h"
+#include "esp32c3/rom/crc.h"
+#include "esp32c3/rom/rtc.h"
+#include "esp32c3/rom/uart.h"
+#include "esp32c3/rom/gpio.h"
+#include "esp32c3/rom/secure_boot.h"
+#include "soc/extmem_reg.h"
+#include "soc/cache_memory.h"
+#else // CONFIG_IDF_TARGET_*
 #error "Unsupported IDF_TARGET"
 #endif
 
 #include "soc/soc.h"
 #include "soc/cpu.h"
 #include "soc/rtc.h"
-#include "soc/dport_reg.h"
 #include "soc/gpio_periph.h"
 #include "soc/efuse_periph.h"
 #include "soc/rtc_periph.h"
@@ -693,6 +705,9 @@ static void set_cache_and_start_app(
 #elif CONFIG_IDF_TARGET_ESP32S3
     uint32_t autoload = Cache_Suspend_DCache();
     Cache_Invalidate_DCache_All();
+#elif CONFIG_IDF_TARGET_ESP32C3
+    uint32_t autoload = Cache_Suspend_ICache();
+    Cache_Invalidate_ICache_All();
 #endif
 
     /* Clear the MMU entries that are already set up,
@@ -702,7 +717,7 @@ static void set_cache_and_start_app(
     for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
         DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
     }
-#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
+#else
     for (int i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
         FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
     }
@@ -717,6 +732,8 @@ static void set_cache_and_start_app(
     rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
 #elif CONFIG_IDF_TARGET_ESP32S3
     rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
+#elif CONFIG_IDF_TARGET_ESP32C3
+    rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
 #endif
     ESP_LOGV(TAG, "rc=%d", rc);
 #if CONFIG_IDF_TARGET_ESP32
@@ -742,6 +759,8 @@ static void set_cache_and_start_app(
     rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
 #elif CONFIG_IDF_TARGET_ESP32S3
     rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
+#elif CONFIG_IDF_TARGET_ESP32C3
+    rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
 #endif
     ESP_LOGV(TAG, "rc=%d", rc);
 #if CONFIG_IDF_TARGET_ESP32
@@ -762,6 +781,9 @@ static void set_cache_and_start_app(
 #if !CONFIG_FREERTOS_UNICORE
     REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
 #endif
+#elif CONFIG_IDF_TARGET_ESP32C3
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
 #endif
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Enable(0);
@@ -769,6 +791,8 @@ static void set_cache_and_start_app(
     Cache_Resume_ICache(autoload);
 #elif CONFIG_IDF_TARGET_ESP32S3
     Cache_Resume_DCache(autoload);
+#elif CONFIG_IDF_TARGET_ESP32C3
+    Cache_Resume_ICache(autoload);
 #endif
     // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
 
diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c
index 2c39650995..8c6e46a1c6 100644
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -35,6 +35,9 @@
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/rtc.h"
 #include "esp32s3/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/rtc.h"
+#include "esp32c3/rom/secure_boot.h"
 #endif
 
 /* Checking signatures as part of verifying images is necessary:
diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c
index 1fc650f45b..f1b14ecab6 100644
--- a/components/bootloader_support/src/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encrypt.c
@@ -29,6 +29,9 @@
 #elif CONFIG_IDF_TARGET_ESP32S3
 #define CRYPT_CNT ESP_EFUSE_SPI_BOOT_CRYPT_CNT
 #define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT
+#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT
 #endif
 
 #ifndef BOOTLOADER_BUILD
diff --git a/components/bootloader_support/src/flash_partitions.c b/components/bootloader_support/src/flash_partitions.c
index c95b2b0da0..81ef00de9b 100644
--- a/components/bootloader_support/src/flash_partitions.c
+++ b/components/bootloader_support/src/flash_partitions.c
@@ -14,8 +14,14 @@
 #include <string.h>
 #include "esp_flash_partitions.h"
 #include "esp_log.h"
-#include "esp32/rom/spi_flash.h"
 #include "esp_rom_md5.h"
+#if CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/spi_flash.h"
+#else
+#include "esp32/rom/spi_flash.h"
+#endif
 
 static const char *TAG = "flash_parts";
 
diff --git a/components/bootloader_support/src/flash_qio_mode.c b/components/bootloader_support/src/flash_qio_mode.c
index 140e64da61..0fb82c0e1d 100644
--- a/components/bootloader_support/src/flash_qio_mode.c
+++ b/components/bootloader_support/src/flash_qio_mode.c
@@ -27,6 +27,8 @@
 #include "esp32s2/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
 #endif
 #include "soc/efuse_periph.h"
 #include "soc/io_mux_reg.h"
@@ -195,7 +197,7 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
 #if CONFIG_IDF_TARGET_ESP32
     int wp_pin = bootloader_flash_get_wp_pin();
     esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig);
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else
     esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), spiconfig);
 #endif
     return ESP_OK;
diff --git a/components/driver/adc_common.c b/components/driver/adc_common.c
index ee44cef816..4d39e6ac6b 100644
--- a/components/driver/adc_common.c
+++ b/components/driver/adc_common.c
@@ -16,7 +16,6 @@
 #include <stdlib.h>
 #include <ctype.h>
 #include "freertos/FreeRTOS.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/semphr.h"
 #include "freertos/timers.h"
 #include "esp_log.h"
@@ -31,6 +30,8 @@
 
 #include "hal/adc_types.h"
 #include "hal/adc_hal.h"
+
+#if !CONFIG_IDF_TARGET_ESP32C3
 #include "hal/dac_hal.h"
 #include "hal/adc_hal_conf.h"
 
@@ -83,14 +84,14 @@ static _lock_t adc2_wifi_lock;
 #define ADC2_WIFI_LOCK_TRY_ACQUIRE()    _lock_try_acquire( &adc2_wifi_lock )
 #define ADC2_WIFI_LOCK_CHECK()          ((uint32_t *)adc2_wifi_lock != NULL)
 
-#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
+#else // !CONFIG_IDF_TARGET_ESP32
 
 #define ADC2_WIFI_LOCK_ACQUIRE()
 #define ADC2_WIFI_LOCK_RELEASE()
 #define ADC2_WIFI_LOCK_TRY_ACQUIRE()    (0)     //WIFI controller and rtc controller have independent parameter configuration.
 #define ADC2_WIFI_LOCK_CHECK()          (true)
 
-#endif
+#endif // CONFIG_IDF_TARGET_ESP32
 
 //prevent ADC2 being used by tasks (regardless of WIFI)
 static portMUX_TYPE adc2_spinlock = portMUX_INITIALIZER_UNLOCKED;
@@ -102,11 +103,11 @@ static _lock_t adc1_dma_lock;
 #define ADC1_DMA_LOCK_ACQUIRE() _lock_acquire( &adc1_dma_lock )
 #define ADC1_DMA_LOCK_RELEASE() _lock_release( &adc1_dma_lock )
 
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
 #ifdef CONFIG_PM_ENABLE
 static esp_pm_lock_handle_t s_adc2_arbiter_lock;
 #endif  //CONFIG_PM_ENABLE
-#endif  //CONFIG_IDF_TARGET_ESP32S2
+#endif  // !CONFIG_IDF_TARGET_ESP32
 
 /*---------------------------------------------------------------
                     ADC Common
@@ -176,19 +177,15 @@ esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
     if (adc_unit & ADC_UNIT_1) {
         ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
         gpio_num = ADC_GET_IO_NUM(ADC_NUM_1, channel);
-        ADC_CHECK_RET(rtc_gpio_init(gpio_num));
-        ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
-        ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
-        ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num));
     }
     if (adc_unit & ADC_UNIT_2) {
         ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
         gpio_num = ADC_GET_IO_NUM(ADC_NUM_2, channel);
-        ADC_CHECK_RET(rtc_gpio_init(gpio_num));
-        ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
-        ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
-        ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num));
     }
+    ADC_CHECK_RET(rtc_gpio_init(gpio_num));
+    ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
+    ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
+    ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num));
     return ESP_OK;
 }
 
@@ -210,8 +207,8 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
 {
 #ifdef CONFIG_IDF_TARGET_ESP32
     ADC_CHECK(bits < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
-#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
-    ADC_CHECK(bits == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG);
+#else
+    ADC_CHECK(bits == ADC_WIDTH_BIT_13, "WIDTH ERR: " CONFIG_IDF_TARGET " support 13 bit width", ESP_ERR_INVALID_ARG);
 #endif
 
     ADC_ENTER_CRITICAL();
@@ -232,7 +229,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
  * @return
  *      - ESP_OK Success
  */
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
 esp_err_t adc_rtc_reset(void)
 {
     ADC_ENTER_CRITICAL();
@@ -284,8 +281,8 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit)
 {
 #ifdef CONFIG_IDF_TARGET_ESP32
     ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
-#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
-    ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG);
+#elif !defined(CONFIG_IDF_TARGET_ESP32)
+    ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: " CONFIG_IDF_TARGET " support 13 bit width", ESP_ERR_INVALID_ARG);
 #endif
 
     ADC_ENTER_CRITICAL();
@@ -345,13 +342,13 @@ int adc1_get_raw(adc1_channel_t channel)
     adc_hal_hall_disable(); //Disable other peripherals.
     adc_hal_amp_disable();  //Currently the LNA is not open, close it by default.
 #endif
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
     adc_set_init_code(ADC_NUM_1, channel);             // calibration for adc
 #endif
     adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_RTC);    //Set controller
     adc_hal_convert(ADC_NUM_1, channel, &adc_value);   //Start conversion, For ADC1, the data always valid.
     ADC_EXIT_CRITICAL();
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
     adc_hal_rtc_reset();    //Reset FSM of rtc controller
 #endif
 
@@ -364,6 +361,7 @@ int adc1_get_voltage(adc1_channel_t channel)    //Deprecated. Use adc1_get_raw()
     return adc1_get_raw(channel);
 }
 
+#if SOC_ULP_SUPPORTED
 void adc1_ulp_enable(void)
 {
     adc_power_on();
@@ -379,6 +377,7 @@ void adc1_ulp_enable(void)
 #endif
     ADC_EXIT_CRITICAL();
 }
+#endif
 
 /*---------------------------------------------------------------
                     ADC2
@@ -438,7 +437,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
 
 static inline void adc2_config_width(adc_bits_width_t width_bit)
 {
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
 #ifdef CONFIG_PM_ENABLE
     /* Lock APB clock. */
     if (s_adc2_arbiter_lock == NULL) {
@@ -459,7 +458,7 @@ static inline void adc2_dac_disable( adc2_channel_t channel)
     } else if ( channel == ADC2_CHANNEL_9 ) {
         dac_output_disable(DAC_CHANNEL_2);
     }
-#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
+#else
     if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 1
         dac_output_disable(DAC_CHANNEL_1);
     } else if ( channel == ADC2_CHANNEL_7 ) {
@@ -482,7 +481,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     ADC_CHECK(channel < ADC2_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
 #ifdef CONFIG_IDF_TARGET_ESP32
     ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
-#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
+#else
     ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG);
 #endif
 
@@ -498,12 +497,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     adc2_dac_disable(channel);      //disable other peripherals
 #endif
     adc2_config_width(width_bit);   // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
     adc_set_init_code(ADC_NUM_2, channel);  // calibration for adc
 #endif
     adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);// set controller
 
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
 #ifdef CONFIG_PM_ENABLE
     if (s_adc2_arbiter_lock) {
         esp_pm_lock_acquire(s_adc2_arbiter_lock);
@@ -527,7 +526,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     ADC2_WIFI_LOCK_RELEASE();
     ADC2_EXIT_CRITICAL();
 
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
     adc_rtc_reset();
 #endif
 
@@ -572,3 +571,5 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
     adc_gpio_init(ADC_UNIT_2, ch);
     return ESP_OK;
 }
+
+#endif // !CONFIG_IDF_TARGET_ESP32C3
diff --git a/components/driver/gpio.c b/components/driver/gpio.c
index 9cc2fcd45f..f8cbcae1ba 100644
--- a/components/driver/gpio.c
+++ b/components/driver/gpio.c
@@ -15,7 +15,6 @@
 #include <esp_types.h>
 #include "esp_err.h"
 #include "freertos/FreeRTOS.h"
-#include "freertos/xtensa_api.h"
 #include "driver/gpio.h"
 #include "driver/rtc_io.h"
 #include "soc/soc.h"
@@ -87,7 +86,11 @@ esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
         gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     } else {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
         rtc_gpio_pullup_en(gpio_num);
+#else
+        abort(); // This should be eliminated as unreachable, unless a programming error has occured
+#endif
     }
 
     return ESP_OK;
@@ -102,7 +105,11 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
         gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     } else {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
         rtc_gpio_pullup_dis(gpio_num);
+#else
+        abort(); // This should be eliminated as unreachable, unless a programming error has occured
+#endif
     }
 
     return ESP_OK;
@@ -117,7 +124,11 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
         gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     } else {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
         rtc_gpio_pulldown_en(gpio_num);
+#else
+        abort(); // This should be eliminated as unreachable, unless a programming error has occured
+#endif
     }
 
     return ESP_OK;
@@ -132,7 +143,11 @@ esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
         gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     } else {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
         rtc_gpio_pulldown_dis(gpio_num);
+#else
+        abort(); // This should be eliminated as unreachable, unless a programming error has occured
+#endif
     }
 
     return ESP_OK;
@@ -326,9 +341,11 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
         if (((gpio_pin_mask >> io_num) & BIT(0))) {
             assert(io_reg != (intptr_t)NULL);
 
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
             if (rtc_gpio_is_valid_gpio(io_num)) {
                 rtc_gpio_deinit(io_num);
             }
+#endif
 
             if ((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
                 input_en = 1;
@@ -576,7 +593,11 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng
         gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     } else {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
         ret = rtc_gpio_set_drive_capability(gpio_num, strength);
+#else
+        abort(); // This should be eliminated as unreachable, unless a programming error has occured
+#endif
     }
 
     return ret;
@@ -593,7 +614,11 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
         gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     } else {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
         ret = rtc_gpio_get_drive_capability(gpio_num, strength);
+#else
+        abort(); // This should be eliminated as unreachable, unless a programming error has occured
+#endif
     }
 
     return ret;
diff --git a/components/driver/i2c.c b/components/driver/i2c.c
index cdcf713058..b090ad0a69 100644
--- a/components/driver/i2c.c
+++ b/components/driver/i2c.c
@@ -20,10 +20,8 @@
 #include "malloc.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/task.h"
 #include "freertos/ringbuf.h"
-#include "soc/dport_reg.h"
 #include "esp_pm.h"
 #include "soc/soc_memory_layout.h"
 #include "hal/i2c_hal.h"
@@ -176,7 +174,9 @@ typedef struct
 
 static i2c_context_t i2c_context[I2C_NUM_MAX] = {
     I2C_CONTEX_INIT_DEF(I2C_NUM_0),
+#if I2C_NUM_MAX > 1
     I2C_CONTEX_INIT_DEF(I2C_NUM_1),
+#endif
 };
 
 // i2c clock characteristic, The order is the same as i2c_sclk_t.
diff --git a/components/driver/i2s.c b/components/driver/i2s.c
index b22e74fbde..3c609336e6 100644
--- a/components/driver/i2s.c
+++ b/components/driver/i2s.c
@@ -19,19 +19,19 @@
 
 #include "freertos/FreeRTOS.h"
 #include "freertos/queue.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/semphr.h"
 
 #include "soc/lldesc.h"
 #include "driver/gpio.h"
 #include "driver/i2s.h"
-
 #if SOC_I2S_SUPPORTS_ADC_DAC
 #include "driver/dac.h"
 #include "hal/i2s_hal.h"
 #include "adc1_private.h"
 #endif
 
+#include "soc/rtc.h"
+
 #include "esp_intr_alloc.h"
 #include "esp_err.h"
 #include "esp_attr.h"
@@ -40,6 +40,8 @@
 #include "esp_efuse.h"
 #include "esp_rom_gpio.h"
 
+#include "sdkconfig.h"
+
 static const char* I2S_TAG = "I2S";
 
 #define I2S_CHECK(a, str, ret) if (!(a)) {                                              \
diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h
index ef5406ab70..3f382d4931 100644
--- a/components/driver/include/driver/gpio.h
+++ b/components/driver/include/driver/gpio.h
@@ -31,6 +31,8 @@
 #include "esp32/rom/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/gpio.h"
 #endif
 
 #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
diff --git a/components/driver/include/driver/i2c.h b/components/driver/include/driver/i2c.h
index 9b4107865f..30488fc570 100644
--- a/components/driver/include/driver/i2c.h
+++ b/components/driver/include/driver/i2c.h
@@ -24,7 +24,6 @@ extern "C" {
 #include "esp_intr_alloc.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/task.h"
 #include "freertos/queue.h"
 #include "freertos/ringbuf.h"
diff --git a/components/driver/include/driver/rtc_io.h b/components/driver/include/driver/rtc_io.h
index c6127e666f..ea8878223c 100644
--- a/components/driver/include/driver/rtc_io.h
+++ b/components/driver/include/driver/rtc_io.h
@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include "esp_err.h"
 #include "driver/gpio.h"
+#include "soc/soc_caps.h"
 #include "soc/rtc_io_periph.h"
 #include "hal/rtc_io_types.h"
 #ifdef __cplusplus
@@ -32,8 +33,11 @@ extern "C" {
  */
 static inline bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
 {
-    return (gpio_num < GPIO_PIN_COUNT
-        && rtc_io_num_map[gpio_num] >= 0);
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+    return (gpio_num < GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0);
+#else
+    return false;
+#endif
 }
 
 #define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio()
@@ -48,9 +52,15 @@ static inline bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
  */
 static inline int rtc_io_number_get(gpio_num_t gpio_num)
 {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
     return rtc_io_num_map[gpio_num];
+#else
+    return gpio_num;
+#endif
 }
 
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+
 /**
  * @brief Init a GPIO as RTC GPIO
  *
@@ -186,6 +196,34 @@ esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num);
  */
 esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num);
 
+/**
+ * @brief Set RTC GPIO pad drive capability
+ *
+ * @param gpio_num GPIO number, only support output GPIOs
+ * @param strength Drive capability of the pad
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength);
+
+/**
+ * @brief Get RTC GPIO pad drive capability
+ *
+ * @param gpio_num GPIO number, only support output GPIOs
+ * @param strength Pointer to accept drive capability of the pad
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
+
+#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+
+#if SOC_RTCIO_HOLD_SUPPORTED
+
 /**
  * @brief Enable hold function on an RTC IO pad
  *
@@ -249,29 +287,9 @@ esp_err_t rtc_gpio_force_hold_all(void);
  */
 esp_err_t rtc_gpio_force_hold_dis_all(void);
 
-/**
- * @brief Set RTC GPIO pad drive capability
- *
- * @param gpio_num GPIO number, only support output GPIOs
- * @param strength Drive capability of the pad
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength);
+#endif // SOC_RTCIO_HOLD_SUPPORTED
 
-/**
- * @brief Get RTC GPIO pad drive capability
- *
- * @param gpio_num GPIO number, only support output GPIOs
- * @param strength Pointer to accept drive capability of the pad
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
+#if SOC_RTCIO_WAKE_SUPPORTED
 
 /**
  * @brief Enable wakeup from sleep mode using specific GPIO
@@ -294,6 +312,8 @@ esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
  */
 esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num);
 
+#endif // SOC_RTCIO_WAKE_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/driver/include/driver/uart.h b/components/driver/include/driver/uart.h
index 4ca05e366b..7269b3fa14 100644
--- a/components/driver/include/driver/uart.h
+++ b/components/driver/include/driver/uart.h
@@ -23,7 +23,6 @@ extern "C" {
 #include "soc/soc_caps.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/task.h"
 #include "freertos/queue.h"
 #include "freertos/ringbuf.h"
diff --git a/components/driver/ledc.c b/components/driver/ledc.c
index aab6324aa6..69eae2c1ea 100644
--- a/components/driver/ledc.c
+++ b/components/driver/ledc.c
@@ -15,7 +15,6 @@
 #include <esp_types.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
 #include "esp_log.h"
 #include "soc/gpio_periph.h"
 #include "soc/ledc_periph.h"
diff --git a/components/driver/pcnt.c b/components/driver/pcnt.c
index 2c637a2486..e04e177242 100644
--- a/components/driver/pcnt.c
+++ b/components/driver/pcnt.c
@@ -11,7 +11,6 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "esp_log.h"
diff --git a/components/driver/rtc_io.c b/components/driver/rtc_io.c
index 16b4bc9adf..47f8bc826a 100644
--- a/components/driver/rtc_io.c
+++ b/components/driver/rtc_io.c
@@ -34,6 +34,8 @@ extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate posi
 #define RTCIO_ENTER_CRITICAL()  portENTER_CRITICAL(&rtc_spinlock)
 #define RTCIO_EXIT_CRITICAL()  portEXIT_CRITICAL(&rtc_spinlock)
 
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+
 /*---------------------------------------------------------------
                         RTC IO
 ---------------------------------------------------------------*/
@@ -156,6 +158,8 @@ esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num)
     return ESP_OK;
 }
 
+#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+
 esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num)
 {
     RTCIO_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTCIO number error", ESP_ERR_INVALID_ARG);
diff --git a/components/driver/rtc_module.c b/components/driver/rtc_module.c
index 1bb405ca6d..f19d2b6899 100644
--- a/components/driver/rtc_module.c
+++ b/components/driver/rtc_module.c
@@ -23,7 +23,6 @@
 #include "soc/rtc.h"
 #include "soc/periph_defs.h"
 #include "freertos/FreeRTOS.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/semphr.h"
 #include "freertos/timers.h"
 #include "esp_intr_alloc.h"
diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c
index 32b30b69a8..1c46a5775d 100644
--- a/components/driver/spi_common.c
+++ b/components/driver/spi_common.c
@@ -23,7 +23,6 @@
 #include "esp_err.h"
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
-#include "soc/dport_reg.h"
 #include "soc/lldesc.h"
 #include "driver/gpio.h"
 #include "driver/periph_ctrl.h"
@@ -33,9 +32,14 @@
 #include "hal/spi_hal.h"
 #include "esp_rom_gpio.h"
 
+#if CONFIG_IDF_TARGET_ESP32
+#include "soc/dport_reg.h"
+#endif
+
 //This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
 #if SOC_GDMA_SUPPORTED
 #include "hal/gdma_ll.h"
+#include "soc/spi_caps.h"
 
 #define spi_dma_set_rx_channel_priority(gdma_chan, priority)       gdma_ll_rx_set_priority(&GDMA, gdma_chan, priority);
 #define spi_dma_set_tx_channel_priority(gdma_chan, priority)       gdma_ll_tx_set_priority(&GDMA, gdma_chan, priority);
@@ -134,7 +138,7 @@ int spicommon_irqdma_source_for_host(spi_host_device_t host)
     return spi_periph_signal[host].irq_dma;
 }
 
-static inline uint32_t get_dma_periph(int dma_chan)
+static inline periph_module_t get_dma_periph(int dma_chan)
 {
 #if CONFIG_IDF_TARGET_ESP32S2
     if (dma_chan == 1) {
@@ -223,9 +227,11 @@ void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan)
     if (dma_chan == 1) {
         gdma_chan = SOC_GDMA_SPI2_DMA_CHANNEL;
         periph_id = GDMA_LL_TRIG_SRC_SPI2;
+#ifdef GDMA_LL_TRIG_SRC_SPI3
     } else if (dma_chan == 2) {
         gdma_chan = SOC_GDMA_SPI3_DMA_CHANNEL;
         periph_id = GDMA_LL_TRIG_SRC_SPI3;
+#endif
     } else {
         abort();
     }
@@ -240,15 +246,25 @@ void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan)
 static bool bus_uses_iomux_pins(spi_host_device_t host, const spi_bus_config_t* bus_config)
 {
     if (bus_config->sclk_io_num>=0 &&
-        bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) return false;
+        bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) {
+            return false;
+        }
     if (bus_config->quadwp_io_num>=0 &&
-        bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) return false;
+        bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) {
+            return false;
+        }
     if (bus_config->quadhd_io_num>=0 &&
-        bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) return false;
+        bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) {
+            return false;
+            }
     if (bus_config->mosi_io_num >= 0 &&
-        bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) return false;
+        bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) {
+            return false;
+        }
     if (bus_config->miso_io_num>=0 &&
-        bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) return false;
+        bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) {
+            return false;
+        }
 
     return true;
 }
@@ -441,11 +457,7 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num,
     if (!force_gpio_matrix && cs_io_num == spi_periph_signal[host].spics0_iomux_pin && cs_num == 0) {
         //The cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define.
         gpio_iomux_in(cs_io_num, spi_periph_signal[host].spics_in);
-#if CONFIG_IDF_TARGET_ESP32
         gpio_iomux_out(cs_io_num, spi_periph_signal[host].func, false);
-#elif CONFIG_IDF_TARGET_ESP32S2
-        gpio_iomux_out(cs_io_num, spi_periph_signal[host].func, false);
-#endif
     } else {
         //Use GPIO matrix
         if (GPIO_IS_VALID_OUTPUT_GPIO(cs_io_num)) {
diff --git a/components/driver/spi_master.c b/components/driver/spi_master.c
index 790506e7aa..00325c24d9 100644
--- a/components/driver/spi_master.c
+++ b/components/driver/spi_master.c
@@ -128,6 +128,7 @@ We have two bits to control the interrupt:
 #include "soc/soc_memory_layout.h"
 #include "driver/gpio.h"
 #include "hal/spi_hal.h"
+#include "esp_heap_caps.h"
 
 
 typedef struct spi_device_t spi_device_t;
@@ -189,8 +190,8 @@ static inline bool is_valid_host(spi_host_device_t host)
 {
 #if CONFIG_IDF_TARGET_ESP32
     return host >= SPI1_HOST && host <= SPI3_HOST;
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
-// SPI_HOST (SPI1_HOST) is not supported by the SPI Master driver on ESP32-S2
+#else
+// SPI_HOST (SPI1_HOST) is not supported by the SPI Master driver on ESP32-S2 and later
     return host >= SPI2_HOST && host <= SPI3_HOST;
 #endif
 }
diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c
index 9059c4e924..91f512be2f 100644
--- a/components/driver/spi_slave.c
+++ b/components/driver/spi_slave.c
@@ -30,7 +30,6 @@
 #include "hal/spi_slave_hal.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/task.h"
 #include "sdkconfig.h"
 
@@ -82,8 +81,8 @@ static inline bool is_valid_host(spi_host_device_t host)
 {
 #if CONFIG_IDF_TARGET_ESP32
     return host >= SPI1_HOST && host <= SPI3_HOST;
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
-// SPI_HOST (SPI1_HOST) is not supported by the SPI Slave driver on ESP32-S2
+#else
+// SPI_HOST (SPI1_HOST) is not supported by the SPI Slave driver on ESP32-S2 & later
     return host >= SPI2_HOST && host <= SPI3_HOST;
 #endif
 }
diff --git a/components/driver/test/include/test/test_adc_dac_dma.h b/components/driver/test/include/test/test_adc_dac_dma.h
index 8e3d0e3d31..1e7483dd31 100644
--- a/components/driver/test/include/test/test_adc_dac_dma.h
+++ b/components/driver/test/include/test/test_adc_dac_dma.h
@@ -14,7 +14,7 @@
 
 #pragma once
 
-#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2
+/* Common header for ESP32-S2 ADC/DAC tests */
 
 /**
  * SPI DMA type.
@@ -63,5 +63,3 @@ void adc_dac_dma_linker_stop(spi_dma_link_type_t type);
  * Deinit SPI3 DMA. Disable interrupt, stop DMA trans.
  */
 void adc_dac_dma_linker_deinit(void);
-
-#endif
diff --git a/components/driver/test/param_test/param_test.c b/components/driver/test/param_test/param_test.c
index 0cc34673fd..85e17626eb 100644
--- a/components/driver/test/param_test/param_test.c
+++ b/components/driver/test/param_test/param_test.c
@@ -1,3 +1,5 @@
+#include <stddef.h>
+#include <stdlib.h>
 #include "param_test.h"
 #include "esp_log.h"
 
diff --git a/components/driver/test/test_adc2_with_wifi.c b/components/driver/test/test_adc2_with_wifi.c
index 1b709665b2..1c5419c40c 100644
--- a/components/driver/test/test_adc2_with_wifi.c
+++ b/components/driver/test/test_adc2_with_wifi.c
@@ -3,7 +3,6 @@
 */
 #include "esp_system.h"
 #include "driver/adc.h"
-#include "driver/dac.h"
 #include "unity.h"
 #include "esp_system.h"
 #include "esp_event.h"
@@ -12,7 +11,8 @@
 #include "nvs_flash.h"
 #include "test_utils.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)
+#include "driver/dac.h"
 
 static const char* TAG = "test_adc2";
 
diff --git a/components/driver/test/test_adc_common.c b/components/driver/test/test_adc_common.c
index 123f35d55d..792bae4940 100644
--- a/components/driver/test/test_adc_common.c
+++ b/components/driver/test/test_adc_common.c
@@ -3,7 +3,6 @@
 */
 #include "esp_system.h"
 #include "driver/adc.h"
-#include "driver/dac.h"
 #include "driver/rtc_io.h"
 #include "driver/gpio.h"
 #include "unity.h"
@@ -15,7 +14,8 @@
 #include "test_utils.h"
 #include "soc/adc_periph.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3,ESP32C3)
+#include "driver/dac.h"
 
 static const char *TAG = "test_adc";
 
diff --git a/components/driver/test/test_dac.c b/components/driver/test/test_dac.c
index 430f1c6c45..31f0e8e142 100644
--- a/components/driver/test/test_dac.c
+++ b/components/driver/test/test_dac.c
@@ -4,7 +4,6 @@
 #include "esp_system.h"
 
 #include "driver/adc.h"
-#include "driver/dac.h"
 #include "unity.h"
 #include "esp_system.h"
 #include "esp_event.h"
@@ -14,7 +13,8 @@
 #include "test_utils.h"
 #include "driver/i2s.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+#if !DISABLED_FOR_TARGETS(ESP32C3) && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+#include "driver/dac.h"
 #include "esp_adc_cal.h"
 
 static const char *TAG = "test_dac";
@@ -182,4 +182,4 @@ TEST_CASE("esp32s2 adc2-dac with adc2 calibration", "[adc-dac]")
 }
 #endif
 
-#endif
+#endif // !DISABLED_FOR_TARGETS(ESP32C3) && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c
index babc18d6ca..b8bf98934a 100644
--- a/components/driver/test/test_gpio.c
+++ b/components/driver/test/test_gpio.c
@@ -16,7 +16,7 @@
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)
 
 #define WAKE_UP_IGNORE 1  // gpio_wakeup function development is not completed yet, set it deprecated.
 
diff --git a/components/driver/test/test_rmt.c b/components/driver/test/test_rmt.c
index 9ae1b5d74e..1cc4600ef4 100644
--- a/components/driver/test/test_rmt.c
+++ b/components/driver/test/test_rmt.c
@@ -217,7 +217,7 @@ static void do_nec_tx_rx(uint32_t flags)
 {
     RingbufHandle_t rb = NULL;
     rmt_item32_t *items = NULL;
-    uint32_t length = 0;
+    size_t length = 0;
     uint32_t addr = 0x10;
     uint32_t cmd = 0x20;
     bool repeat = false;
@@ -313,7 +313,7 @@ TEST_CASE("RMT TX stop", "[rmt]")
 {
     RingbufHandle_t rb = NULL;
     rmt_item32_t *frames = NULL;
-    uint32_t length = 0;
+    size_t length = 0;
     uint32_t count = 10;
     uint32_t addr = 0x10;
     uint32_t cmd = 0x20;
@@ -409,7 +409,7 @@ TEST_CASE("RMT Ping-Pong operation", "[rmt]")
         TEST_ESP_OK(rmt_write_items(tx_channel, frames, size, true));
 
         // parse received data
-        uint32_t length = 0;
+        size_t length = 0;
         rmt_item32_t *items = (rmt_item32_t *) xRingbufferReceive(rb, &length, 1000);
         if (items) {
             vRingbufferReturnItem(rb, (void *) items);
@@ -490,7 +490,7 @@ TEST_CASE("RMT TX loop", "[rmt]")
 {
     RingbufHandle_t rb = NULL;
     rmt_item32_t *items = NULL;
-    uint32_t length = 0;
+    size_t length = 0;
     uint32_t addr = 0x10;
     uint32_t cmd = 0x20;
     bool repeat = false;
diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c
index 4581b76206..1846097676 100644
--- a/components/driver/test/test_spi_master.c
+++ b/components/driver/test/test_spi_master.c
@@ -11,7 +11,6 @@
 #include "freertos/task.h"
 #include "freertos/semphr.h"
 #include "freertos/queue.h"
-#include "freertos/xtensa_api.h"
 #include "unity.h"
 #include "driver/spi_master.h"
 #include "driver/spi_slave.h"
@@ -40,7 +39,7 @@ static void check_spi_pre_n_for(int clk, int pre, int n)
         .clock_speed_hz=clk,
         .duty_cycle_pos=128,
         .mode=0,
-        .spics_io_num=21,
+        .spics_io_num=PIN_NUM_CS,
         .queue_size=3
     };
     char sendbuf[16]="";
@@ -65,7 +64,6 @@ static void check_spi_pre_n_for(int clk, int pre, int n)
     TEST_ASSERT(ret==ESP_OK);
 }
 
-
 TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
 {
     spi_bus_config_t buscfg={
@@ -86,7 +84,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
     check_spi_pre_n_for(100000, 16, 50);
     check_spi_pre_n_for(333333, 4, 60);
     check_spi_pre_n_for(900000, 2, 44);
-    check_spi_pre_n_for(1, 8192, 64); //Actually should generate the minimum clock speed, 152Hz
+    check_spi_pre_n_for(1, SOC_SPI_MAX_PRE_DIVIDER, 64); //Actually should generate the minimum clock speed, 152Hz
     check_spi_pre_n_for(26000000, 1, 3);
 
     ret=spi_bus_free(TEST_SPI_HOST);
diff --git a/components/driver/test/test_spi_sio.c b/components/driver/test/test_spi_sio.c
index 9146b417e8..92aef5b4f1 100644
--- a/components/driver/test/test_spi_sio.c
+++ b/components/driver/test/test_spi_sio.c
@@ -12,7 +12,6 @@
 #include "freertos/task.h"
 #include "freertos/semphr.h"
 #include "freertos/queue.h"
-#include "freertos/xtensa_api.h"
 #include "unity.h"
 #include "driver/spi_master.h"
 #include "driver/spi_slave.h"
diff --git a/components/driver/uart.c b/components/driver/uart.c
index 8ef0977859..77d8039369 100644
--- a/components/driver/uart.c
+++ b/components/driver/uart.c
@@ -20,7 +20,6 @@
 #include "malloc.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
 #include "freertos/ringbuf.h"
 #include "hal/uart_hal.h"
 #include "soc/uart_periph.h"
@@ -38,6 +37,8 @@
 #include "esp32s2/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
 #endif
 
 #ifdef CONFIG_UART_ISR_IN_IRAM
diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h
index 84d03c5a22..bebfd64403 100644
--- a/components/efuse/include/esp_efuse.h
+++ b/components/efuse/include/esp_efuse.h
@@ -29,6 +29,8 @@ extern "C" {
 #include "esp32s2/esp_efuse.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/esp_efuse.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/esp_efuse.h"
 #endif
 
 #define ESP_ERR_EFUSE                              0x1600                     /*!< Base error code for efuse api. */
diff --git a/components/efuse/private_include/esp_efuse_utility.h b/components/efuse/private_include/esp_efuse_utility.h
index 6999127b66..5345b0bbab 100644
--- a/components/efuse/private_include/esp_efuse_utility.h
+++ b/components/efuse/private_include/esp_efuse_utility.h
@@ -29,6 +29,8 @@ extern "C" {
 #include "esp32s2/esp_efuse_utility.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/esp_efuse_utility.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/esp_efuse_utility.h"
 #endif
 
 /**
diff --git a/components/esp_system/include/esp_system.h b/components/esp_system/include/esp_system.h
index c054ac3c96..ea3e914159 100644
--- a/components/esp_system/include/esp_system.h
+++ b/components/esp_system/include/esp_system.h
@@ -262,6 +262,7 @@ typedef enum {
     CHIP_ESP32  = 1, //!< ESP32
     CHIP_ESP32S2 = 2, //!< ESP32-S2
     CHIP_ESP32S3 = 4, //!< ESP32-S3
+    CHIP_ESP32C3 = 5, //!< ESP32-C3
 } esp_chip_model_t;
 
 /* Chip feature flags, used in esp_chip_info_t */
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 43209c267b..bbdc7e0f0c 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -30,6 +30,7 @@
 #include "sdkconfig.h"
 
 #if CONFIG_IDF_TARGET_ESP32
+#include "soc/dport_reg.h"
 #include "esp32/rtc.h"
 #include "esp32/cache_err_int.h"
 #include "esp32/rom/cache.h"
@@ -55,6 +56,13 @@
 #include "esp32s3/memprot.h"
 #include "soc/assist_debug_reg.h"
 #include "soc/cache_memory.h"
+#include "soc/system_reg.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rtc.h"
+#include "esp32c3/cache_err_int.h"
+#include "esp32s3/rom/cache.h"
+#include "esp32c3/rom/rtc.h"
+#include "soc/cache_memory.h"
 #endif
 
 #include "bootloader_flash_config.h"
@@ -64,7 +72,6 @@
 #include "hal/rtc_io_hal.h"
 #include "hal/wdt_hal.h"
 #include "soc/rtc.h"
-#include "soc/dport_reg.h"
 #include "soc/efuse_reg.h"
 #include "soc/periph_defs.h"
 #include "soc/cpu.h"
@@ -434,7 +441,7 @@ void IRAM_ATTR call_start_cpu0(void)
 
 #ifdef CONFIG_ESP_CONSOLE_UART
     uint32_t clock_hz = rtc_clk_apb_freq_get();
-#if CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
     clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
 #endif
     esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c
index e23149d511..a708667f23 100644
--- a/components/esp_system/sleep_modes.c
+++ b/components/esp_system/sleep_modes.c
@@ -13,6 +13,7 @@
 // limitations under the License.
 
 #include <stddef.h>
+#include <string.h>
 #include <sys/lock.h>
 #include <sys/param.h>
 
@@ -27,19 +28,23 @@
 #include "freertos/task.h"
 #include "driver/touch_sensor.h"
 #include "driver/touch_sensor_common.h"
+#include "soc/soc_caps.h"
+
 #include "driver/rtc_io.h"
+#include "hal/rtc_io_hal.h"
+
 #include "driver/uart.h"
 
 #include "soc/cpu.h"
 #include "soc/rtc.h"
-#include "soc/dport_reg.h"
 #include "soc/soc_caps.h"
 
 #include "hal/wdt_hal.h"
-#include "hal/rtc_io_hal.h"
 #include "hal/rtc_hal.h"
 #include "hal/uart_hal.h"
+#if SOC_TOUCH_SENSOR_NUM > 0
 #include "hal/touch_sensor_hal.h"
+#endif
 #include "hal/clk_gate_ll.h"
 
 #include "sdkconfig.h"
@@ -59,6 +64,11 @@
 #include "esp32s3/rom/cache.h"
 #include "esp32s3/rom/rtc.h"
 #include "soc/extmem_reg.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
+#include "esp32s3/rom/cache.h"
+#include "esp32c3/rom/rtc.h"
+#include "soc/extmem_reg.h"
 #endif
 
 // If light sleep time is less than that, don't power down flash
@@ -73,6 +83,8 @@
 #define DEFAULT_CPU_FREQ_MHZ        CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
 #elif CONFIG_IDF_TARGET_ESP32S3
 #define DEFAULT_CPU_FREQ_MHZ        CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define DEFAULT_CPU_FREQ_MHZ        CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
 #endif
 
 #if defined(CONFIG_IDF_TARGET_ESP32)
@@ -93,6 +105,15 @@
 #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
 #endif // CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS
 
+#elif defined(CONFIG_IDF_TARGET_ESP32C3)
+#ifdef CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS
+#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ)
+#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ)
+#else
+#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ)
+#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ)
+#endif // CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS
+
 #else // other target
 #define LIGHT_SLEEP_TIME_OVERHEAD_US 0
 #define DEEP_SLEEP_TIME_OVERHEAD_US 0
@@ -678,18 +699,22 @@ static void ext1_wakeup_prepare(void)
         if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
             continue;
         }
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
         // Route pad to RTC
         rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_RTC);
         // set input enable in sleep mode
         rtcio_hal_input_enable(rtc_pin);
+#endif
 
         // Pad configuration depends on RTC_PERIPH state in sleep mode
         if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
             // RTC_PERIPH will be powered down, so RTC_IO_ registers will
             // loose their state. Lock pad configuration.
             // Pullups/pulldowns also need to be disabled.
             rtcio_hal_pullup_disable(rtc_pin);
             rtcio_hal_pulldown_disable(rtc_pin);
+#endif
             rtcio_hal_hold_enable(rtc_pin);
         }
         // Keep track of pins which are processed to bail out early
@@ -725,10 +750,12 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void)
 
 esp_err_t esp_sleep_enable_gpio_wakeup(void)
 {
+#if CONFIG_IDF_TARGET_ESP32
     if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
         ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
         return ESP_ERR_INVALID_STATE;
     }
+#endif
     s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
     return ESP_OK;
 }
@@ -780,8 +807,10 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
         return ESP_SLEEP_WAKEUP_TIMER;
     } else if (wakeup_cause & RTC_TOUCH_TRIG_EN) {
         return ESP_SLEEP_WAKEUP_TOUCHPAD;
+#if SOC_ULP_SUPPORTED
     } else if (wakeup_cause & RTC_ULP_TRIG_EN) {
         return ESP_SLEEP_WAKEUP_ULP;
+#endif
     } else if (wakeup_cause & RTC_GPIO_TRIG_EN) {
         return ESP_SLEEP_WAKEUP_GPIO;
     } else if (wakeup_cause & (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN)) {
@@ -818,6 +847,7 @@ static uint32_t get_power_down_flags(void)
     // If there is any data placed into .rtc.data or .rtc.bss segments, and
     // RTC_SLOW_MEM is Auto, keep it powered up as well.
 
+#if SOC_RTC_SLOW_MEM_SUPPORTED && SOC_ULP_SUPPORTED
     // Labels are defined in the linker script
     extern int _rtc_slow_length;
 
@@ -826,6 +856,7 @@ static uint32_t get_power_down_flags(void)
              (s_config.wakeup_triggers & RTC_ULP_TRIG_EN))) {
         s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON;
     }
+#endif
 
     // RTC_FAST_MEM is needed for deep sleep stub.
     // If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub
@@ -839,9 +870,13 @@ static uint32_t get_power_down_flags(void)
     // RTC_PERIPH is needed for EXT0 wakeup and GPIO wakeup.
     // If RTC_PERIPH is auto, and EXT0/GPIO aren't enabled, power down RTC_PERIPH.
     if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
+        uint32_t wakeup_source = RTC_TOUCH_TRIG_EN;
+#if SOC_ULP_SUPPORTED
+        wakeup_source |= RTC_ULP_TRIG_EN;
+#endif
         if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) {
             s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
-        } else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
+        } else if (s_config.wakeup_triggers & wakeup_source) {
             // In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH
             // prevents ULP timer and touch FSMs from working correctly.
             s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
@@ -853,19 +888,22 @@ static uint32_t get_power_down_flags(void)
     }
 
     const char* option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
-    ESP_LOGD(TAG, "RTC_PERIPH: %s, RTC_SLOW_MEM: %s, RTC_FAST_MEM: %s",
-            option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]],
-            option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]],
-            option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
+    ESP_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]]);
+#if SOC_RTC_SLOW_MEM_SUPPORTED
+    ESP_LOGD(TAG, "RTC_SLOW_MEM: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]]);
+#endif
+    ESP_LOGD(TAG, "RTC_FAST_MEM: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
 
     // Prepare flags based on the selected options
     uint32_t pd_flags = 0;
     if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) {
         pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM;
     }
+#if SOC_RTC_SLOW_MEM_SUPPORTED
     if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) {
         pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM;
     }
+#endif
     if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
         pd_flags |= RTC_SLEEP_PD_RTC_PERIPH;
     }
diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c
index 0f16477400..09cd07ef8b 100644
--- a/components/esp_system/startup.c
+++ b/components/esp_system/startup.c
@@ -70,6 +70,9 @@
 #include "esp32s3/clk.h"
 #include "esp32s3/spiram.h"
 #include "esp32s3/brownout.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
+#include "esp32c3/brownout.h"
 #endif
 /***********************************************/
 
diff --git a/components/esp_system/system_api.c b/components/esp_system/system_api.c
index 66f30f9704..04b84c573f 100644
--- a/components/esp_system/system_api.c
+++ b/components/esp_system/system_api.c
@@ -12,6 +12,8 @@
 #include "esp32s2/memprot.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/memprot.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/memprot.h"
 #endif
 
 
diff --git a/components/esp_system/system_time.c b/components/esp_system/system_time.c
index a53087ef26..d8c16415fd 100644
--- a/components/esp_system/system_time.c
+++ b/components/esp_system/system_time.c
@@ -27,6 +27,8 @@
 #include "esp32s2/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rtc.h"
 #endif
 
 #include "esp_private/startup_internal.h"
diff --git a/components/esp_timer/src/esp_timer.c b/components/esp_timer/src/esp_timer.c
index d3ccb4f59a..3ce7399ddc 100644
--- a/components/esp_timer/src/esp_timer.c
+++ b/components/esp_timer/src/esp_timer.c
@@ -37,6 +37,8 @@
 #include "esp32s2/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rtc.h"
 #endif
 
 #include "sdkconfig.h"
diff --git a/components/esp_timer/test/test_ets_timer.c b/components/esp_timer/test/test_ets_timer.c
index 75f92e830d..a17add857f 100644
--- a/components/esp_timer/test/test_ets_timer.c
+++ b/components/esp_timer/test/test_ets_timer.c
@@ -7,12 +7,15 @@
 #include "freertos/task.h"
 #include "freertos/semphr.h"
 #include "esp_spi_flash.h"
+#include "esp_rom_sys.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/ets_sys.h"  // for ETSTimer type
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/ets_sys.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/ets_sys.h"
 #endif
 
 TEST_CASE("ets_timer produces correct delay", "[ets_timer]")
@@ -26,7 +29,7 @@ TEST_CASE("ets_timer produces correct delay", "[ets_timer]")
     ETSTimer timer1 = {0};
 
     const int delays_ms[] = {20, 100, 200, 250};
-    const size_t delays_count = sizeof(delays_ms)/sizeof(delays_ms[0]);
+    const size_t delays_count = sizeof(delays_ms) / sizeof(delays_ms[0]);
 
     for (size_t i = 0; i < delays_count; ++i) {
         struct timeval tv_end = {0};
@@ -39,7 +42,7 @@ TEST_CASE("ets_timer produces correct delay", "[ets_timer]")
 
         vTaskDelay(delays_ms[i] * 2 / portTICK_PERIOD_MS);
         int32_t ms_diff = (tv_end.tv_sec - tv_start.tv_sec) * 1000 +
-                (tv_end.tv_usec - tv_start.tv_usec) / 1000;
+                          (tv_end.tv_usec - tv_start.tv_usec) / 1000;
         printf("%d %d\n", delays_ms[i], ms_diff);
 
         TEST_ASSERT_INT32_WITHIN(portTICK_PERIOD_MS, delays_ms[i], ms_diff);
@@ -54,24 +57,23 @@ TEST_CASE("periodic ets_timer produces correct delays", "[ets_timer]")
 #define NUM_INTERVALS 16
 
     typedef struct {
-        ETSTimer* timer;
+        ETSTimer *timer;
         size_t cur_interval;
         int intervals[NUM_INTERVALS];
         struct timeval tv_start;
     } test_args_t;
 
-    void timer_func(void* arg)
-    {
-        test_args_t* p_args = (test_args_t*) arg;
+    void timer_func(void *arg) {
+        test_args_t *p_args = (test_args_t *) arg;
         struct timeval tv_now;
         gettimeofday(&tv_now, NULL);
         int32_t ms_diff = (tv_now.tv_sec - p_args->tv_start.tv_sec) * 1000 +
-                        (tv_now.tv_usec - p_args->tv_start.tv_usec) / 1000;
+                          (tv_now.tv_usec - p_args->tv_start.tv_usec) / 1000;
         printf("timer #%d %dms\n", p_args->cur_interval, ms_diff);
         p_args->intervals[p_args->cur_interval++] = ms_diff;
         // Deliberately make timer handler run longer.
         // We check that this doesn't affect the result.
-        esp_rom_delay_us(10*1000);
+        esp_rom_delay_us(10 * 1000);
         if (p_args->cur_interval == NUM_INTERVALS) {
             printf("done\n");
             ets_timer_disarm(p_args->timer);
diff --git a/components/freertos/port/riscv/port.c b/components/freertos/port/riscv/port.c
index a30d225263..6c25ad11ad 100644
--- a/components/freertos/port/riscv/port.c
+++ b/components/freertos/port/riscv/port.c
@@ -80,6 +80,7 @@
 #include "sdkconfig.h"
 #include "portmacro.h"
 #include "riscv/interrupt.h"
+#include "riscv/rvruntime-frames.h"
 #include "soc/periph_defs.h"
 #include "soc/system_reg.h"
 #include "soc/interrupt_reg.h"
@@ -220,8 +221,9 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC
 
     /* Simulate the stack frame as it would be created by a context switch
     interrupt. */
+    pxTopOfStack -= RV_STK_FRMSZ;
+
     RvExcFrame *frame = (RvExcFrame *)pxTopOfStack;
-    frame--;
     frame->ra = (UBaseType_t)prvTaskExitError;
     frame->mepc = (UBaseType_t)pxCode;
     frame->a0 = (UBaseType_t)pvParameters;
diff --git a/components/freertos/port/xtensa/include/freertos/FreeRTOSConfig.h b/components/freertos/port/xtensa/include/freertos/FreeRTOSConfig.h
index 0e2b1719a7..af703d8d62 100644
--- a/components/freertos/port/xtensa/include/freertos/FreeRTOSConfig.h
+++ b/components/freertos/port/xtensa/include/freertos/FreeRTOSConfig.h
@@ -127,6 +127,8 @@ int xt_clock_freq(void) __attribute__((deprecated));
 #include "esp32s2/rom/ets_sys.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/ets_sys.h"
 #endif
 
 #if defined(CONFIG_FREERTOS_ASSERT_DISABLE)
diff --git a/components/heap/include/esp_heap_caps.h b/components/heap/include/esp_heap_caps.h
index 8f0654622d..5d6a94727e 100644
--- a/components/heap/include/esp_heap_caps.h
+++ b/components/heap/include/esp_heap_caps.h
@@ -40,6 +40,7 @@ extern "C" {
 #define MALLOC_CAP_INTERNAL         (1<<11) ///< Memory must be internal; specifically it should not disappear when flash/spiram cache is switched off
 #define MALLOC_CAP_DEFAULT          (1<<12) ///< Memory can be returned in a non-capability-specific memory allocation (e.g. malloc(), calloc()) call
 #define MALLOC_CAP_IRAM_8BIT        (1<<13) ///< Memory must be in IRAM and allow unaligned access
+#define MALLOC_CAP_RETENTION        (1<<14)
 
 #define MALLOC_CAP_INVALID          (1<<31) ///< Memory can't be used / list end marker
 
diff --git a/components/heap/multi_heap_platform.h b/components/heap/multi_heap_platform.h
index 24a1719af7..e6114a5e9d 100644
--- a/components/heap/multi_heap_platform.h
+++ b/components/heap/multi_heap_platform.h
@@ -92,8 +92,6 @@ inline static void multi_heap_assert(bool condition, const char *format, int lin
 
 #include <assert.h>
 
-typedef int multi_heap_lock_t;
-
 #define MULTI_HEAP_PRINTF printf
 #define MULTI_HEAP_STDERR_PRINTF(MSG, ...) fprintf(stderr, MSG, __VA_ARGS__)
 #define MULTI_HEAP_LOCK(PLOCK)  (void) (PLOCK)
diff --git a/components/idf_test/include/idf_performance.h b/components/idf_test/include/idf_performance.h
index 0dc7752668..2ec2f82198 100644
--- a/components/idf_test/include/idf_performance.h
+++ b/components/idf_test/include/idf_performance.h
@@ -125,7 +125,9 @@
 #endif
 
 // Some performance value based on the test against GD chip with single_core config.
-// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B in target file
+#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B
+#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B                  64900
+#endif
 // IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B in target file
 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB
 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB                 (475*1000)
diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h
index a6ac60ea79..4a132c7751 100644
--- a/components/log/include/esp_log.h
+++ b/components/log/include/esp_log.h
@@ -25,6 +25,8 @@
 #include "esp32s2/rom/ets_sys.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/ets_sys.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/components/mbedtls/port/esp32/bignum.c b/components/mbedtls/port/esp32/bignum.c
index 3a5649f66c..82bacfa591 100644
--- a/components/mbedtls/port/esp32/bignum.c
+++ b/components/mbedtls/port/esp32/bignum.c
@@ -22,6 +22,7 @@
  */
 
 #include "soc/hwcrypto_periph.h"
+#include "soc/dport_reg.h"
 #include "driver/periph_ctrl.h"
 #include <mbedtls/bignum.h>
 #include "bignum_impl.h"
diff --git a/components/mbedtls/port/esp_aes_xts.c b/components/mbedtls/port/esp_aes_xts.c
index d3a1566c5e..c2f5226421 100644
--- a/components/mbedtls/port/esp_aes_xts.c
+++ b/components/mbedtls/port/esp_aes_xts.c
@@ -44,6 +44,8 @@
 
 #if CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/aes.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/aes.h"
 #endif
 
 #if CONFIG_IDF_TARGET_ESP32S3
diff --git a/components/mbedtls/port/include/aes_alt.h b/components/mbedtls/port/include/aes_alt.h
index f313d508bd..ba63cd9202 100644
--- a/components/mbedtls/port/include/aes_alt.h
+++ b/components/mbedtls/port/include/aes_alt.h
@@ -34,6 +34,8 @@ extern "C" {
 #include "esp32s2/aes.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/aes.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/aes.h"
 #endif
 
 typedef esp_aes_context mbedtls_aes_context;
diff --git a/components/mbedtls/port/include/gcm_alt.h b/components/mbedtls/port/include/gcm_alt.h
index 9a79850c02..e395b8de94 100644
--- a/components/mbedtls/port/include/gcm_alt.h
+++ b/components/mbedtls/port/include/gcm_alt.h
@@ -29,8 +29,12 @@ extern "C" {
 
 #if defined(MBEDTLS_GCM_ALT)
 
-#if CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32C3
 #include "esp32s3/gcm.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/gcm.h"
+#endif
 
 
 typedef esp_gcm_context mbedtls_gcm_context;
@@ -44,7 +48,7 @@ typedef esp_gcm_context mbedtls_gcm_context;
 #define mbedtls_gcm_auth_decrypt    esp_aes_gcm_auth_decrypt
 #define mbedtls_gcm_crypt_and_tag   esp_aes_gcm_crypt_and_tag
 
-#endif // CONFIG_IDF_TARGET_ESP32S3
+#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
 
 #if CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/gcm.h"
diff --git a/components/mbedtls/port/sha/dma/sha.c b/components/mbedtls/port/sha/dma/sha.c
index 168f34cd46..8310edcb41 100644
--- a/components/mbedtls/port/sha/dma/sha.c
+++ b/components/mbedtls/port/sha/dma/sha.c
@@ -32,7 +32,6 @@
 #include "esp_log.h"
 #include "esp_crypto_lock.h"
 #include "soc/lldesc.h"
-#include "soc/dport_reg.h"
 #include "soc/cache_memory.h"
 #include "soc/periph_defs.h"
 
@@ -50,6 +49,8 @@
 #include "esp32s2/rom/cache.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32s3/rom/cache.h"
 #endif
 
 #if SOC_SHA_GENERAL_DMA
diff --git a/components/mdns/private_include/mdns_networking.h b/components/mdns/private_include/mdns_networking.h
index 12316f9edc..5a8156af93 100644
--- a/components/mdns/private_include/mdns_networking.h
+++ b/components/mdns/private_include/mdns_networking.h
@@ -19,7 +19,6 @@
 #include "lwip/priv/tcpip_priv.h"
 #include "esp_wifi.h"
 #include "esp_system.h"
-#include "esp_timer.h"
 #include "esp_event.h"
 #if CONFIG_ETH_ENABLED
 #include "esp_eth.h"
diff --git a/components/mdns/private_include/mdns_private.h b/components/mdns/private_include/mdns_private.h
index 3fa57e597e..60dfeb4ee5 100644
--- a/components/mdns/private_include/mdns_private.h
+++ b/components/mdns/private_include/mdns_private.h
@@ -16,6 +16,7 @@
 
 #include "esp_event_base.h"
 #include "esp_task.h"
+#include "esp_timer.h"
 
 //#define MDNS_ENABLE_DEBUG
 
diff --git a/components/newlib/port/esp_time_impl.c b/components/newlib/port/esp_time_impl.c
index 1f4d9334d0..63586257d5 100644
--- a/components/newlib/port/esp_time_impl.c
+++ b/components/newlib/port/esp_time_impl.c
@@ -39,6 +39,10 @@
 #include "esp32s3/rom/rtc.h"
 #include "esp32s3/clk.h"
 #include "esp32s3/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/rtc.h"
+#include "esp32c3/clk.h"
+#include "esp32c3/rtc.h"
 #endif
 
 
diff --git a/components/newlib/test/test_time.c b/components/newlib/test/test_time.c
index 361cba9b33..044c437f5c 100644
--- a/components/newlib/test/test_time.c
+++ b/components/newlib/test/test_time.c
@@ -26,6 +26,9 @@
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
 #define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
+#define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
 #endif
 
 #if portNUM_PROCESSORS == 2
diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index 37c3bab0b4..5285e6be27 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -21,6 +21,7 @@
 #include <freertos/task.h>
 #include <freertos/semphr.h>
 #if CONFIG_IDF_TARGET_ESP32
+#include "soc/dport_reg.h"
 #include <esp32/rom/spi_flash.h>
 #include <esp32/rom/cache.h>
 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -33,9 +34,13 @@
 #include "esp32s3/rom/cache.h"
 #include "soc/extmem_reg.h"
 #include "soc/cache_memory.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
+#include "esp32c3/rom/cache.h"
+#include "soc/extmem_reg.h"
+#include "soc/cache_memory.h"
 #endif
 #include <soc/soc.h>
-#include <soc/dport_reg.h>
 #include "sdkconfig.h"
 #ifndef CONFIG_FREERTOS_UNICORE
 #include "esp_ipc.h"
@@ -314,6 +319,10 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st
     icache_state = Cache_Suspend_ICache() << 16;
     dcache_state = Cache_Suspend_DCache();
     *saved_state = icache_state | dcache_state;
+#elif CONFIG_IDF_TARGET_ESP32C3
+    uint32_t icache_state;
+    icache_state = Cache_Suspend_ICache() << 16;
+    *saved_state = icache_state;
 #endif
 }
 
@@ -336,6 +345,8 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta
 #elif CONFIG_IDF_TARGET_ESP32S3
     Cache_Resume_DCache(saved_state & 0xffff);
     Cache_Resume_ICache(saved_state >> 16);
+#elif CONFIG_IDF_TARGET_ESP32C3
+    Cache_Resume_ICache(saved_state >> 16);
 #endif
 }
 
@@ -348,7 +359,7 @@ IRAM_ATTR bool spi_flash_cache_enabled(void)
 #endif
 #elif CONFIG_IDF_TARGET_ESP32S2
     bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0);
-#elif CONFIG_IDF_TARGET_ESP32S3
+#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
     bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0);
 #endif
     return result;
@@ -463,19 +474,19 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
     int i;
     bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
     uint32_t drom0_in_icache = 1;//always 1 in esp32s2
-#if CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
     drom0_in_icache = 0;
 #endif
 
     if (icache_wrap_enable) {
-#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
+#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B
         icache_wrap_size = 16;
 #else
         icache_wrap_size = 32;
 #endif
     }
     if (dcache_wrap_enable) {
-#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B
+#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B
         dcache_wrap_size = 16;
 #else
         dcache_wrap_size = 32;
diff --git a/components/spi_flash/cache_utils.h b/components/spi_flash/cache_utils.h
index e12f2f8442..a2835ac7d2 100644
--- a/components/spi_flash/cache_utils.h
+++ b/components/spi_flash/cache_utils.h
@@ -15,6 +15,7 @@
 #ifndef ESP_SPI_FLASH_CACHE_UTILS_H
 #define ESP_SPI_FLASH_CACHE_UTILS_H
 
+#include "sdkconfig.h"
 #include <stdbool.h>
 
 /**
@@ -57,10 +58,10 @@ void spi_flash_enable_interrupts_caches_no_os(void);
 //
 // Only call this while holding spi_flash_op_lock()
 // Returns true if cache was flushed, false otherwise
-bool spi_flash_check_and_flush_cache(uint32_t start_addr, uint32_t length);
+bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length);
 
 //config cache mode
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
 //config instrcutin cache size and cache block size by menuconfig
 void esp_config_instruction_cache_mode(void);
 //config data cache size and cache block size by menuconfig
diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c
index 5b2e5ee27f..de764901c7 100644
--- a/components/spi_flash/esp_flash_spi_init.c
+++ b/components/spi_flash/esp_flash_spi_init.c
@@ -31,6 +31,8 @@
 #include "esp32s2/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
 #endif
 
 __attribute__((unused)) static const char TAG[] = "spi_flash";
@@ -224,7 +226,7 @@ esp_err_t esp_flash_init_default_chip(void)
 {
     memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
 
-    #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+    #if !CONFIG_IDF_TARGET_ESP32
     // For esp32s2 spi IOs are configured as from IO MUX by default
     cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ?  true : false;
     #endif
diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c
index 6e9ec0cebf..aacf13a7be 100644
--- a/components/spi_flash/flash_mmap.c
+++ b/components/spi_flash/flash_mmap.c
@@ -20,22 +20,24 @@
 #include <freertos/FreeRTOS.h>
 #include <freertos/task.h>
 #include <freertos/semphr.h>
-#include <soc/soc.h>
-#include <soc/dport_reg.h>
-#include <soc/soc_memory_layout.h>
+#include "soc/soc.h"
+#include "soc/soc_memory_layout.h"
+#include "soc/dport_access.h"
 #include "sdkconfig.h"
 #include "esp_attr.h"
 #include "esp_spi_flash.h"
 #include "esp_flash_encrypt.h"
 #include "esp_log.h"
 #include "cache_utils.h"
+
 #if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/spi_flash.h"
+#include "soc/dport_reg.h"
 #include "esp32/rom/cache.h"
+#include "esp32/rom/spi_flash.h"
 #include "esp32/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/spi_flash.h"
 #include "esp32s2/rom/cache.h"
+#include "esp32s2/rom/spi_flash.h"
 #include "esp32s2/spiram.h"
 #include "soc/extmem_reg.h"
 #include "soc/cache_memory.h"
@@ -45,6 +47,10 @@
 #include "esp32s3/spiram.h"
 #include "soc/extmem_reg.h"
 #include "soc/cache_memory.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/cache.h"
+#include "esp32c3/rom/spi_flash.h"
+#include "soc/cache_memory.h"
 #endif
 
 #ifndef NDEBUG
@@ -274,7 +280,7 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp
                     DPORT_APP_FLASH_MMU_TABLE[i] = pages[pageno];
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
                     Cache_Invalidate_Addr(region_addr + (i - region_begin) * SPI_FLASH_MMU_PAGE_SIZE, SPI_FLASH_MMU_PAGE_SIZE);
 #endif
                     need_flush = true;
@@ -300,14 +306,14 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp
     */
     if (need_flush) {
 #if CONFIG_IDF_TARGET_ESP32
-# if CONFIG_SPIRAM
+#if CONFIG_SPIRAM
         esp_spiram_writeback_cache();
-# endif
+#endif // CONFIG_SPIRAM
         Cache_Flush(0);
-# if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_FREERTOS_UNICORE
         Cache_Flush(1);
-# endif
-#endif
+#endif // !CONFIG_FREERTOS_UNICORE
+#endif // CONFIG_IDF_TARGET_ESP32
     }
 
     spi_flash_enable_interrupts_caches_and_other_cpu();
@@ -438,7 +444,7 @@ uint32_t spi_flash_cache2phys(const void *cached)
     return phys_offs | (c & (SPI_FLASH_MMU_PAGE_SIZE-1));
 }
 
-const void *IRAM_ATTR spi_flash_phys2cache(uint32_t phys_offs, spi_flash_mmap_memory_t memory)
+const void *IRAM_ATTR spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory)
 {
     uint32_t phys_page = phys_offs / SPI_FLASH_MMU_PAGE_SIZE;
     int start, end, page_delta;
@@ -506,7 +512,7 @@ static bool IRAM_ATTR is_page_mapped_in_cache(uint32_t phys_page, const void **o
     for (int j = 0; j < 2; j++) {
         for (int i = start[j]; i < end[j]; i++) {
             if (DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]) == PAGE_IN_FLASH(phys_page)) {
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
                 if (j == 0) { /* SPI_FLASH_MMAP_DATA */
                     *out_ptr = (const void *)(VADDR0_START_ADDR + SPI_FLASH_MMU_PAGE_SIZE * (i - start[0]));
                 } else { /* SPI_FLASH_MMAP_INST */
@@ -547,12 +553,12 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
             Cache_Flush(1);
 #endif
             return true;
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else // CONFIG_IDF_TARGET_ESP32
             if (vaddr != NULL) {
                 Cache_Invalidate_Addr((uint32_t)vaddr, SPI_FLASH_MMU_PAGE_SIZE);
                 ret = true;
             }
-#endif
+#endif // CONFIG_IDF_TARGET_ESP32
 
         }
     }
diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c
index 4cbdab4bdf..d13b11a68f 100644
--- a/components/spi_flash/flash_ops.c
+++ b/components/spi_flash/flash_ops.c
@@ -22,7 +22,6 @@
 #include <freertos/task.h>
 #include <freertos/semphr.h>
 #include <soc/soc.h>
-#include <soc/dport_reg.h>
 #include <soc/soc_memory_layout.h>
 #include "sdkconfig.h"
 #include "esp_attr.h"
@@ -30,17 +29,21 @@
 #include "esp_log.h"
 #include "esp_private/system_internal.h"
 #if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/spi_flash.h"
 #include "esp32/rom/cache.h"
+#include "esp32/rom/spi_flash.h"
 #include "esp32/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/spi_flash.h"
 #include "esp32s2/rom/cache.h"
+#include "esp32s2/rom/spi_flash.h"
 #include "esp32s2/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/spi_flash.h"
 #include "esp32s3/rom/cache.h"
 #include "esp32s3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/cache.h"
+#include "esp32c3/rom/spi_flash.h"
+#include "esp32c3/clk.h"
 #endif
 #include "esp_flash_partitions.h"
 #include "cache_utils.h"
@@ -68,11 +71,11 @@ static const char *TAG __attribute__((unused)) = "spi_flash";
 #if CONFIG_SPI_FLASH_ENABLE_COUNTERS
 static spi_flash_counters_t s_flash_stats;
 
-#define COUNTER_START()     uint32_t ts_begin = xthal_get_ccount()
+#define COUNTER_START()     uint32_t ts_begin = cpu_hal_get_cycle_count()
 #define COUNTER_STOP(counter)  \
     do{ \
         s_flash_stats.counter.count++; \
-        s_flash_stats.counter.time += (xthal_get_ccount() - ts_begin) / (esp_clk_cpu_freq() / 1000000); \
+        s_flash_stats.counter.time += (cpu_hal_get_cycle_count() - ts_begin) / (esp_clk_cpu_freq() / 1000000); \
     } while(0)
 
 #define COUNTER_ADD_BYTES(counter, size) \
@@ -784,8 +787,7 @@ void spi_flash_dump_counters(void)
 
 #endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS
 
-
-#if defined(CONFIG_SPI_FLASH_USE_LEGACY_IMPL) && (defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3))
-// TODO esp32s2: Remove once ESP32S2 has new SPI Flash API support
+#if CONFIG_SPI_FLASH_USE_LEGACY_IMPL && !CONFIG_IDF_TARGET_ESP32
+// TODO esp32s2: Remove once ESP32-S2 & later chips has new SPI Flash API support
 esp_flash_t *esp_flash_default_chip = NULL;
 #endif
diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c
index 493aad0aa4..a50878ba3f 100644
--- a/components/spi_flash/spi_flash_os_func_noos.c
+++ b/components/spi_flash/spi_flash_os_func_noos.c
@@ -25,6 +25,9 @@
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/ets_sys.h"
 #include "esp32s3/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/ets_sys.h"
+#include "esp32c3/rom/cache.h"
 #endif
 
 #include "esp_attr.h"
@@ -63,6 +66,10 @@ static IRAM_ATTR esp_err_t end(void *arg)
     Cache_Invalidate_ICache_All();
     Cache_Resume_ICache(spi_arg->icache_autoload);
     Cache_Resume_DCache(spi_arg->dcache_autoload);
+#elif CONFIG_IDF_TARGET_ESP32C3
+    spi_noos_arg_t *spi_arg = arg;
+    Cache_Invalidate_ICache_All();
+    Cache_Resume_ICache(spi_arg->icache_autoload);
 #endif
     return ESP_OK;
 }
@@ -88,7 +95,7 @@ esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip)
 {
     chip->os_func = &esp_flash_noos_functions;
 
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#if !CONFIG_IDF_TARGET_ESP32
     chip->os_func_data = &spi_arg;
 #endif
 
diff --git a/components/unity/unity_port_esp32.c b/components/unity/unity_port_esp32.c
index ce2112f1de..e47960828d 100644
--- a/components/unity/unity_port_esp32.c
+++ b/components/unity/unity_port_esp32.c
@@ -23,6 +23,8 @@
 #include "esp32s2/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
 #endif
 
 static uint32_t s_test_start, s_test_stop;
diff --git a/components/vfs/vfs_uart.c b/components/vfs/vfs_uart.c
index 5ef09d7040..3b11edd589 100644
--- a/components/vfs/vfs_uart.c
+++ b/components/vfs/vfs_uart.c
@@ -162,7 +162,7 @@ static void uart_tx_char(int fd, int c)
     }
 #if CONFIG_IDF_TARGET_ESP32
     uart->fifo.rw_byte = c;
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else // CONFIG_IDF_TARGET_ESP32
     uart->ahb_fifo.rw_byte = c;
 #endif
 }
@@ -181,7 +181,7 @@ static int uart_rx_char(int fd)
     }
 #if CONFIG_IDF_TARGET_ESP32
     return uart->fifo.rw_byte;
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else // CONFIG_IDF_TARGET_ESP32
     return READ_PERI_REG(UART_FIFO_AHB_REG(fd));
 #endif
 }
diff --git a/examples/peripherals/ledc/main/ledc_example_main.c b/examples/peripherals/ledc/main/ledc_example_main.c
index ab476fa3da..9f5124f195 100644
--- a/examples/peripherals/ledc/main/ledc_example_main.c
+++ b/examples/peripherals/ledc/main/ledc_example_main.c
@@ -33,7 +33,7 @@
  *    GPIO4/5 are from low speed channel group.
  *
  */
-#ifdef CONFIG_IDF_TARGET_ESP32
+#if CONFIG_IDF_TARGET_ESP32
 #define LEDC_HS_TIMER          LEDC_TIMER_0
 #define LEDC_HS_MODE           LEDC_HIGH_SPEED_MODE
 #define LEDC_HS_CH0_GPIO       (18)
@@ -43,7 +43,7 @@
 #endif
 #define LEDC_LS_TIMER          LEDC_TIMER_1
 #define LEDC_LS_MODE           LEDC_LOW_SPEED_MODE
-#ifdef CONFIG_IDF_TARGET_ESP32S2
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
 #define LEDC_LS_CH0_GPIO       (18)
 #define LEDC_LS_CH0_CHANNEL    LEDC_CHANNEL_0
 #define LEDC_LS_CH1_GPIO       (19)
@@ -95,7 +95,7 @@ void app_main(void)
      *         will be the same
      */
     ledc_channel_config_t ledc_channel[LEDC_TEST_CH_NUM] = {
-#ifdef CONFIG_IDF_TARGET_ESP32
+#if CONFIG_IDF_TARGET_ESP32
         {
             .channel    = LEDC_HS_CH0_CHANNEL,
             .duty       = 0,
@@ -112,7 +112,7 @@ void app_main(void)
             .hpoint     = 0,
             .timer_sel  = LEDC_HS_TIMER
         },
-#elif defined CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
         {
             .channel    = LEDC_LS_CH0_CHANNEL,
             .duty       = 0,
diff --git a/examples/peripherals/rmt/ir_protocols/components/infrared_tools/include/ir_tools.h b/examples/peripherals/rmt/ir_protocols/components/infrared_tools/include/ir_tools.h
index 3938d6897d..0ef37d3269 100644
--- a/examples/peripherals/rmt/ir_protocols/components/infrared_tools/include/ir_tools.h
+++ b/examples/peripherals/rmt/ir_protocols/components/infrared_tools/include/ir_tools.h
@@ -130,7 +130,7 @@ struct ir_builder_s {
     *      - ESP_ERR_INVALID_ARG: Get result data failed because of invalid arguments
     *      - ESP_FAIL: Get result data failed because some other errors occurred
     */
-    esp_err_t (*get_result)(ir_builder_t *builder, void *result, uint32_t *length);
+    esp_err_t (*get_result)(ir_builder_t *builder, void *result, size_t *length);
 
     /**
     * @brief Free resources used by IR builder
diff --git a/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_nec.c b/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_nec.c
index 3b41e9eeb6..c553766564 100644
--- a/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_nec.c
+++ b/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_nec.c
@@ -142,7 +142,7 @@ static esp_err_t nec_build_repeat_frame(ir_builder_t *builder)
     return ESP_OK;
 }
 
-static esp_err_t nec_builder_get_result(ir_builder_t *builder, void *result, uint32_t *length)
+static esp_err_t nec_builder_get_result(ir_builder_t *builder, void *result, size_t *length)
 {
     esp_err_t ret = ESP_OK;
     nec_builder_t *nec_builder = __containerof(builder, nec_builder_t, parent);
diff --git a/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_rc5.c b/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_rc5.c
index 7b30d32114..7063961abf 100644
--- a/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_rc5.c
+++ b/examples/peripherals/rmt/ir_protocols/components/infrared_tools/src/ir_builder_rmt_rc5.c
@@ -135,7 +135,7 @@ static esp_err_t rc5_build_repeat_frame(ir_builder_t *builder)
     return ESP_OK;
 }
 
-static esp_err_t rc5_builder_get_result(ir_builder_t *builder, void *result, uint32_t *length)
+static esp_err_t rc5_builder_get_result(ir_builder_t *builder, void *result, size_t *length)
 {
     esp_err_t ret = ESP_OK;
     rc5_builder_t *rc5_builder = __containerof(builder, rc5_builder_t, parent);
diff --git a/examples/peripherals/rmt/ir_protocols/main/ir_protocols_main.c b/examples/peripherals/rmt/ir_protocols/main/ir_protocols_main.c
index b9fa721b4d..4c819107c2 100644
--- a/examples/peripherals/rmt/ir_protocols/main/ir_protocols_main.c
+++ b/examples/peripherals/rmt/ir_protocols/main/ir_protocols_main.c
@@ -18,7 +18,7 @@
 static const char *TAG = "example";
 
 static rmt_channel_t example_tx_channel = RMT_CHANNEL_0;
-static rmt_channel_t example_rx_channel = RMT_CHANNEL_1;
+static rmt_channel_t example_rx_channel = RMT_CHANNEL_2;
 
 /**
  * @brief RMT Receive Task
diff --git a/examples/security/flash_encryption/main/flash_encrypt_main.c b/examples/security/flash_encryption/main/flash_encrypt_main.c
index ffad2225e7..4f6e3300b5 100644
--- a/examples/security/flash_encryption/main/flash_encrypt_main.c
+++ b/examples/security/flash_encryption/main/flash_encrypt_main.c
@@ -29,6 +29,9 @@ static const char* TAG = "example";
 #elif CONFIG_IDF_TARGET_ESP32S2
 #define TARGET_CRYPT_CNT_EFUSE ESP_EFUSE_SPI_BOOT_CRYPT_CNT
 #define TARGET_CRYPT_CNT_WIDTH  3
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define TARGET_CRYPT_CNT_EFUSE ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT
+#define TARGET_CRYPT_CNT_WIDTH  3
 #endif
 
 void app_main(void)
diff --git a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c
index 6fc92090bd..8ac93923aa 100644
--- a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c
+++ b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_data.c
@@ -15,6 +15,8 @@
 #include "esp32s2/clk.h"
 #elif CONFIG_IDF_TARTGET_ESP32S3
 #include "esp32s3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/clk.h"
 #endif
 
 #include "unity.h"
@@ -36,6 +38,11 @@ static const char* TAG = "test_ccomp_timer";
 #define CACHE_LINE_SIZE         32
 #define CACHE_SIZE              (1 << 13)
 #define TEST_SIZE               (CACHE_SIZE)
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define CACHE_WAYS              8
+#define CACHE_LINE_SIZE         32
+#define CACHE_SIZE              (1 << 14)
+#define TEST_SIZE               (CACHE_SIZE)
 #endif
 
 typedef struct {
diff --git a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c
index 0797730de2..921de84f73 100644
--- a/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c
+++ b/tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c
@@ -23,6 +23,10 @@
 #define CACHE_WAYS              8
 #define CACHE_LINE_SIZE         32
 #define CACHE_SIZE              (1 << 13)
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define CACHE_WAYS              8
+#define CACHE_LINE_SIZE         32
+#define CACHE_SIZE              (1 << 14)
 #endif
 
 typedef void (*ccomp_test_func_t)(void);