From 1d0442bf99939df34d0b332877ee426019b2bf28 Mon Sep 17 00:00:00 2001 From: LonerDan Date: Tue, 18 Jun 2024 12:49:43 +0200 Subject: [PATCH] fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V According to the ESP32-S2/S3 TRM, the output pin's mode is set in the RTC_GPIO_PINn_REG by programming the RTC_GPIO_PINn_PAD_DRIVER bit. The current ULP RISC-V RTCIO driver however, incorrectly programs the RTC_IO_TOUCH_PADn_REG register field RTC_IO_TOUCH_PADn_DRV. This commit fixes the bug. --- components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h index 6e02ea70f9..f3c8827167 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h @@ -96,7 +96,7 @@ static inline uint8_t ulp_riscv_gpio_get_level(gpio_num_t gpio_num) static inline void ulp_riscv_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode) { - REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_DRV, mode); + REG_SET_FIELD(RTC_GPIO_PIN0_REG + gpio_num * 4, RTC_GPIO_PIN0_PAD_DRIVER, mode); } static inline void ulp_riscv_gpio_pullup(gpio_num_t gpio_num)