diff --git a/components/driver/can.c b/components/driver/can.c index d67b826388..ced010c761 100644 --- a/components/driver/can.c +++ b/components/driver/can.c @@ -340,7 +340,11 @@ esp_err_t can_driver_install(const can_general_config_t *g_config, const can_tim CAN_CHECK(g_config->rx_queue_len > 0, ESP_ERR_INVALID_ARG); CAN_CHECK(g_config->tx_io >= 0 && g_config->tx_io < GPIO_NUM_MAX, ESP_ERR_INVALID_ARG); CAN_CHECK(g_config->rx_io >= 0 && g_config->rx_io < GPIO_NUM_MAX, ESP_ERR_INVALID_ARG); - CAN_CHECK(CAN_BRP_IS_VALID(t_config->brp), ESP_ERR_INVALID_ARG); +#if (CONFIG_ESP32_REV_MIN >= 2) + CAN_CHECK(t_config->brp >= CAN_BRP_MIN && t_config->brp <= CAN_BRP_MAX_ECO, ESP_ERR_INVALID_ARG); +#else + CAN_CHECK(t_config->brp >= CAN_BRP_MIN && t_config->brp <= CAN_BRP_MAX, ESP_ERR_INVALID_ARG); +#endif esp_err_t ret; can_obj_t *p_can_obj_dummy; diff --git a/components/soc/esp32/include/hal/can_ll.h b/components/soc/esp32/include/hal/can_ll.h index c498ed59a5..170949634c 100644 --- a/components/soc/esp32/include/hal/can_ll.h +++ b/components/soc/esp32/include/hal/can_ll.h @@ -28,6 +28,7 @@ extern "C" { #include #include +#include "sdkconfig.h" #include "hal/can_types.h" #include "soc/can_periph.h" @@ -334,8 +335,8 @@ static inline uint32_t can_ll_get_and_clear_intrs(can_dev_t *hw) */ static inline void can_ll_set_enabled_intrs(can_dev_t *hw, uint32_t intr_mask) { -#ifdef CAN_BRP_DIV_SUPPORTED - //ESP32 Rev 2 has brp div. Need to mask when setting +#if (CONFIG_ESP32_REV_MIN >= 2) + //ESP32 Rev 2 or later has brp div field. Need to mask it out hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask; #else hw->interrupt_enable_reg.val = intr_mask; @@ -360,7 +361,7 @@ static inline void can_ll_set_enabled_intrs(can_dev_t *hw, uint32_t intr_mask) */ static inline void can_ll_set_bus_timing(can_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling) { -#ifdef CAN_BRP_DIV_SUPPORTED +#if (CONFIG_ESP32_REV_MIN >= 2) if (brp > CAN_BRP_DIV_THRESH) { //Need to set brp_div bit hw->interrupt_enable_reg.brp_div = 1; diff --git a/components/soc/esp32/include/soc/can_caps.h b/components/soc/esp32/include/soc/can_caps.h index 68073a3363..6313c0dfcd 100644 --- a/components/soc/esp32/include/soc/can_caps.h +++ b/components/soc/esp32/include/soc/can_caps.h @@ -18,15 +18,10 @@ extern "C" { #endif -#if (CONFIG_ESP32_REV_MIN >= 2) -#define CAN_BRP_DIV_SUPPORTED 1 -#define CAN_BRP_DIV_THRESH 128 -//Any even number from 2 to 128, or multiples of 4 from 132 to 256 -#define CAN_BRP_IS_VALID(brp) (((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0) || ((brp) >= 132 && (brp) <= 256 && ((brp) & 0x3) == 0)) -#else -//Any even number from 2 to 128 -#define CAN_BRP_IS_VALID(brp) ((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0) -#endif +#define CAN_BRP_MIN 2 +#define CAN_BRP_MAX 128 +#define CAN_BRP_MAX_ECO 256 +#define CAN_BRP_DIV_THRESH 128 //Todo: Add FIFO overrun errata workaround //Todo: Add ECC decode capabilities diff --git a/components/soc/include/hal/can_types.h b/components/soc/include/hal/can_types.h index d7947e65c1..0cdac7b704 100644 --- a/components/soc/include/hal/can_types.h +++ b/components/soc/include/hal/can_types.h @@ -20,6 +20,7 @@ extern "C" { #include #include +#include "sdkconfig.h" /** * @brief CAN2.0B Constants @@ -53,7 +54,7 @@ extern "C" { * @note These timing values are based on the assumption APB clock is at 80MHz * @note The 20K, 16K and 12.5K bit rates are only available from ESP32 Revision 2 onwards */ -#ifdef CAN_BRP_DIV_SUPPORTED +#if (CONFIG_ESP32_REV_MIN >= 2) #define CAN_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} #define CAN_TIMING_CONFIG_16KBITS() {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} #define CAN_TIMING_CONFIG_20KBITS() {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}