From 5436d1f0c42138a9517e1f7d2acce23cc7b92dce Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 27 Jun 2025 20:04:13 +0800 Subject: [PATCH] fix(esp_system): force enable uart0 sclk in esp_restart --- components/esp_system/port/soc/esp32c5/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32c6/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32c61/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32h2/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32h21/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32h4/system_internal.c | 5 +++++ 6 files changed, 30 insertions(+) diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index f5afa5da8a..6c1e701d26 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -22,6 +22,7 @@ #include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" +#include "hal/uart_ll.h" #if SOC_MODEM_CLOCK_SUPPORTED #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" @@ -82,6 +83,10 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c index 2b7bfa1f9e..4652cda722 100644 --- a/components/esp_system/port/soc/esp32c6/system_internal.c +++ b/components/esp_system/port/soc/esp32c6/system_internal.c @@ -20,6 +20,7 @@ #include "esp_private/rtc_clk.h" #include "soc/rtc_periph.h" #include "soc/uart_reg.h" +#include "hal/uart_ll.h" #include "hal/wdt_hal.h" #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" @@ -75,6 +76,10 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index 8bfd22149b..6a64bf21db 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -20,6 +20,7 @@ #include "esp_private/rtc_clk.h" #include "soc/rtc_periph.h" #include "soc/uart_reg.h" +#include "hal/uart_ll.h" #include "hal/wdt_hal.h" #include "esp_private/cache_err_int.h" @@ -82,6 +83,10 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index 43afa42d37..eb750868b9 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -23,6 +23,7 @@ #include "soc/uart_reg.h" #include "hal/wdt_hal.h" #include "hal/spimem_flash_ll.h" +#include "hal/uart_ll.h" #include "esp_private/cache_err_int.h" #include "esp_private/mspi_timing_tuning.h" @@ -73,6 +74,10 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32h21/system_internal.c b/components/esp_system/port/soc/esp32h21/system_internal.c index 77c491e940..4f88da7e16 100644 --- a/components/esp_system/port/soc/esp32h21/system_internal.c +++ b/components/esp_system/port/soc/esp32h21/system_internal.c @@ -20,6 +20,7 @@ #include "esp_private/rtc_clk.h" #include "soc/rtc_periph.h" #include "soc/uart_reg.h" +#include "hal/uart_ll.h" #include "hal/wdt_hal.h" #include "hal/spimem_flash_ll.h" #include "esp_private/cache_err_int.h" @@ -77,6 +78,10 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c index f421bbd90f..960e65f181 100644 --- a/components/esp_system/port/soc/esp32h4/system_internal.c +++ b/components/esp_system/port/soc/esp32h4/system_internal.c @@ -21,6 +21,7 @@ #include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" +#include "hal/uart_ll.h" #include "esp32h4/rom/cache.h" // TODO: IDF-11911 need refactor @@ -70,6 +71,10 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this