From 544a3f7df5693bc32a7264e0a5bfec486620f9dd Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Thu, 19 Nov 2020 15:14:54 -0300 Subject: [PATCH] interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available --- components/esp_system/intr_alloc.c | 25 +++++--- .../port/riscv/include/freertos/xtensa_api.h | 2 - components/freertos/port/riscv/portasm.S | 2 +- .../include/hal/interrupt_controller_ll.h | 6 +- .../hal/esp32c3/interrupt_descriptor_table.c | 64 +++++++++---------- .../include/hal/interrupt_controller_types.h | 4 +- components/riscv/include/riscv/interrupt.h | 7 ++ components/riscv/interrupt.c | 6 ++ 8 files changed, 64 insertions(+), 52 deletions(-) delete mode 100644 components/freertos/port/riscv/include/freertos/xtensa_api.h diff --git a/components/esp_system/intr_alloc.c b/components/esp_system/intr_alloc.c index 67f3b6c697..b00fdacae3 100644 --- a/components/esp_system/intr_alloc.c +++ b/components/esp_system/intr_alloc.c @@ -48,7 +48,7 @@ Define this to debug the choices made when allocating the interrupt. This leads output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog being triggered, that is why it is separate from the normal LOG* scheme. */ -//define DEBUG_INT_ALLOC_DECISIONS +//#define DEBUG_INT_ALLOC_DECISIONS #ifdef DEBUG_INT_ALLOC_DECISIONS # define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__) #else @@ -238,13 +238,14 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force return false; } //Check if the interrupt level is acceptable - if (!(flags&(1<> 1) & ESP_INTR_FLAG_LEVELMASK)) + 1; - interrupt_controller_hal_set_int_type(intr, - interrupt_controller_hal_desc_type(intr)); + interrupt_controller_hal_set_int_level(intr,level); + + if (flags & ESP_INTR_FLAG_EDGE) { + interrupt_controller_hal_set_int_type(intr,INTTP_EDGE); + } else { + interrupt_controller_hal_set_int_type(intr,INTTP_LEVEL); + } portEXIT_CRITICAL(&spinlock); diff --git a/components/freertos/port/riscv/include/freertos/xtensa_api.h b/components/freertos/port/riscv/include/freertos/xtensa_api.h deleted file mode 100644 index 245b6246c0..0000000000 --- a/components/freertos/port/riscv/include/freertos/xtensa_api.h +++ /dev/null @@ -1,2 +0,0 @@ -/* Just a placeholder since this file is exposed in some top-level apps */ -#pragma once diff --git a/components/freertos/port/riscv/portasm.S b/components/freertos/port/riscv/portasm.S index 04a5399a94..3f4740299b 100644 --- a/components/freertos/port/riscv/portasm.S +++ b/components/freertos/port/riscv/portasm.S @@ -73,7 +73,7 @@ rtos_int_exit: la t2, uxInterruptNesting lw t3, 0x0(t2) - /* Already zero, protect againts underflow */ + /* Already zero, protect against underflow */ beq t3, zero, isr_skip_decrement addi t3,t3, -1 sw t3, 0x0(t2) diff --git a/components/hal/esp32c3/include/hal/interrupt_controller_ll.h b/components/hal/esp32c3/include/hal/interrupt_controller_ll.h index 8d0b8cb6d4..ca47c3a16f 100644 --- a/components/hal/esp32c3/include/hal/interrupt_controller_ll.h +++ b/components/hal/esp32c3/include/hal/interrupt_controller_ll.h @@ -122,8 +122,7 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask) */ static inline void intr_cntrl_ll_edge_int_acknowledge (int intr) { - intr_cntrl_ll_disable_interrupts(1 << intr); - esprv_intc_int_set_priority(intr, 0); + esprv_intc_set_interrupt_clear(intr); } /** @@ -145,9 +144,6 @@ static inline void intr_cntrl_ll_set_int_level(int intr, int level) */ static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type) { - /* Not needed currently for xtensa platforms since the type is already set - * in interrupt table - */ esprv_intc_int_set_type(BIT(intr), type); } diff --git a/components/hal/esp32c3/interrupt_descriptor_table.c b/components/hal/esp32c3/interrupt_descriptor_table.c index 8c0837e195..7e0e5709c4 100644 --- a/components/hal/esp32c3/interrupt_descriptor_table.c +++ b/components/hal/esp32c3/interrupt_descriptor_table.c @@ -18,38 +18,38 @@ //This is basically a software-readable version of the interrupt usage table in include/soc/soc.h const int_desc_t interrupt_descriptor_table[32] = { - { 1, INTTP_LEVEL, {INTDESC_RESVD } }, //0 - { 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //1 - { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //2 - { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //3 - { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //4 - { 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //5 - { 1, INTTP_NA, {INTDESC_NORMAL } }, //6 - { 1, INTTP_NA, {INTDESC_NORMAL } }, //7 - { 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //8 - { 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //9 - { 1, INTTP_EDGE, {INTDESC_NORMAL } }, //10 - { 3, INTTP_NA, {INTDESC_NORMAL } }, //11 - { 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //12 - { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //13 - { 7, INTTP_LEVEL, {INTDESC_NORMAL } }, //14 - { 3, INTTP_NA, {INTDESC_NORMAL } }, //15 - { 5, INTTP_NA, {INTDESC_NORMAL } }, //16 - { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //17 - { 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //18 - { 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //19 - { 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //20 - { 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //21 - { 3, INTTP_EDGE, {INTDESC_NORMAL } }, //22 - { 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //23 - { 4, INTTP_LEVEL, {INTDESC_RESVD } }, //24 - { 4, INTTP_LEVEL, {INTDESC_RESVD } }, //25 - { 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //26 - { 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //27 - { 4, INTTP_EDGE, {INTDESC_NORMAL } }, //28 - { 3, INTTP_NA, {INTDESC_NORMAL } }, //29 - { 4, INTTP_EDGE, {INTDESC_NORMAL } }, //30 - { 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //31 + { 1, INTTP_ANY, {INTDESC_RESVD } }, //0 + { 1, INTTP_ANY, {INTDESC_SPECIAL } }, //1 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //2 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //3 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //4 + { 1, INTTP_ANY, {INTDESC_SPECIAL } }, //5 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //6 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //7 + { 1, INTTP_ANY, {INTDESC_SPECIAL } }, //8 + { 1, INTTP_ANY, {INTDESC_SPECIAL } }, //9 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //10 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //11 + { 1, INTTP_ANY, {INTDESC_SPECIAL } }, //12 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //13 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //14 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //15 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //16 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //17 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //18 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //19 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //20 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //21 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //22 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //23 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //24 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //25 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //26 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //27 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //28 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //29 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //30 + { 1, INTTP_ANY, {INTDESC_NORMAL } }, //31 }; const int_desc_t *interrupt_controller_hal_desc_table(void) diff --git a/components/hal/include/hal/interrupt_controller_types.h b/components/hal/include/hal/interrupt_controller_types.h index bf9be1fd1f..9e36dc7361 100644 --- a/components/hal/include/hal/interrupt_controller_types.h +++ b/components/hal/include/hal/interrupt_controller_types.h @@ -24,13 +24,13 @@ extern "C" { typedef enum { INTDESC_NORMAL=0, INTDESC_RESVD, - INTDESC_SPECIAL + INTDESC_SPECIAL, } int_desc_flag_t; typedef enum { INTTP_LEVEL=0, INTTP_EDGE, - INTTP_NA + INTTP_ANY, } int_type_t; typedef struct { diff --git a/components/riscv/include/riscv/interrupt.h b/components/riscv/include/riscv/interrupt.h index 6498d57f2f..ed87384c17 100644 --- a/components/riscv/include/riscv/interrupt.h +++ b/components/riscv/include/riscv/interrupt.h @@ -110,6 +110,13 @@ void esprv_intc_set_threshold(int priority_threshold); */ uint32_t esprv_intc_get_interrupt_unmask(void); +/** + * @brief Set a bit in int clear register + * @param intr bit to set from 0 to 31 + * @return none + */ +void esprv_intc_set_interrupt_clear(int intr); + #ifdef __cplusplus } #endif diff --git a/components/riscv/interrupt.c b/components/riscv/interrupt.c index 1b48bfdf89..3be259be89 100644 --- a/components/riscv/interrupt.c +++ b/components/riscv/interrupt.c @@ -89,6 +89,12 @@ uint32_t esprv_intc_get_interrupt_unmask(void) return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG); } +void esprv_intc_set_interrupt_clear(int intr) +{ + REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr); +} + + /*************************** Exception names. Used in .gdbinit file. ***************************/ const char *riscv_excp_names[16] __attribute__((used)) = {