From fd5a63f31edf5fa56f27ec2974f43b411b7565a9 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 17 Sep 2021 10:42:04 +0800 Subject: [PATCH] modify csv & generate update efuse_reg.h & efuse_struct.h & references in rst file --- components/efuse/esp32c3/esp_efuse_table.c | 11 +----- components/efuse/esp32c3/esp_efuse_table.csv | 1 - .../efuse/esp32c3/include/esp_efuse_table.h | 3 +- components/efuse/esp32s3/esp_efuse_table.c | 22 ++---------- components/efuse/esp32s3/esp_efuse_table.csv | 2 -- .../efuse/esp32s3/include/esp_efuse_table.h | 6 ++-- .../soc/esp32c3/include/soc/efuse_reg.h | 36 +++++++++---------- .../soc/esp32c3/include/soc/efuse_struct.h | 6 ++-- .../soc/esp32s3/include/soc/efuse_reg.h | 36 +++++++++---------- .../system/inc/espefuse_summary_ESP32-C3.rst | 1 - .../system/inc/espefuse_summary_ESP32-S3.rst | 1 - 11 files changed, 45 insertions(+), 80 deletions(-) diff --git a/components/efuse/esp32c3/esp_efuse_table.c b/components/efuse/esp32c3/esp_efuse_table.c index bdb85decaa..a9bf093315 100644 --- a/components/efuse/esp32c3/esp_efuse_table.c +++ b/components/efuse/esp32c3/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 7e5a29e190c8e3a63e1a85a40b50c355 +// md5_digest_table fe80e03d1417e5757ef89923f8d01d33 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -155,10 +155,6 @@ static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, }; -static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, -}; - static const esp_efuse_desc_t DIS_ICACHE[] = { {EFUSE_BLK0, 40, 1}, // Disable Icache, }; @@ -677,11 +673,6 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { - &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { &DIS_ICACHE[0], // Disable Icache NULL diff --git a/components/efuse/esp32c3/esp_efuse_table.csv b/components/efuse/esp32c3/esp_efuse_table.csv index b6563e3848..90d3012952 100644 --- a/components/efuse/esp32c3/esp_efuse_table.csv +++ b/components/efuse/esp32c3/esp_efuse_table.csv @@ -50,7 +50,6 @@ RD_DIS_KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 RD_DIS_KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 RD_DIS_SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode diff --git a/components/efuse/esp32c3/include/esp_efuse_table.h b/components/efuse/esp32c3/include/esp_efuse_table.h index 4ea821416c..2ecdf5c46d 100644 --- a/components/efuse/esp32c3/include/esp_efuse_table.h +++ b/components/efuse/esp32c3/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table 7e5a29e190c8e3a63e1a85a40b50c355 +// md5_digest_table fe80e03d1417e5757ef89923f8d01d33 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -57,7 +57,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index fc07d89417..cca177cdf3 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -1,4 +1,4 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 6a29c09c943d9cb07bd874af57b5870e +// md5_digest_table 32d4e5502110edd26bdad463b5ac1d2d // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -27,10 +27,6 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, }; -static const esp_efuse_desc_t WR_DIS_DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 1, 1}, // Write protection for DIS_RTC_RAM_BOOT, -}; - static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, }; @@ -163,10 +159,6 @@ static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, }; -static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, -}; - static const esp_efuse_desc_t DIS_ICACHE[] = { {EFUSE_BLK0, 40, 1}, // Disable Icache, }; @@ -461,11 +453,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = { - &WR_DIS_DIS_RTC_RAM_BOOT[0], // Write protection for DIS_RTC_RAM_BOOT - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT NULL @@ -631,11 +618,6 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { - &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { &DIS_ICACHE[0], // Disable Icache NULL diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index 9ef6418fba..ae9163c703 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -14,7 +14,6 @@ # EFUSE_RD_WR_DIS_REG # # EFUSE_WR_DIS [WR_DIS 0 32] # WR_DIS_RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - WR_DIS_DIS_RTC_RAM_BOOT, EFUSE_BLK0, 1, 1, Write protection for DIS_RTC_RAM_BOOT WR_DIS_GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT WR_DIS_GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL WR_DIS_SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT @@ -51,7 +50,6 @@ RD_DIS_KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 RD_DIS_KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 RD_DIS_SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7 diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index 881e7808d2..9b1733d51f 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -1,4 +1,4 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table 6a29c09c943d9cb07bd874af57b5870e +// md5_digest_table 32d4e5502110edd26bdad463b5ac1d2d // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -25,7 +25,6 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; @@ -59,7 +58,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/include/soc/efuse_reg.h index ddaff7285c..fce4c04e26 100644 --- a/components/soc/esp32c3/include/soc/efuse_reg.h +++ b/components/soc/esp32c3/include/soc/efuse_reg.h @@ -141,12 +141,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to disable boot from RTC RAM.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: Set this bit to disable reading from BlOCK4-10.*/ #define EFUSE_RD_DIS 0x0000007F @@ -516,12 +516,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of DIS_RTC_RAM_BOOT.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: The value of RD_DIS.*/ #define EFUSE_RD_DIS 0x0000007F @@ -1486,12 +1486,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_V 0x1 #define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved..*/ +#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED5_ERR_S 7 /* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ #define EFUSE_RD_DIS_ERR 0x0000007F diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h index eed9c2544f..60d30feb91 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/include/soc/efuse_struct.h @@ -22,7 +22,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t dis_rtc_ram_boot: 1; /*Set this bit to disable boot from RTC RAM.*/ + uint32_t rpt4_reserved5: 1; /*Reserved*/ uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/ uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/ @@ -106,7 +106,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis: 7; /*The value of RD_DIS.*/ - uint32_t dis_rtc_ram_boot: 1; /*The value of DIS_RTC_RAM_BOOT.*/ + uint32_t rpt4_reserved5: 1; /*Reserved*/ uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/ uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/ uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ @@ -274,7 +274,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/ - uint32_t dis_rtc_ram_boot_err: 1; /*If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ + uint32_t rpt4_reserved5_err: 1; /*Reserved.*/ uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/ uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/ uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index 5d68868580..e99e116f91 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -142,12 +142,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to disable boot from RTC RAM.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved */ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: Set this bit to disable reading from BlOCK4-10.*/ #define EFUSE_RD_DIS 0x0000007F @@ -571,12 +571,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of DIS_RTC_RAM_BOOT.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved */ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: The value of RD_DIS.*/ #define EFUSE_RD_DIS 0x0000007F @@ -1583,12 +1583,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_V 0x1 #define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved..*/ +#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED5_ERR_S 7 /* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ #define EFUSE_RD_DIS_ERR 0x0000007F diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst index 89d1059feb..0329792ae4 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst @@ -8,7 +8,6 @@ EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- Config fuses: - DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0) DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst index 041f8abedc..e629a5ead6 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst @@ -27,7 +27,6 @@ ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001) Config fuses: - DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0) DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0) DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)