From a90f29fced223d2c73e7d5e38d88f6397d5354d6 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 18 Mar 2021 02:31:28 +0800 Subject: [PATCH 1/2] wdt: Updates --- .../bootloader_support/src/esp32c3/bootloader_esp32c3.c | 5 +++-- components/esp32c3/crosscore_int.c | 4 ++++ components/esp_system/task_wdt.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 13607bcf3d..b017f76624 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -233,8 +233,9 @@ static void wdt_reset_cpu0_info_enable(void) static void wdt_reset_info_dump(int cpu) { - // TODO ESP32-C3 IDF-2118 - ESP_LOGE(TAG, "WDT reset info dump is not supported yet"); + (void) cpu; + // saved PC was already printed by the ROM bootloader. + // nothing to do here. } static void bootloader_check_wdt_reset(void) diff --git a/components/esp32c3/crosscore_int.c b/components/esp32c3/crosscore_int.c index e704b33914..2eaccec255 100644 --- a/components/esp32c3/crosscore_int.c +++ b/components/esp32c3/crosscore_int.c @@ -58,6 +58,10 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) * to allow DFS features without the extra latency of the ISR hook. */ } + // TODO: ESP32-C3 IDF-2986 + // if (my_reason_val & REASON_PRINT_BACKTRACE) { + // esp_backtrace_print(100); + // } } // Initialize the crosscore interrupt on this core. diff --git a/components/esp_system/task_wdt.c b/components/esp_system/task_wdt.c index 27a68a5b15..26d716b452 100644 --- a/components/esp_system/task_wdt.c +++ b/components/esp_system/task_wdt.c @@ -184,7 +184,7 @@ static void task_wdt_isr(void *arg) abort(); } else { -#if !CONFIG_IDF_TARGET_ESP32C3 // TODO ESP32-C3 add backtrace printing support IDF-2285 +#if !CONFIG_IDF_TARGET_ESP32C3 // TODO: ESP32-C3 IDF-2986 int current_core = xPortGetCoreID(); //Print backtrace of current core ESP_EARLY_LOGE(TAG, "Print CPU %d (current core) backtrace", current_core); From aa1338bf239a1608edb64c5bf9b79ec4b0560d6f Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 19 Mar 2021 00:15:18 +0800 Subject: [PATCH 2/2] wdt: Fix timeout and RTC_SLOW_CLK RTC_SLOW_CLK ESP32: 150kHz ESP32-S2: 90kHz ESP32-S3: 150kHz ESP32-C3: 150kHz --- components/bt/controller/esp32c3/Kconfig.in | 4 ++-- components/bt/controller/esp32c3/bt.c | 2 +- components/bt/include/esp32c3/include/esp_bt.h | 2 +- components/esp32c3/Kconfig | 4 ++-- components/esp32s3/Kconfig | 4 ++-- components/esp_hw_support/port/esp32c3/rtc_clk.c | 2 +- components/esp_hw_support/port/esp32c3/rtc_clk_init.c | 6 +++--- components/esp_hw_support/port/esp32c3/rtc_time.c | 8 ++++---- components/esp_hw_support/port/esp32s3/rtc_clk.c | 2 +- components/esp_hw_support/port/esp32s3/rtc_clk_init.c | 6 +++--- components/esp_hw_support/port/esp32s3/rtc_time.c | 8 ++++---- components/esp_system/port/soc/esp32c3/clk.c | 8 ++++---- components/esp_system/port/soc/esp32s3/clk.c | 8 ++++---- components/hal/esp32s3/include/hal/touch_sensor_ll.h | 2 +- components/soc/esp32c3/include/soc/rtc.h | 6 +++--- components/soc/esp32s2/include/soc/rtc.h | 4 ++-- components/soc/esp32s3/include/soc/rtc.h | 6 +++--- docs/en/api-guides/ulp-risc-v.rst | 4 +++- docs/en/api-reference/system/system_time.rst | 2 +- 19 files changed, 45 insertions(+), 43 deletions(-) diff --git a/components/bt/controller/esp32c3/Kconfig.in b/components/bt/controller/esp32c3/Kconfig.in index e7839196f0..cc8d516807 100644 --- a/components/bt/controller/esp32c3/Kconfig.in +++ b/components/bt/controller/esp32c3/Kconfig.in @@ -331,10 +331,10 @@ menu "MODEM SLEEP Options" modem sleep to be used with both DFS and light sleep. config BT_CTRL_LPCLK_SEL_RTC_SLOW - bool "Internal 90kHz RC oscillator" + bool "Internal 150kHz RC oscillator" depends on ESP32C3_RTC_CLK_SRC_INT_RC help - Internal 90kHz RC oscillator. + Internal 150kHz RC oscillator. endchoice diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index aba2da6ba2..c71b2e07f9 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -1045,7 +1045,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) { s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_RTC_SLOW; // set default value } else { - ESP_LOGW(BTDM_LOG_TAG, "Internal 90kHz RC oscillator not detected, fall back to main XTAL as Bluetooth sleep clock\n" + ESP_LOGW(BTDM_LOG_TAG, "Internal 150kHz RC oscillator not detected, fall back to main XTAL as Bluetooth sleep clock\n" "light sleep mode will not be able to apply when bluetooth is enabled"); s_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL; // set default value } diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h index d0ea8c4fc2..b0f80ce1ce 100644 --- a/components/bt/include/esp32c3/include/esp_bt.h +++ b/components/bt/include/esp32c3/include/esp_bt.h @@ -73,7 +73,7 @@ typedef enum { ESP_BT_SLEEP_CLOCK_NONE = 0, /*!< Sleep clock not configured */ ESP_BT_SLEEP_CLOCK_MAIN_XTAL = 1, /*!< SoC main crystal */ ESP_BT_SLEEP_CLOCK_EXT_32K_XTAL = 2, /*!< External 32.768kHz crystal */ - ESP_BT_SLEEP_CLOCK_RTC_SLOW = 3, /*!< Internal 90kHz RC oscillator */ + ESP_BT_SLEEP_CLOCK_RTC_SLOW = 3, /*!< Internal 150kHz RC oscillator */ ESP_BT_SLEEP_CLOCK_FPGA_32K = 4, /*!< Hardwired 32KHz clock temporarily used for FPGA */ } esp_bt_sleep_clock_t; diff --git a/components/esp32c3/Kconfig b/components/esp32c3/Kconfig index 64e271d8da..59454e541a 100644 --- a/components/esp32c3/Kconfig +++ b/components/esp32c3/Kconfig @@ -162,7 +162,7 @@ menu "ESP32C3-Specific" Choose which clock is used as RTC clock source. config ESP32C3_RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" + bool "Internal 150kHz RC oscillator" config ESP32C3_RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL @@ -188,7 +188,7 @@ menu "ESP32C3-Specific" When this option is set to 0, clock calibration will not be performed at startup, and approximate clock frequencies will be assumed: - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. In case more value will help improve the definition of the launch of the crystal. If the crystal could not start, it will be switched to internal RC. diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig index 0ffeea963c..89dff330bf 100644 --- a/components/esp32s3/Kconfig +++ b/components/esp32s3/Kconfig @@ -448,7 +448,7 @@ menu "ESP32S3-Specific" Choose which clock is used as RTC clock source. config ESP32S3_RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" + bool "Internal 150kHz RC oscillator" config ESP32S3_RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL @@ -474,7 +474,7 @@ menu "ESP32S3-Specific" When this option is set to 0, clock calibration will not be performed at startup, and approximate clock frequencies will be assumed: - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. In case more value will help improve the definition of the launch of the crystal. If the crystal could not start, it will be switched to internal RC. diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index 93314b7dc6..7b52bebae8 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -180,7 +180,7 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void) uint32_t rtc_clk_slow_freq_get_hz(void) { switch (rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_90K; + case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; } diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c index 3c4314a85e..ca9dd74cba 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c @@ -36,10 +36,10 @@ void rtc_clk_init(rtc_clk_config_t cfg) { rtc_cpu_freq_config_t old_config, new_config; - /* Set tuning parameters for 8M and 90k clocks. + /* Set tuning parameters for 8M and 150k clocks. * Note: this doesn't attempt to set the clocks to precise frequencies. * Instead, we calibrate these clocks against XTAL frequency later, when necessary. - * - SCK_DCAP value controls tuning of 90k clock. + * - SCK_DCAP value controls tuning of 150k clock. * The higher the value of DCAP is, the lower is the frequency. * - CK8M_DFREQ value controls tuning of 8M clock. * CLK_8M_DFREQ constant gives the best temperature characteristics. @@ -47,7 +47,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); - /* Configure 90k clock division */ + /* Configure 150k clock division */ rtc_clk_divider_set(cfg.clk_rtc_clk_div); /* Configure 8M clock division */ diff --git a/components/esp_hw_support/port/esp32c3/rtc_time.c b/components/esp_hw_support/port/esp32c3/rtc_time.c index e5b6b77575..7792d5cf13 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_time.c +++ b/components/esp_hw_support/port/esp32c3/rtc_time.c @@ -40,7 +40,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { /* On ESP32C3, choosing RTC_CAL_RTC_MUX results in calibration of - * the 90k RTC clock regardless of the currenlty selected SLOW_CLK. + * the 150k RTC clock regardless of the currenlty selected SLOW_CLK. * On the ESP32, it used the currently selected SLOW_CLK. * The following code emulates ESP32 behavior: */ @@ -52,7 +52,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) cal_clk = RTC_CAL_8MD256; } } - /* Enable requested clock (90k clock is always on) */ + /* Enable requested clock (150k clock is always on) */ int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); @@ -84,8 +84,8 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = RTC_SLOW_CLK_FREQ_8MD256; } else { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_90K; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_150K; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 71b208a6a0..9ae161734c 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -187,7 +187,7 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void) uint32_t rtc_clk_slow_freq_get_hz(void) { switch (rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_90K; + case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; } diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk_init.c b/components/esp_hw_support/port/esp32s3/rtc_clk_init.c index 9fced2bc2f..013ccfc7f4 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk_init.c @@ -32,10 +32,10 @@ void rtc_clk_init(rtc_clk_config_t cfg) { rtc_cpu_freq_config_t old_config, new_config; - /* Set tuning parameters for 8M and 90k clocks. + /* Set tuning parameters for 8M and 150k clocks. * Note: this doesn't attempt to set the clocks to precise frequencies. * Instead, we calibrate these clocks against XTAL frequency later, when necessary. - * - SCK_DCAP value controls tuning of 90k clock. + * - SCK_DCAP value controls tuning of 150k clock. * The higher the value of DCAP is, the lower is the frequency. * - CK8M_DFREQ value controls tuning of 8M clock. * CLK_8M_DFREQ constant gives the best temperature characteristics. @@ -43,7 +43,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); - /* Configure 90k clock division */ + /* Configure 150k clock division */ rtc_clk_divider_set(cfg.clk_rtc_clk_div); /* Configure 8M clock division */ diff --git a/components/esp_hw_support/port/esp32s3/rtc_time.c b/components/esp_hw_support/port/esp32s3/rtc_time.c index a0e2072e5e..2aa925fda2 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_time.c +++ b/components/esp_hw_support/port/esp32s3/rtc_time.c @@ -39,7 +39,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { /* On ESP32S3, choosing RTC_CAL_RTC_MUX results in calibration of - * the 90k RTC clock regardless of the currenlty selected SLOW_CLK. + * the 150k RTC clock regardless of the currenlty selected SLOW_CLK. * On the ESP32, it used the currently selected SLOW_CLK. * The following code emulates ESP32 behavior: */ @@ -51,7 +51,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) cal_clk = RTC_CAL_8MD256; } } - /* Enable requested clock (90k clock is always on) */ + /* Enable requested clock (150k clock is always on) */ int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); @@ -83,8 +83,8 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = RTC_SLOW_CLK_FREQ_8MD256; } else { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = RTC_SLOW_CLK_FREQ_90K; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_150K; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c index 3b442a2332..cc3580c714 100644 --- a/components/esp_system/port/soc/esp32c3/clk.c +++ b/components/esp_system/port/soc/esp32c3/clk.c @@ -60,7 +60,7 @@ * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. */ typedef enum { - SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 90 kHz RC oscillator + SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256 SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin @@ -89,10 +89,10 @@ static const char *TAG = "clk"; #ifdef CONFIG_BOOTLOADER_WDT_ENABLE // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. - // If the frequency changes from 90kHz to 32kHz, then the timeout set for the WDT will increase 2.8 times. + // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times. // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec). // This prevents excessive delay before resetting in case the supply voltage is drawdown. - // (If frequency is changed from 90kHz to 32kHz then WDT timeout will increased to 1.6sec * 90/32 = 4.5 sec). + // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec). wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); wdt_hal_write_protect_disable(&rtc_wdt_ctx); @@ -172,7 +172,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) if (retry_32k_xtal-- > 0) { continue; } - ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 90 kHz oscillator"); + ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); rtc_slow_freq = RTC_SLOW_FREQ_RTC; } } diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c index 0478452f42..91c6e6cf68 100644 --- a/components/esp_system/port/soc/esp32s3/clk.c +++ b/components/esp_system/port/soc/esp32s3/clk.c @@ -66,7 +66,7 @@ static const char *TAG = "clk"; * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values. */ typedef enum { - SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 90 kHz RC oscillator + SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256 SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin @@ -85,10 +85,10 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); #ifdef CONFIG_BOOTLOADER_WDT_ENABLE // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. - // If the frequency changes from 90kHz to 32kHz, then the timeout set for the WDT will increase 2.8 times. + // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times. // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec). // This prevents excessive delay before resetting in case the supply voltage is drawdown. - // (If frequency is changed from 90kHz to 32kHz then WDT timeout will increased to 1.6sec * 90/32 = 4.5 sec). + // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec). wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); wdt_hal_write_protect_disable(&rtc_wdt_ctx); @@ -170,7 +170,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) if (retry_32k_xtal-- > 0) { continue; } - ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 90 kHz oscillator"); + ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); rtc_slow_freq = RTC_SLOW_FREQ_RTC; } } diff --git a/components/hal/esp32s3/include/hal/touch_sensor_ll.h b/components/hal/esp32s3/include/hal/touch_sensor_ll.h index f60054e8ac..0ad95126f3 100644 --- a/components/hal/esp32s3/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32s3/include/hal/touch_sensor_ll.h @@ -72,7 +72,7 @@ static inline void touch_ll_get_measure_times(uint16_t *meas_time) */ static inline void touch_ll_set_sleep_time(uint16_t sleep_time) { - // touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK(90k) + // touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK(150k) RTCCNTL.touch_ctrl1.touch_sleep_cycles = sleep_time; } diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 6133166c73..de718efec5 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -55,9 +55,9 @@ extern "C" { #define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) -#define RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_FREQ_90K 90000 +#define RTC_SLOW_CLK_FREQ_150K 150000 #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) #define RTC_SLOW_CLK_FREQ_32K 32768 @@ -210,7 +210,7 @@ typedef struct { rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set uint32_t clk_rtc_clk_div : 8; uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 90k clock adjustment parameter (higher value leads to lower frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index 409a39b6a7..8c42d24cde 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -178,7 +178,7 @@ typedef struct rtc_cpu_freq_config_s { * @brief RTC SLOW_CLK frequency values */ typedef enum { - RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator + RTC_SLOW_FREQ_RTC = 0, //!< Internal 90 kHz RC oscillator RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 } rtc_slow_freq_t; @@ -426,7 +426,7 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void); /** * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz * - * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 + * - if RTC_SLOW_FREQ_RTC is selected, returns ~90000 * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 * diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index d754d01da6..fc8c618c56 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -55,9 +55,9 @@ extern "C" { #define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) -#define RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_FREQ_90K 90000 +#define RTC_SLOW_CLK_FREQ_150K 150000 #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) #define RTC_SLOW_CLK_FREQ_32K 32768 @@ -214,7 +214,7 @@ typedef struct { rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set uint32_t clk_rtc_clk_div : 8; uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 90k clock adjustment parameter (higher value leads to lower frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) } rtc_clk_config_t; diff --git a/docs/en/api-guides/ulp-risc-v.rst b/docs/en/api-guides/ulp-risc-v.rst index fc6a195b95..3b4625a0c1 100644 --- a/docs/en/api-guides/ulp-risc-v.rst +++ b/docs/en/api-guides/ulp-risc-v.rst @@ -136,7 +136,9 @@ Once the program is loaded into RTC memory, the application can start it, callin ULP-RISC-V Program Flow ----------------------- -The ULP-RISC-V coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_riscv_run` is called. The timer counts the number of RTC_SLOW_CLK ticks (by default, produced by an internal 90 kHz RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register. When starting the ULP, ``RTC_CNTL_ULP_CP_TIMER_1_REG`` will be used to set the number of timer ticks. +{IDF_TARGET_RTC_CLK_FRE:default="150kHz", esp32s2="90kHz"} + +The ULP-RISC-V coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_riscv_run` is called. The timer counts the number of RTC_SLOW_CLK ticks (by default, produced by an internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register. When starting the ULP, ``RTC_CNTL_ULP_CP_TIMER_1_REG`` will be used to set the number of timer ticks. The application can set ULP timer period values (RTC_CNTL_ULP_CP_TIMER_1_REG) using the :cpp:func:`ulp_set_wakeup_period` function. diff --git a/docs/en/api-reference/system/system_time.rst b/docs/en/api-reference/system/system_time.rst index 9d3ba5ad50..396c48d05c 100644 --- a/docs/en/api-reference/system/system_time.rst +++ b/docs/en/api-reference/system/system_time.rst @@ -1,7 +1,7 @@ System Time =========== -{IDF_TARGET_RTC_CLK_FRE:default="90kHz", esp32="150kHz"} +{IDF_TARGET_RTC_CLK_FRE:default="150kHz", esp32s2="90kHz"} {IDF_TARGET_HARDWARE_DESIGN_URL:default="`ESP32 Hardware Design Guidelines `_", esp32="`ESP32 Hardware Design Guidelines `_", esp32s2="`ESP32-S2 Hardware Design Guidelines `_"} Overview