From 0a25960783398454666fb2dac21e63bfa21d4a47 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 28 May 2025 15:27:20 +0800 Subject: [PATCH 1/7] feat(soc): update modem syscon and lpcon register header and structure file for esp32c61 --- .../esp32c61/include/modem/modem_lpcon_reg.h | 808 +++++++------ .../include/modem/modem_lpcon_struct.h | 452 ++++--- .../esp32c61/include/modem/modem_syscon_reg.h | 1037 ++++++++--------- .../include/modem/modem_syscon_struct.h | 342 +++--- 4 files changed, 1370 insertions(+), 1269 deletions(-) diff --git a/components/soc/esp32c61/include/modem/modem_lpcon_reg.h b/components/soc/esp32c61/include/modem/modem_lpcon_reg.h index 2e16b2e54c..5ef865e64f 100644 --- a/components/soc/esp32c61/include/modem/modem_lpcon_reg.h +++ b/components/soc/esp32c61/include/modem/modem_lpcon_reg.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -11,366 +11,524 @@ extern "C" { #endif -#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) -/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_TEST_CONF_REG register + * need_des + */ +#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) +/** MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_EN (BIT(0)) -#define MODEM_LPCON_CLK_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_EN_V 0x1 +#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S) +#define MODEM_LPCON_CLK_EN_V 0x00000001U #define MODEM_LPCON_CLK_EN_S 0 -#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) -/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_LP_TIMER_CONF_REG register + * need_des + */ +#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) +/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 +/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 +/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 +/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 +/** MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S) +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) -/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_COEX_LP_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) +/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 +/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 +/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 +/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 +/** MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S) +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) -/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_WIFI_LP_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc) +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 +/** MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) -/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1 -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 -/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003 -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S)) -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3 +/** MODEM_LPCON_MODEM_SRC_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) +/** MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003U +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M (MODEM_LPCON_CLK_MODEM_AON_FORCE_V << MODEM_LPCON_CLK_MODEM_AON_FORCE_S) +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x00000003U #define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0 +/** MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V << MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x00000001U +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 -#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) -/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 -#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) -#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 +/** MODEM_LPCON_MODEM_32K_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) +/** MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003U +#define MODEM_LPCON_CLK_MODEM_32K_SEL_M (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S) +#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x00000003U #define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 -#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) -/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 -/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_V 0x1 -#define MODEM_LPCON_CLK_COEX_EN_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) +/** MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_EN_M (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S) +#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 +/** MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S) +#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_EN_S 1 +/** MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S) +#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U +#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 +/** MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_M (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S) +#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) -/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 -/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 -/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_V 0x1 -#define MODEM_LPCON_CLK_COEX_FO_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_CLK_CONF_FORCE_ON_REG register + * need_des + */ +#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c) +/** MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_FO_M (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S) +#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 +/** MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S) +#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_FO_S 1 +/** MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S) +#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U +#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 +/** MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_M (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S) +#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 +/** MODEM_LPCON_CLK_FE_MEM_FO : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_M (MODEM_LPCON_CLK_FE_MEM_FO_V << MODEM_LPCON_CLK_FE_MEM_FO_S) +#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 -#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) -/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 -/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) -#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 -/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF +/** MODEM_LPCON_CLK_CONF_POWER_ST_REG register + * need_des + */ +#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) +/** MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S) +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0x0000000FU #define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 +/** MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_COEX_ST_MAP_M (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S) +#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 +/** MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S) +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 +/** MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S) +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) -/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_V 0x1 -#define MODEM_LPCON_RST_LP_TIMER_S 3 -/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_I2C_MST (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_V 0x1 -#define MODEM_LPCON_RST_I2C_MST_S 2 -/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_COEX (BIT(1)) -#define MODEM_LPCON_RST_COEX_M (BIT(1)) -#define MODEM_LPCON_RST_COEX_V 0x1 -#define MODEM_LPCON_RST_COEX_S 1 -/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_RST_CONF_REG register + * need_des + */ +#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) +/** MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_RST_WIFIPWR (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_V 0x1 +#define MODEM_LPCON_RST_WIFIPWR_M (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S) +#define MODEM_LPCON_RST_WIFIPWR_V 0x00000001U #define MODEM_LPCON_RST_WIFIPWR_S 0 +/** MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_COEX (BIT(1)) +#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S) +#define MODEM_LPCON_RST_COEX_V 0x00000001U +#define MODEM_LPCON_RST_COEX_S 1 +/** MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_I2C_MST (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S) +#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U +#define MODEM_LPCON_RST_I2C_MST_S 2 +/** MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_M (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S) +#define MODEM_LPCON_RST_LP_TIMER_V 0x00000001U +#define MODEM_LPCON_RST_LP_TIMER_S 3 +/** MODEM_LPCON_RST_DCMEM : WO; bitpos: [4]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_DCMEM (BIT(4)) +#define MODEM_LPCON_RST_DCMEM_M (MODEM_LPCON_RST_DCMEM_V << MODEM_LPCON_RST_DCMEM_S) +#define MODEM_LPCON_RST_DCMEM_V 0x00000001U +#define MODEM_LPCON_RST_DCMEM_S 4 -#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) -/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)) -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F +/** MODEM_LPCON_TICK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) +/** MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W; bitpos: [5:0]; default: 39; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003FU +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M (MODEM_LPCON_MODEM_PWR_TICK_TARGET_V << MODEM_LPCON_MODEM_PWR_TICK_TARGET_S) +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x0000003FU #define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0 -#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 -/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)) -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 -/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1 -#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 -/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007 -#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S)) -#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7 -#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 -/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_BC_MEM_FORCE_S 15 -/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_MODE 0x00000007 -#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S)) -#define MODEM_LPCON_BC_MEM_MODE_V 0x7 -#define MODEM_LPCON_BC_MEM_MODE_S 12 -/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1 -#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 -/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007 -#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S)) -#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7 -#define MODEM_LPCON_PBUS_MEM_MODE_S 8 -/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_AGC_MEM_FORCE_S 7 -/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_MODE 0x00000007 -#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S)) -#define MODEM_LPCON_AGC_MEM_MODE_V 0x7 -#define MODEM_LPCON_AGC_MEM_MODE_S 4 -/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_DC_MEM_FORCE_S 3 -/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_MODE 0x00000007 -#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S)) -#define MODEM_LPCON_DC_MEM_MODE_V 0x7 +/** MODEM_LPCON_MEM_CONF_REG register + * need_des + */ +#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2c) +/** MODEM_LPCON_DC_MEM_MODE : R/W; bitpos: [2:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_DC_MEM_MODE 0x00000007U +#define MODEM_LPCON_DC_MEM_MODE_M (MODEM_LPCON_DC_MEM_MODE_V << MODEM_LPCON_DC_MEM_MODE_S) +#define MODEM_LPCON_DC_MEM_MODE_V 0x00000007U #define MODEM_LPCON_DC_MEM_MODE_S 0 +/** MODEM_LPCON_DC_MEM_FORCE : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) +#define MODEM_LPCON_DC_MEM_FORCE_M (MODEM_LPCON_DC_MEM_FORCE_V << MODEM_LPCON_DC_MEM_FORCE_S) +#define MODEM_LPCON_DC_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_DC_MEM_FORCE_S 3 +/** MODEM_LPCON_AGC_MEM_MODE : R/W; bitpos: [6:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_AGC_MEM_MODE 0x00000007U +#define MODEM_LPCON_AGC_MEM_MODE_M (MODEM_LPCON_AGC_MEM_MODE_V << MODEM_LPCON_AGC_MEM_MODE_S) +#define MODEM_LPCON_AGC_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_AGC_MEM_MODE_S 4 +/** MODEM_LPCON_AGC_MEM_FORCE : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) +#define MODEM_LPCON_AGC_MEM_FORCE_M (MODEM_LPCON_AGC_MEM_FORCE_V << MODEM_LPCON_AGC_MEM_FORCE_S) +#define MODEM_LPCON_AGC_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_AGC_MEM_FORCE_S 7 +/** MODEM_LPCON_PBUS_MEM_MODE : R/W; bitpos: [10:8]; default: 0; + * need_des + */ +#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007U +#define MODEM_LPCON_PBUS_MEM_MODE_M (MODEM_LPCON_PBUS_MEM_MODE_V << MODEM_LPCON_PBUS_MEM_MODE_S) +#define MODEM_LPCON_PBUS_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_PBUS_MEM_MODE_S 8 +/** MODEM_LPCON_PBUS_MEM_FORCE : R/W; bitpos: [11]; default: 1; + * need_des + */ +#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) +#define MODEM_LPCON_PBUS_MEM_FORCE_M (MODEM_LPCON_PBUS_MEM_FORCE_V << MODEM_LPCON_PBUS_MEM_FORCE_S) +#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 +/** MODEM_LPCON_BC_MEM_MODE : R/W; bitpos: [14:12]; default: 0; + * need_des + */ +#define MODEM_LPCON_BC_MEM_MODE 0x00000007U +#define MODEM_LPCON_BC_MEM_MODE_M (MODEM_LPCON_BC_MEM_MODE_V << MODEM_LPCON_BC_MEM_MODE_S) +#define MODEM_LPCON_BC_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_BC_MEM_MODE_S 12 +/** MODEM_LPCON_BC_MEM_FORCE : R/W; bitpos: [15]; default: 1; + * need_des + */ +#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) +#define MODEM_LPCON_BC_MEM_FORCE_M (MODEM_LPCON_BC_MEM_FORCE_V << MODEM_LPCON_BC_MEM_FORCE_S) +#define MODEM_LPCON_BC_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_BC_MEM_FORCE_S 15 +/** MODEM_LPCON_I2C_MST_MEM_MODE : R/W; bitpos: [18:16]; default: 0; + * need_des + */ +#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007U +#define MODEM_LPCON_I2C_MST_MEM_MODE_M (MODEM_LPCON_I2C_MST_MEM_MODE_V << MODEM_LPCON_I2C_MST_MEM_MODE_S) +#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 +/** MODEM_LPCON_I2C_MST_MEM_FORCE : R/W; bitpos: [19]; default: 1; + * need_des + */ +#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (MODEM_LPCON_I2C_MST_MEM_FORCE_V << MODEM_LPCON_I2C_MST_MEM_FORCE_S) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 +/** MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007U +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M (MODEM_LPCON_CHAN_FREQ_MEM_MODE_V << MODEM_LPCON_CHAN_FREQ_MEM_MODE_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 +/** MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W; bitpos: [23]; default: 1; + * need_des + */ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 -#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) -/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_LPCON_MEM_RF1_AUX_CTRL_REG register + * need_des + */ +#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) +/** MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFFU +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S) +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0 -#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) -/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_LPCON_MEM_RF2_AUX_CTRL_REG register + * need_des + */ +#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) +/** MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFFU +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S) +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0 -#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) -/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_V 0x1 -#define MODEM_LPCON_AGC_MEM_EN_S 2 -/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_V 0x1 -#define MODEM_LPCON_PBUS_MEM_EN_S 1 -/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_APB_MEM_SEL_REG register + * need_des + */ +#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) +/** MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (MODEM_LPCON_CHAN_FREQ_MEM_EN_V << MODEM_LPCON_CHAN_FREQ_MEM_EN_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x00000001U #define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0 +/** MODEM_LPCON_PBUS_MEM_EN : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) +#define MODEM_LPCON_PBUS_MEM_EN_M (MODEM_LPCON_PBUS_MEM_EN_V << MODEM_LPCON_PBUS_MEM_EN_S) +#define MODEM_LPCON_PBUS_MEM_EN_V 0x00000001U +#define MODEM_LPCON_PBUS_MEM_EN_S 1 +/** MODEM_LPCON_AGC_MEM_EN : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) +#define MODEM_LPCON_AGC_MEM_EN_M (MODEM_LPCON_AGC_MEM_EN_V << MODEM_LPCON_AGC_MEM_EN_S) +#define MODEM_LPCON_AGC_MEM_EN_V 0x00000001U +#define MODEM_LPCON_AGC_MEM_EN_S 2 -#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C) -/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */ -/*description: .*/ -#define MODEM_LPCON_DATE 0x0FFFFFFF -#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) -#define MODEM_LPCON_DATE_V 0xFFFFFFF +/** MODEM_LPCON_DCMEM_VALID_0_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_0_REG (DR_REG_MODEM_LPCON_BASE + 0x3c) +/** MODEM_LPCON__DCMEM_VALID_0 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_0 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_0_M (MODEM_LPCON__DCMEM_VALID_0_V << MODEM_LPCON__DCMEM_VALID_0_S) +#define MODEM_LPCON__DCMEM_VALID_0_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_0_S 0 + +/** MODEM_LPCON_DCMEM_VALID_1_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_1_REG (DR_REG_MODEM_LPCON_BASE + 0x40) +/** MODEM_LPCON__DCMEM_VALID_1 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_1 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_1_M (MODEM_LPCON__DCMEM_VALID_1_V << MODEM_LPCON__DCMEM_VALID_1_S) +#define MODEM_LPCON__DCMEM_VALID_1_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_1_S 0 + +/** MODEM_LPCON_DCMEM_VALID_2_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_2_REG (DR_REG_MODEM_LPCON_BASE + 0x44) +/** MODEM_LPCON__DCMEM_VALID_2 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_2 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_2_M (MODEM_LPCON__DCMEM_VALID_2_V << MODEM_LPCON__DCMEM_VALID_2_S) +#define MODEM_LPCON__DCMEM_VALID_2_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_2_S 0 + +/** MODEM_LPCON_DCMEM_VALID_3_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_3_REG (DR_REG_MODEM_LPCON_BASE + 0x48) +/** MODEM_LPCON__DCMEM_VALID_3 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_3 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_3_M (MODEM_LPCON__DCMEM_VALID_3_V << MODEM_LPCON__DCMEM_VALID_3_S) +#define MODEM_LPCON__DCMEM_VALID_3_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_3_S 0 + +/** MODEM_LPCON_DATE_REG register + * need_des + */ +#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x4c) +/** MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 37814640; + * need_des + */ +#define MODEM_LPCON_DATE 0x0FFFFFFFU +#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S) +#define MODEM_LPCON_DATE_V 0x0FFFFFFFU #define MODEM_LPCON_DATE_S 0 #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/modem/modem_lpcon_struct.h b/components/soc/esp32c61/include/modem/modem_lpcon_struct.h index 6c695e5413..98d722fcf7 100644 --- a/components/soc/esp32c61/include/modem/modem_lpcon_struct.h +++ b/components/soc/esp32c61/include/modem/modem_lpcon_struct.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,240 +10,228 @@ extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t clk_en : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 30; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t clk_lp_timer_sel_osc_slow : 1; - uint32_t clk_lp_timer_sel_osc_fast : 1; - uint32_t clk_lp_timer_sel_xtal : 1; - uint32_t clk_lp_timer_sel_xtal32k : 1; - uint32_t clk_lp_timer_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } lp_timer_conf; - union { - struct { - uint32_t clk_coex_lp_sel_osc_slow : 1; - uint32_t clk_coex_lp_sel_osc_fast : 1; - uint32_t clk_coex_lp_sel_xtal : 1; - uint32_t clk_coex_lp_sel_xtal32k : 1; - uint32_t clk_coex_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } coex_lp_clk_conf; - union { - struct { - uint32_t clk_wifipwr_lp_sel_osc_slow: 1; - uint32_t clk_wifipwr_lp_sel_osc_fast: 1; - uint32_t clk_wifipwr_lp_sel_xtal : 1; - uint32_t clk_wifipwr_lp_sel_xtal32k: 1; - uint32_t clk_wifipwr_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } wifi_lp_clk_conf; - union { - struct { - uint32_t clk_modem_aon_force : 2; - uint32_t modem_pwr_clk_src_fo : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } modem_src_clk_conf; - union { - struct { - uint32_t clk_modem_32k_sel : 2; - uint32_t reserved2 : 30; - }; - uint32_t val; - } modem_32k_clk_conf; - union { - struct { - uint32_t clk_wifipwr_en : 1; - uint32_t clk_coex_en : 1; - uint32_t clk_i2c_mst_en : 1; - uint32_t clk_lp_timer_en : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t clk_wifipwr_fo : 1; - uint32_t clk_coex_fo : 1; - uint32_t clk_i2c_mst_fo : 1; - uint32_t clk_lp_timer_fo : 1; - uint32_t clk_fe_mem_fo : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 16; - uint32_t clk_wifipwr_st_map : 4; - uint32_t clk_coex_st_map : 4; - uint32_t clk_i2c_mst_st_map : 4; - uint32_t clk_lp_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t rst_wifipwr : 1; - uint32_t rst_coex : 1; - uint32_t rst_i2c_mst : 1; - uint32_t rst_lp_timer : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } rst_conf; - union { - struct { - uint32_t modem_pwr_tick_target : 6; - uint32_t reserved6 : 26; - }; - uint32_t val; - } tick_conf; - union { - struct { - uint32_t dc_mem_mode : 3; - uint32_t dc_mem_force : 1; - uint32_t agc_mem_mode : 3; - uint32_t agc_mem_force : 1; - uint32_t pbus_mem_mode : 3; - uint32_t pbus_mem_force : 1; - uint32_t bc_mem_mode : 3; - uint32_t bc_mem_force : 1; - uint32_t i2c_mst_mem_mode : 3; - uint32_t i2c_mst_mem_force : 1; - uint32_t chan_freq_mem_mode : 3; - uint32_t chan_freq_mem_force : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } mem_conf; - uint32_t mem_rf1_aux_ctrl; - uint32_t mem_rf2_aux_ctrl; - union { - struct { - uint32_t chan_freq_mem_en : 1; - uint32_t pbus_mem_en : 1; - uint32_t agc_mem_en : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } apb_mem_sel; - union { - struct { - uint32_t date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; +/** Group: configure_register */ +typedef union { + struct { + uint32_t clk_en: 1; + uint32_t reserved_1: 31; + }; + uint32_t val; +} modem_lpcon_test_conf_t; + +typedef union { + struct { + uint32_t clk_lp_timer_sel_osc_slow: 1; + uint32_t clk_lp_timer_sel_osc_fast: 1; + uint32_t clk_lp_timer_sel_xtal: 1; + uint32_t clk_lp_timer_sel_xtal32k: 1; + uint32_t clk_lp_timer_div_num: 12; + uint32_t reserved_16: 16; + }; + uint32_t val; +} modem_lpcon_lp_timer_conf_t; + +typedef union { + struct { + uint32_t clk_coex_lp_sel_osc_slow: 1; + uint32_t clk_coex_lp_sel_osc_fast: 1; + uint32_t clk_coex_lp_sel_xtal: 1; + uint32_t clk_coex_lp_sel_xtal32k: 1; + uint32_t clk_coex_lp_div_num: 12; + uint32_t reserved_16: 16; + }; + uint32_t val; +} modem_lpcon_coex_lp_clk_conf_t; + +typedef union { + struct { + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal: 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num: 12; + uint32_t reserved_16: 16; + }; + uint32_t val; +} modem_lpcon_wifi_lp_clk_conf_t; + +typedef union { + struct { + uint32_t clk_modem_aon_force: 2; + uint32_t modem_pwr_clk_src_fo: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} modem_lpcon_modem_src_clk_conf_t; + +typedef union { + struct { + uint32_t clk_modem_32k_sel: 2; + uint32_t reserved_2: 30; + }; + uint32_t val; +} modem_lpcon_modem_32k_clk_conf_t; + +typedef union { + struct { + uint32_t clk_wifipwr_en: 1; + uint32_t clk_coex_en: 1; + uint32_t clk_i2c_mst_en: 1; + uint32_t clk_lp_timer_en: 1; + uint32_t reserved_4: 28; + }; + uint32_t val; +} modem_lpcon_clk_conf_t; + +typedef union { + struct { + uint32_t clk_wifipwr_fo: 1; + uint32_t clk_coex_fo: 1; + uint32_t clk_i2c_mst_fo: 1; + uint32_t clk_lp_timer_fo: 1; + uint32_t clk_fe_mem_fo: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} modem_lpcon_clk_conf_force_on_t; + +typedef union { + struct { + uint32_t reserved_0: 16; + uint32_t clk_wifipwr_st_map: 4; + uint32_t clk_coex_st_map: 4; + uint32_t clk_i2c_mst_st_map: 4; + uint32_t clk_lp_apb_st_map: 4; + }; + uint32_t val; +} modem_lpcon_clk_conf_power_st_t; + +typedef union { + struct { + uint32_t rst_wifipwr: 1; + uint32_t rst_coex: 1; + uint32_t rst_i2c_mst: 1; + uint32_t rst_lp_timer: 1; + uint32_t rst_dcmem: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} modem_lpcon_rst_conf_t; + +typedef union { + struct { + uint32_t modem_pwr_tick_target: 6; + uint32_t reserved_6: 26; + }; + uint32_t val; +} modem_lpcon_tick_conf_t; + +typedef union { + struct { + uint32_t dc_mem_mode: 3; + uint32_t dc_mem_force: 1; + uint32_t agc_mem_mode: 3; + uint32_t agc_mem_force: 1; + uint32_t pbus_mem_mode: 3; + uint32_t pbus_mem_force: 1; + uint32_t bc_mem_mode: 3; + uint32_t bc_mem_force: 1; + uint32_t i2c_mst_mem_mode: 3; + uint32_t i2c_mst_mem_force: 1; + uint32_t chan_freq_mem_mode: 3; + uint32_t chan_freq_mem_force: 1; + uint32_t reserved_24: 8; + }; + uint32_t val; +} modem_lpcon_mem_conf_t; + +typedef union { + struct { + uint32_t modem_pwr_rf1_aux_ctrl: 32; + }; + uint32_t val; +} modem_lpcon_mem_rf1_aux_ctrl_t; + +typedef union { + struct { + uint32_t modem_pwr_rf2_aux_ctrl: 32; + }; + uint32_t val; +} modem_lpcon_mem_rf2_aux_ctrl_t; + +typedef union { + struct { + uint32_t chan_freq_mem_en: 1; + uint32_t pbus_mem_en: 1; + uint32_t agc_mem_en: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} modem_lpcon_apb_mem_sel_t; + +typedef union { + struct { + uint32_t _dcmem_valid_0: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_0_t; + +typedef union { + struct { + uint32_t _dcmem_valid_1: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_1_t; + +typedef union { + struct { + uint32_t _dcmem_valid_2: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_2_t; + +typedef union { + struct { + uint32_t _dcmem_valid_3: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_3_t; + +typedef union { + struct { + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} modem_lpcon_date_t; + +typedef struct { + volatile modem_lpcon_test_conf_t test_conf; + volatile modem_lpcon_lp_timer_conf_t lp_timer_conf; + volatile modem_lpcon_coex_lp_clk_conf_t coex_lp_clk_conf; + volatile modem_lpcon_wifi_lp_clk_conf_t wifi_lp_clk_conf; + volatile modem_lpcon_modem_src_clk_conf_t modem_src_clk_conf; + volatile modem_lpcon_modem_32k_clk_conf_t modem_32k_clk_conf; + volatile modem_lpcon_clk_conf_t clk_conf; + volatile modem_lpcon_clk_conf_force_on_t clk_conf_force_on; + volatile modem_lpcon_clk_conf_power_st_t clk_conf_power_st; + volatile modem_lpcon_rst_conf_t rst_conf; + volatile modem_lpcon_tick_conf_t tick_conf; + volatile modem_lpcon_mem_conf_t mem_conf; + volatile modem_lpcon_mem_rf1_aux_ctrl_t mem_rf1_aux_ctrl; + volatile modem_lpcon_mem_rf2_aux_ctrl_t mem_rf2_aux_ctrl; + volatile modem_lpcon_apb_mem_sel_t apb_mem_sel; + volatile modem_lpcon_dcmem_valid_0_t dcmem_valid_0; + volatile modem_lpcon_dcmem_valid_1_t dcmem_valid_1; + volatile modem_lpcon_dcmem_valid_2_t dcmem_valid_2; + volatile modem_lpcon_dcmem_valid_3_t dcmem_valid_3; + volatile modem_lpcon_date_t date; } modem_lpcon_dev_t; extern modem_lpcon_dev_t MODEM_LPCON; #ifndef __cplusplus -_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure"); +_Static_assert(sizeof(modem_lpcon_dev_t) == 0x50, "Invalid size of modem_lpcon_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/modem/modem_syscon_reg.h b/components/soc/esp32c61/include/modem/modem_syscon_reg.h index bf811fff09..f94698d8e7 100644 --- a/components/soc/esp32c61/include/modem/modem_syscon_reg.h +++ b/components/soc/esp32c61/include/modem/modem_syscon_reg.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -11,582 +11,507 @@ extern "C" { #endif -#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) -/* MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE (BIT(9)) -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_M (BIT(9)) -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V 0x1 -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S 9 -/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x1 -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 -/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 -/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 -/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 -/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 -/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 -/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_TEST_CONF_REG register **/ +#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) +/** MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_CLK_EN (BIT(0)) -#define MODEM_SYSCON_CLK_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_EN_V 0x1 +#define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S) +#define MODEM_SYSCON_CLK_EN_V 0x00000001U #define MODEM_SYSCON_CLK_EN_S 0 +/** MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W; bitpos: [1]; default: 0; **/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V << MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x00000001U +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 +/** MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W; bitpos: [2]; default: 0; **/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V << MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x00000001U +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 +/** MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W; bitpos: [3]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V << MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 +/** MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W; bitpos: [4]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (MODEM_SYSCON_FPGA_DEBUG_CLK80_V << MODEM_SYSCON_FPGA_DEBUG_CLK80_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 +/** MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W; bitpos: [5]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (MODEM_SYSCON_FPGA_DEBUG_CLK40_V << MODEM_SYSCON_FPGA_DEBUG_CLK40_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 +/** MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W; bitpos: [6]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (MODEM_SYSCON_FPGA_DEBUG_CLK20_V << MODEM_SYSCON_FPGA_DEBUG_CLK20_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 +/** MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W; bitpos: [7]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (MODEM_SYSCON_FPGA_DEBUG_CLK10_V << MODEM_SYSCON_FPGA_DEBUG_CLK10_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 +/** MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W; bitpos: [8]; default: 1; **/ +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V << MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x00000001U +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 +/** MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE (BIT(9)) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_M (MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V << MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V 0x00000001U +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S 9 -#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) -/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 -/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 -/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 -/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 -/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 -/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 -/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 -/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 -#define MODEM_SYSCON_CLK_ETM_EN_S 22 -/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 -/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x1 -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 -/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 -/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 -/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 -/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */ -/*description: .*/ -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S)) -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0xFF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 -/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_CLK_CONF_REG register **/ +#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) +/** MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x1 +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V << MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S) +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x00000001U #define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S 0 +/** MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W; bitpos: [8:1]; default: 1; **/ +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FFU +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M (MODEM_SYSCON_PWDET_CLK_DIV_NUM_V << MODEM_SYSCON_PWDET_CLK_DIV_NUM_S) +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0x000000FFU +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 +/** MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V << MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x00000001U +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 +/** MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W; bitpos: [10]; default: 0; **/ +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V << MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x00000001U +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 +/** MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W; bitpos: [11]; default: 0; **/ +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V << MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x00000001U +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 +/** MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [12]; default: 0; **/ +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V << MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x00000001U +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 +/** MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 1; **/ +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 +/** MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; **/ +#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S) +#define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ETM_EN_S 22 +/** MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S) +#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 +/** MODEM_SYSCON_CLK_ZBMAC_EN : R/W; bitpos: [24]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_M (MODEM_SYSCON_CLK_ZBMAC_EN_V << MODEM_SYSCON_CLK_ZBMAC_EN_S) +#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 +/** MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 +/** MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 +/** MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 +/** MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 +/** MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 +/** MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; **/ +#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 +/** MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; **/ +#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) -/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 -/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 -#define MODEM_SYSCON_CLK_ETM_FO_S 28 -/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 -/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 -/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 -/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 -/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_FO_S 5 -/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 -/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_FO_S 3 -/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 -/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_CLK_CONF_FORCE_ON_REG register **/ +#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) +/** MODEM_SYSCON_CLK_WIFIBB_FO : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_FO_M (MODEM_SYSCON_CLK_WIFIBB_FO_V << MODEM_SYSCON_CLK_WIFIBB_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x00000001U #define MODEM_SYSCON_CLK_WIFIBB_FO_S 0 +/** MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [1]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 +/** MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [2]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 +/** MODEM_SYSCON_CLK_FE_FO : R/W; bitpos: [3]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_M (MODEM_SYSCON_CLK_FE_FO_V << MODEM_SYSCON_CLK_FE_FO_S) +#define MODEM_SYSCON_CLK_FE_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_FO_S 3 +/** MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [4]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_M (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S) +#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 +/** MODEM_SYSCON_CLK_BTBB_FO : R/W; bitpos: [5]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_M (MODEM_SYSCON_CLK_BTBB_FO_V << MODEM_SYSCON_CLK_BTBB_FO_S) +#define MODEM_SYSCON_CLK_BTBB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BTBB_FO_S 5 +/** MODEM_SYSCON_CLK_BTMAC_FO : R/W; bitpos: [6]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_M (MODEM_SYSCON_CLK_BTMAC_FO_V << MODEM_SYSCON_CLK_BTMAC_FO_S) +#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 +/** MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [7]; default: 0; **/ +#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_M (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S) +#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 +/** MODEM_SYSCON_CLK_ZBMAC_FO : R/W; bitpos: [8]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_M (MODEM_SYSCON_CLK_ZBMAC_FO_V << MODEM_SYSCON_CLK_ZBMAC_FO_S) +#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 +/** MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (MODEM_SYSCON_CLK_ZBMAC_APB_FO_V << MODEM_SYSCON_CLK_ZBMAC_APB_FO_S) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 +/** MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [28]; default: 0; **/ +#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S) +#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ETM_FO_S 28 +/** MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 +/** MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; **/ +#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 +/** MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; **/ +#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) -/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 -/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 -/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 -/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S)) -#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 -/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S)) -#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 -/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF +/** MODEM_SYSCON_CLK_CONF_POWER_ST_REG register **/ +#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc) +/** MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_ZB_ST_MAP_M (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S) +#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0x0000000FU #define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 +/** MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_FE_ST_MAP_M (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S) +#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 +/** MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; **/ +#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_BT_ST_MAP_M (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S) +#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 +/** MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S) +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 +/** MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S) +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 +/** MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S) +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 -#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) -/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 -#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 -#define MODEM_SYSCON_RST_BLE_TIMER_S 30 -/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 -#define MODEM_SYSCON_RST_MODEM_SEC_S 29 -/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 -#define MODEM_SYSCON_RST_MODEM_BAH_S 27 -/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 -#define MODEM_SYSCON_RST_MODEM_CCM_S 26 -/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 -#define MODEM_SYSCON_RST_MODEM_ECB_S 25 -/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_S 24 -/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_M (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 -/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ETM (BIT(22)) -#define MODEM_SYSCON_RST_ETM_M (BIT(22)) -#define MODEM_SYSCON_RST_ETM_V 0x1 -#define MODEM_SYSCON_RST_ETM_S 22 -/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_S 18 -/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_APB_S 17 -/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_S 16 -/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_APB_S 15 -/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE (BIT(14)) -#define MODEM_SYSCON_RST_FE_M (BIT(14)) -#define MODEM_SYSCON_RST_FE_V 0x1 -#define MODEM_SYSCON_RST_FE_S 14 -/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_V 0x1 -#define MODEM_SYSCON_RST_FE_AHB_S 13 -/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_ADC_S 12 -/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_V 0x1 -#define MODEM_SYSCON_RST_FE_DAC_S 11 -/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 -/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_V 0x1 -#define MODEM_SYSCON_RST_WIFIMAC_S 9 -/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_MODEM_RST_CONF_REG register **/ +#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) +/** MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; **/ #define MODEM_SYSCON_RST_WIFIBB (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_V 0x1 +#define MODEM_SYSCON_RST_WIFIBB_M (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S) +#define MODEM_SYSCON_RST_WIFIBB_V 0x00000001U #define MODEM_SYSCON_RST_WIFIBB_S 8 +/** MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_M (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S) +#define MODEM_SYSCON_RST_WIFIMAC_V 0x00000001U +#define MODEM_SYSCON_RST_WIFIMAC_S 9 +/** MODEM_SYSCON_RST_FE_PWDET_ADC : R/W; bitpos: [10]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (MODEM_SYSCON_RST_FE_PWDET_ADC_V << MODEM_SYSCON_RST_FE_PWDET_ADC_S) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x00000001U +#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 +/** MODEM_SYSCON_RST_FE_DAC : R/W; bitpos: [11]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_M (MODEM_SYSCON_RST_FE_DAC_V << MODEM_SYSCON_RST_FE_DAC_S) +#define MODEM_SYSCON_RST_FE_DAC_V 0x00000001U +#define MODEM_SYSCON_RST_FE_DAC_S 11 +/** MODEM_SYSCON_RST_FE_ADC : R/W; bitpos: [12]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_M (MODEM_SYSCON_RST_FE_ADC_V << MODEM_SYSCON_RST_FE_ADC_S) +#define MODEM_SYSCON_RST_FE_ADC_V 0x00000001U +#define MODEM_SYSCON_RST_FE_ADC_S 12 +/** MODEM_SYSCON_RST_FE_AHB : R/W; bitpos: [13]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_M (MODEM_SYSCON_RST_FE_AHB_V << MODEM_SYSCON_RST_FE_AHB_S) +#define MODEM_SYSCON_RST_FE_AHB_V 0x00000001U +#define MODEM_SYSCON_RST_FE_AHB_S 13 +/** MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; **/ +#define MODEM_SYSCON_RST_FE (BIT(14)) +#define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S) +#define MODEM_SYSCON_RST_FE_V 0x00000001U +#define MODEM_SYSCON_RST_FE_S 14 +/** MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; **/ +#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S) +#define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_APB_S 15 +/** MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; **/ +#define MODEM_SYSCON_RST_BTMAC (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S) +#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_S 16 +/** MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; **/ +#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S) +#define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_APB_S 17 +/** MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; **/ +#define MODEM_SYSCON_RST_BTBB (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S) +#define MODEM_SYSCON_RST_BTBB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_S 18 +/** MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; **/ +#define MODEM_SYSCON_RST_ETM (BIT(22)) +#define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S) +#define MODEM_SYSCON_RST_ETM_V 0x00000001U +#define MODEM_SYSCON_RST_ETM_S 22 +/** MODEM_SYSCON_RST_ZBMAC_APB : R/W; bitpos: [23]; default: 0; **/ +#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) +#define MODEM_SYSCON_RST_ZBMAC_APB_M (MODEM_SYSCON_RST_ZBMAC_APB_V << MODEM_SYSCON_RST_ZBMAC_APB_S) +#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x00000001U +#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 +/** MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; **/ +#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S) +#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U +#define MODEM_SYSCON_RST_ZBMAC_S 24 +/** MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S) +#define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_ECB_S 25 +/** MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S) +#define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_CCM_S 26 +/** MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S) +#define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_BAH_S 27 +/** MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S) +#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_SEC_S 29 +/** MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; **/ +#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S) +#define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U +#define MODEM_SYSCON_RST_BLE_TIMER_S 30 +/** MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; **/ +#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S) +#define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U +#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) -/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 -/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 -/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 -/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 -/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_EN_S 17 -/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 -/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 -/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 -/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 -/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 -/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 -/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 -/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 -/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 -/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 -/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 -/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 -/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 -/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 -/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 -/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_CLK_CONF1_REG register **/ +#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) +/** MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x00000001U #define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 +/** MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 +/** MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 +/** MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 +/** MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 +/** MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 +/** MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 +/** MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 +/** MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 +/** MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 +/** MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 +/** MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_M (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S) +#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 +/** MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_M (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S) +#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 +/** MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_M (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S) +#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 +/** MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_M (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S) +#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 +/** MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [15]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S) +#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 +/** MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [16]; default: 0; **/ +#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S) +#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 +/** MODEM_SYSCON_CLK_BTBB_EN : R/W; bitpos: [17]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_M (MODEM_SYSCON_CLK_BTBB_EN_V << MODEM_SYSCON_CLK_BTBB_EN_S) +#define MODEM_SYSCON_CLK_BTBB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BTBB_EN_S 17 +/** MODEM_SYSCON_CLK_BTMAC_EN : R/W; bitpos: [18]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_M (MODEM_SYSCON_CLK_BTMAC_EN_V << MODEM_SYSCON_CLK_BTMAC_EN_S) +#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 +/** MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W; bitpos: [19]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V << MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 +/** MODEM_SYSCON_CLK_FE_ADC_EN : R/W; bitpos: [20]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_M (MODEM_SYSCON_CLK_FE_ADC_EN_V << MODEM_SYSCON_CLK_FE_ADC_EN_S) +#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 +/** MODEM_SYSCON_CLK_FE_DAC_EN : R/W; bitpos: [21]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_M (MODEM_SYSCON_CLK_FE_DAC_EN_V << MODEM_SYSCON_CLK_FE_DAC_EN_S) +#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 -#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) -/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF -#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S)) -#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +/** MODEM_SYSCON_WIFI_BB_CFG_REG register **/ +#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) +/** MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; **/ +#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFFU +#define MODEM_SYSCON_WIFI_BB_CFG_M (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S) +#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFFU #define MODEM_SYSCON_WIFI_BB_CFG_S 0 -#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) -/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_SYSCON_FE_CFG_REG register **/ +#define MODEM_SYSCON_FE_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c) +/** MODEM_SYSCON_FE_CFG : R/W; bitpos: [31:0]; default: 0; **/ +#define MODEM_SYSCON_FE_CFG 0xFFFFFFFFU +#define MODEM_SYSCON_FE_CFG_M (MODEM_SYSCON_FE_CFG_V << MODEM_SYSCON_FE_CFG_S) +#define MODEM_SYSCON_FE_CFG_V 0xFFFFFFFFU +#define MODEM_SYSCON_FE_CFG_S 0 + +/** MODEM_SYSCON_MEM_RF1_CONF_REG register **/ +#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) +/** MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; **/ +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFFU +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M (MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V << MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S) +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0 -#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) -/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_SYSCON_MEM_RF2_CONF_REG register **/ +#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) +/** MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; **/ +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFFU +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M (MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V << MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S) +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0 -#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) -/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2401180 ; */ -/*description: .*/ -#define MODEM_SYSCON_DATE 0x0FFFFFFF -#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) -#define MODEM_SYSCON_DATE_V 0xFFFFFFF +/** MODEM_SYSCON_DATE_REG register **/ +#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x28) +/** MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 37823072; **/ +#define MODEM_SYSCON_DATE 0x0FFFFFFFU +#define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S) +#define MODEM_SYSCON_DATE_V 0x0FFFFFFFU #define MODEM_SYSCON_DATE_S 0 #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/modem/modem_syscon_struct.h b/components/soc/esp32c61/include/modem/modem_syscon_struct.h index 101c41dd43..8e7d5f6d5a 100644 --- a/components/soc/esp32c61/include/modem/modem_syscon_struct.h +++ b/components/soc/esp32c61/include/modem/modem_syscon_struct.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,164 +10,194 @@ extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t clk_en : 1; - uint32_t modem_ant_force_sel_bt : 1; - uint32_t modem_ant_force_sel_wifi : 1; - uint32_t fpga_debug_clkswitch : 1; - uint32_t fpga_debug_clk80 : 1; - uint32_t fpga_debug_clk40 : 1; - uint32_t fpga_debug_clk20 : 1; - uint32_t fpga_debug_clk10 : 1; - uint32_t modem_mem_mode_force : 1; - uint32_t modem_dis_wifi6_force : 1; - uint32_t reserved10 : 22; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t pwdet_sar_clock_ena : 1; - uint32_t pwdet_clk_div_num : 8; - uint32_t clk_tx_dac_inv_ena : 1; - uint32_t clk_rx_adc_inv_ena : 1; - uint32_t clk_pwdet_adc_inv_ena : 1; - uint32_t clk_i2c_mst_sel_160m : 1; - uint32_t reserved13 : 8; - uint32_t clk_data_dump_mux : 1; - uint32_t clk_etm_en : 1; - uint32_t clk_zb_apb_en : 1; - uint32_t clk_zbmac_en : 1; - uint32_t clk_modem_sec_ecb_en : 1; - uint32_t clk_modem_sec_ccm_en : 1; - uint32_t clk_modem_sec_bah_en : 1; - uint32_t clk_modem_sec_apb_en : 1; - uint32_t clk_modem_sec_en : 1; - uint32_t clk_ble_timer_en : 1; - uint32_t clk_data_dump_en : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t clk_wifibb_fo : 1; - uint32_t clk_wifimac_fo : 1; - uint32_t clk_wifi_apb_fo : 1; - uint32_t clk_fe_fo : 1; - uint32_t clk_fe_apb_fo : 1; - uint32_t clk_btbb_fo : 1; - uint32_t clk_btmac_fo : 1; - uint32_t clk_bt_apb_fo : 1; - uint32_t clk_zbmac_fo : 1; - uint32_t clk_zbmac_apb_fo : 1; - uint32_t reserved10 : 13; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t clk_etm_fo : 1; - uint32_t clk_modem_sec_fo : 1; - uint32_t clk_ble_timer_fo : 1; - uint32_t clk_data_dump_fo : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 8; - uint32_t clk_zb_st_map : 4; - uint32_t clk_fe_st_map : 4; - uint32_t clk_bt_st_map : 4; - uint32_t clk_wifi_st_map : 4; - uint32_t clk_modem_peri_st_map : 4; - uint32_t clk_modem_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 1; - uint32_t reserved3 : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t rst_wifibb : 1; - uint32_t rst_wifimac : 1; - uint32_t rst_fe_pwdet_adc : 1; - uint32_t rst_fe_dac : 1; - uint32_t rst_fe_adc : 1; - uint32_t rst_fe_ahb : 1; - uint32_t rst_fe : 1; - uint32_t rst_btmac_apb : 1; - uint32_t rst_btmac : 1; - uint32_t rst_btbb_apb : 1; - uint32_t rst_btbb : 1; - uint32_t reserved19 : 3; - uint32_t rst_etm : 1; - uint32_t rst_zbmac_apb : 1; - uint32_t rst_zbmac : 1; - uint32_t rst_modem_ecb : 1; - uint32_t rst_modem_ccm : 1; - uint32_t rst_modem_bah : 1; - uint32_t reserved28 : 1; - uint32_t rst_modem_sec : 1; - uint32_t rst_ble_timer : 1; - uint32_t rst_data_dump : 1; - }; - uint32_t val; - } modem_rst_conf; - union { - struct { - uint32_t clk_wifibb_22m_en : 1; - uint32_t clk_wifibb_40m_en : 1; - uint32_t clk_wifibb_44m_en : 1; - uint32_t clk_wifibb_80m_en : 1; - uint32_t clk_wifibb_40x_en : 1; - uint32_t clk_wifibb_80x_en : 1; - uint32_t clk_wifibb_40x1_en : 1; - uint32_t clk_wifibb_80x1_en : 1; - uint32_t clk_wifibb_160x1_en : 1; - uint32_t clk_wifimac_en : 1; - uint32_t clk_wifi_apb_en : 1; - uint32_t clk_fe_20m_en : 1; - uint32_t clk_fe_40m_en : 1; - uint32_t clk_fe_80m_en : 1; - uint32_t clk_fe_160m_en : 1; - uint32_t clk_fe_apb_en : 1; - uint32_t clk_bt_apb_en : 1; - uint32_t clk_btbb_en : 1; - uint32_t clk_btmac_en : 1; - uint32_t clk_fe_pwdet_adc_en : 1; - uint32_t clk_fe_adc_en : 1; - uint32_t clk_fe_dac_en : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 8; - }; - uint32_t val; - } clk_conf1; - uint32_t wifi_bb_cfg; - uint32_t mem_rf1_conf; - uint32_t mem_rf2_conf; - union { - struct { - uint32_t date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; +/** Group: configure_register */ +typedef union { + struct { + uint32_t clk_en: 1; + uint32_t modem_ant_force_sel_bt: 1; + uint32_t modem_ant_force_sel_wifi: 1; + uint32_t fpga_debug_clkswitch: 1; + uint32_t fpga_debug_clk80: 1; + uint32_t fpga_debug_clk40: 1; + uint32_t fpga_debug_clk20: 1; + uint32_t fpga_debug_clk10: 1; + uint32_t modem_mem_mode_force: 1; + uint32_t modem_dis_wifi6_force: 1; + uint32_t reserved_10: 22; + }; + uint32_t val; +} modem_syscon_test_conf_reg_t; + +typedef union { + struct { + uint32_t pwdet_sar_clock_ena: 1; + uint32_t pwdet_clk_div_num: 8; + uint32_t clk_tx_dac_inv_ena: 1; + uint32_t clk_rx_adc_inv_ena: 1; + uint32_t clk_pwdet_adc_inv_ena: 1; + uint32_t clk_i2c_mst_sel_160m: 1; + uint32_t reserved_13: 8; + uint32_t clk_data_dump_mux: 1; + uint32_t clk_etm_en: 1; + uint32_t clk_zb_apb_en: 1; + uint32_t clk_zbmac_en: 1; + uint32_t clk_modem_sec_ecb_en: 1; + uint32_t clk_modem_sec_ccm_en: 1; + uint32_t clk_modem_sec_bah_en: 1; + uint32_t clk_modem_sec_apb_en: 1; + uint32_t clk_modem_sec_en: 1; + uint32_t clk_ble_timer_en: 1; + uint32_t clk_data_dump_en: 1; + }; + uint32_t val; +} modem_syscon_clk_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifibb_fo: 1; + uint32_t clk_wifimac_fo: 1; + uint32_t clk_wifi_apb_fo: 1; + uint32_t clk_fe_fo: 1; + uint32_t clk_fe_apb_fo: 1; + uint32_t clk_btbb_fo: 1; + uint32_t clk_btmac_fo: 1; + uint32_t clk_bt_apb_fo: 1; + uint32_t clk_zbmac_fo: 1; + uint32_t clk_zbmac_apb_fo: 1; + uint32_t reserved_10: 18; + uint32_t clk_etm_fo: 1; + uint32_t clk_modem_sec_fo: 1; + uint32_t clk_ble_timer_fo: 1; + uint32_t clk_data_dump_fo: 1; + }; + uint32_t val; +} modem_syscon_clk_conf_force_on_reg_t; + +typedef union { + struct { + uint32_t reserved_0: 8; + uint32_t clk_zb_st_map: 4; + uint32_t clk_fe_st_map: 4; + uint32_t clk_bt_st_map: 4; + uint32_t clk_wifi_st_map: 4; + uint32_t clk_modem_peri_st_map: 4; + uint32_t clk_modem_apb_st_map: 4; + }; + uint32_t val; +} modem_syscon_clk_conf_power_st_reg_t; + +typedef union { + struct { + uint32_t reserved_0: 8; + uint32_t rst_wifibb: 1; + uint32_t rst_wifimac: 1; + uint32_t rst_fe_pwdet_adc: 1; + uint32_t rst_fe_dac: 1; + uint32_t rst_fe_adc: 1; + uint32_t rst_fe_ahb: 1; + uint32_t rst_fe: 1; + uint32_t rst_btmac_apb: 1; + uint32_t rst_btmac: 1; + uint32_t rst_btbb_apb: 1; + uint32_t rst_btbb: 1; + uint32_t reserved_19: 3; + uint32_t rst_etm: 1; + uint32_t rst_zbmac_apb: 1; + uint32_t rst_zbmac: 1; + uint32_t rst_modem_ecb: 1; + uint32_t rst_modem_ccm: 1; + uint32_t rst_modem_bah: 1; + uint32_t reserved_28: 1; + uint32_t rst_modem_sec: 1; + uint32_t rst_ble_timer: 1; + uint32_t rst_data_dump: 1; + }; + uint32_t val; +} modem_syscon_modem_rst_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifibb_22m_en: 1; + uint32_t clk_wifibb_40m_en: 1; + uint32_t clk_wifibb_44m_en: 1; + uint32_t clk_wifibb_80m_en: 1; + uint32_t clk_wifibb_40x_en: 1; + uint32_t clk_wifibb_80x_en: 1; + uint32_t clk_wifibb_40x1_en: 1; + uint32_t clk_wifibb_80x1_en: 1; + uint32_t clk_wifibb_160x1_en: 1; + uint32_t clk_wifimac_en: 1; + uint32_t clk_wifi_apb_en: 1; + uint32_t clk_fe_20m_en: 1; + uint32_t clk_fe_40m_en: 1; + uint32_t clk_fe_80m_en: 1; + uint32_t clk_fe_160m_en: 1; + uint32_t clk_fe_apb_en: 1; + uint32_t clk_bt_apb_en: 1; + uint32_t clk_btbb_en: 1; + uint32_t clk_btmac_en: 1; + uint32_t clk_fe_pwdet_adc_en: 1; + uint32_t clk_fe_adc_en: 1; + uint32_t clk_fe_dac_en: 1; + uint32_t reserved_22: 10; + }; + uint32_t val; +} modem_syscon_clk_conf1_reg_t; + +typedef union { + struct { + uint32_t wifi_bb_cfg: 32; + }; + uint32_t val; +} modem_syscon_wifi_bb_cfg_reg_t; + +typedef union { + struct { + uint32_t fe_cfg: 32; + }; + uint32_t val; +} modem_syscon_fe_cfg_reg_t; + +typedef union { + struct { + uint32_t modem_rf1_mem_aux_ctrl: 32; + }; + uint32_t val; +} modem_syscon_mem_rf1_conf_reg_t; + +typedef union { + struct { + uint32_t modem_rf2_mem_aux_ctrl: 32; + }; + uint32_t val; +} modem_syscon_mem_rf2_conf_reg_t; + +typedef union { + struct { + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} modem_syscon_date_reg_t; + +typedef struct { + volatile modem_syscon_test_conf_reg_t test_conf; + volatile modem_syscon_clk_conf_reg_t clk_conf; + volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on; + volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st; + volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf; + volatile modem_syscon_clk_conf1_reg_t clk_conf1; + volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg; + volatile modem_syscon_fe_cfg_reg_t fe_cfg; + volatile modem_syscon_mem_rf1_conf_reg_t mem_rf1_conf; + volatile modem_syscon_mem_rf2_conf_reg_t mem_rf2_conf; + volatile modem_syscon_date_reg_t date; } modem_syscon_dev_t; extern modem_syscon_dev_t MODEM_SYSCON; #ifndef __cplusplus -_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); +_Static_assert(sizeof(modem_syscon_dev_t) == 0x2c, "Invalid size of modem_syscon_dev_t structure"); #endif #ifdef __cplusplus From 8bd81b2bfd02a42a6190efa52a68c9bddcd03416 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 28 May 2025 15:27:20 +0800 Subject: [PATCH 2/7] feat(esp_hw_support): update pmu sleep parameters and register header and structure file for esp32c61 --- .../esp_hw_support/port/esp32c61/pmu_param.c | 97 ++++++++++--------- .../soc/esp32c61/register/soc/pmu_reg.h | 26 +---- .../soc/esp32c61/register/soc/pmu_struct.h | 19 +++- 3 files changed, 69 insertions(+), 73 deletions(-) diff --git a/components/esp_hw_support/port/esp32c61/pmu_param.c b/components/esp_hw_support/port/esp32c61/pmu_param.c index d146f106aa..e565209ac4 100644 --- a/components/esp_hw_support/port/esp32c61/pmu_param.c +++ b/components/esp_hw_support/port/esp32c61/pmu_param.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -202,66 +202,69 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp } #define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \ - .bias = { \ - .xpd_bias = 1, \ - .dbg_atten = 0x0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ + .bias = { \ + .xpd_bias = 1, \ + .dbg_atten = 0x0, \ + .pd_cur = 0, \ + .bias_sleep = 0 \ }, \ - .regulator0 = { \ - .lp_dbias_vol = 0xd, \ - .hp_dbias_vol = 0x1c,\ - .dbias_sel = 1, \ - .dbias_init = 1, \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .xpd = 1, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .dbias = HP_CALI_DBIAS_DEFAULT \ + .regulator0 = { \ + .slp_connect_en_active = 1, \ + .lp_dbias_vol = 0xd, \ + .hp_dbias_vol = 0x1c,\ + .dbias_sel = 1, \ + .dbias_init_active = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = HP_CALI_DBIAS_DEFAULT \ }, \ - .regulator1 = { \ - .drv_b = 0x0 \ + .regulator1 = { \ + .drv_b = 0x0 \ } \ } #define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \ - .bias = { \ - .xpd_bias = 0, \ - .dbg_atten = 0x0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ + .bias = { \ + .xpd_bias = 0, \ + .dbg_atten = 0x0,\ + .pd_cur = 0, \ + .bias_sleep = 0 \ }, \ - .regulator0 = { \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .xpd = 1, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .dbias = HP_CALI_DBIAS_DEFAULT \ + .regulator0 = { \ + .slp_connect_en_modem = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = HP_CALI_DBIAS_DEFAULT \ }, \ - .regulator1 = { \ - .drv_b = 0x0 \ + .regulator1 = { \ + .drv_b = 0x0 \ } \ } #define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \ - .bias = { \ - .xpd_bias = 0, \ - .dbg_atten = 0x0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ + .bias = { \ + .xpd_bias = 0, \ + .dbg_atten = 0x0,\ + .pd_cur = 0, \ + .bias_sleep = 0 \ }, \ - .regulator0 = { \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .xpd = 1, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .dbias = 1 \ + .regulator0 = { \ + .slp_connect_en_sleep = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = 1 \ }, \ - .regulator1 = { \ - .drv_b = 0x0 \ + .regulator1 = { \ + .drv_b = 0x0 \ } \ } diff --git a/components/soc/esp32c61/register/soc/pmu_reg.h b/components/soc/esp32c61/register/soc/pmu_reg.h index ad4b994f78..cf9244c633 100644 --- a/components/soc/esp32c61/register/soc/pmu_reg.h +++ b/components/soc/esp32c61/register/soc/pmu_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1336,18 +1336,6 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 -/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register - * need_des - */ -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) -/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 - /** PMU_HP_SLEEP_LP_DIG_POWER_REG register * need_des */ @@ -1400,18 +1388,6 @@ extern "C" { #define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U #define PMU_HP_SLEEP_PD_OSC_CLK_S 31 -/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register - * need_des - */ -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) -/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 - /** PMU_LP_SLEEP_LP_REGULATOR0_REG register * need_des */ diff --git a/components/soc/esp32c61/register/soc/pmu_struct.h b/components/soc/esp32c61/register/soc/pmu_struct.h index e59470be4e..71d954027a 100644 --- a/components/soc/esp32c61/register/soc/pmu_struct.h +++ b/components/soc/esp32c61/register/soc/pmu_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -156,6 +156,23 @@ typedef union { uint32_t slp_logic_dbias: 4; uint32_t dbias : 5; }; + struct { + uint32_t reserved2 : 3; + uint32_t slp_connect_en_active: 1; + uint32_t reserved3 : 11; + uint32_t dbias_init_active : 1; + uint32_t reserved4 : 16; + }; + struct { + uint32_t reserved5 : 15; + uint32_t slp_connect_en_modem : 1; + uint32_t reserved6 : 16; + }; + struct { + uint32_t reserved7 : 15; + uint32_t slp_connect_en_sleep : 1; + uint32_t reserved8 : 16; + }; uint32_t val; } pmu_hp_regulator0_reg_t; From bc5bef5556a76d065297cf000950d30c90412f0a Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 28 May 2025 22:11:14 +0800 Subject: [PATCH 3/7] feat(esp_hw_support): fix some issues and update esp32c61 eco3 sleep features --- .../lowpower/port/esp32c61/sleep_clock.c | 26 +-- .../lowpower/port/esp32c61/sleep_mmu.c | 152 ------------------ components/esp_hw_support/sleep_modes.c | 8 +- components/esp_system/system_init_fn.txt | 1 - 4 files changed, 15 insertions(+), 172 deletions(-) delete mode 100644 components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c index d0b5f1a730..c123f58cdc 100644 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,24 +18,24 @@ esp_err_t sleep_clock_system_retention_init(void *arg) { const static sleep_retention_entries_config_t pcr_regs_retention[] = { /* Enable i2c master clock */ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, /* Start BBPLL self-calibration */ - [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, /* Wait calibration done */ - [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, + [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, /* Stop BBPLL self-calibration */ - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, /* Clock configuration retention */ - [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), PMU_CLK_STATE0_REG, PMU_STABLE_XPD_BBPLL_STATE, PMU_STABLE_XPD_BBPLL_STATE_M, 1, 0), .owner = ENTRY(0)}, /* Wait PMU_WAIT_XTL_STABLE done */ - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */ - [8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, + [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), PMU_CLK_STATE0_REG, PMU_STABLE_XPD_BBPLL_STATE, PMU_STABLE_XPD_BBPLL_STATE_M, 1, 0), .owner = ENTRY(0) }, /* Wait PMU_WAIT_XTL_STABLE done */ + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(7), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */ + [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, + [9] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(9), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M,0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */ + [10] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M,1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */ #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP - [9] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(9), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) }, + [11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) }, #endif - [10] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M, 0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */ - [11] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(11), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */ }; esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c deleted file mode 100644 index 3a1cad1728..0000000000 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include "esp_attr.h" -#include "esp_check.h" -#include "esp_sleep.h" -#include "esp_log.h" -#include "esp_heap_caps.h" -#include "soc/soc_caps.h" -#include "sdkconfig.h" -#include "soc/spi_mem_reg.h" -#include "esp_private/startup_internal.h" - -static const char *TAG = "sleep_mmu"; - -typedef struct { - uint32_t start; - uint32_t end; -} mmu_domain_dev_regs_region_t; - -typedef struct { - mmu_domain_dev_regs_region_t *region; - int region_num; - uint32_t *regs_frame; -} mmu_domain_dev_sleep_frame_t; - -/** - * Internal structure which holds all requested light sleep mmu retention parameters - */ -typedef struct { - struct { - mmu_domain_dev_sleep_frame_t *mmu_table_frame; - } retent; -} sleep_mmu_retention_t; - -static DRAM_ATTR __attribute__((unused)) sleep_mmu_retention_t s_mmu_retention; - -static void * mmu_domain_dev_sleep_frame_alloc_and_init(const mmu_domain_dev_regs_region_t *regions, const int region_num) -{ - const int region_sz = sizeof(mmu_domain_dev_regs_region_t) * region_num; - int regs_frame_sz = 0; - for (int num = 0; num < region_num; num++) { - regs_frame_sz += regions[num].end - regions[num].start; - } - void *frame = heap_caps_malloc(sizeof(mmu_domain_dev_sleep_frame_t) + region_sz + regs_frame_sz, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL); - if (frame) { - mmu_domain_dev_regs_region_t *region = (mmu_domain_dev_regs_region_t *)(frame + sizeof(mmu_domain_dev_sleep_frame_t)); - memcpy(region, regions, region_num * sizeof(mmu_domain_dev_regs_region_t)); - void *regs_frame = frame + sizeof(mmu_domain_dev_sleep_frame_t) + region_sz; - memset(regs_frame, 0, regs_frame_sz); - *(mmu_domain_dev_sleep_frame_t *)frame = (mmu_domain_dev_sleep_frame_t) { - .region = region, - .region_num = region_num, - .regs_frame = (uint32_t *)regs_frame - }; - } - return frame; -} - -static inline void * mmu_domain_mmu_table_sleep_frame_alloc_and_init(void) -{ - #define MMU_TABLE_SIZE (512 * 4) - const static mmu_domain_dev_regs_region_t regions[] = { - { .start = SPI_MEM_MMU_ITEM_CONTENT_REG(0), .end = SPI_MEM_MMU_ITEM_CONTENT_REG(0) + MMU_TABLE_SIZE} - }; - return mmu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); -} - -static IRAM_ATTR void mmu_domain_dev_regs_save(mmu_domain_dev_sleep_frame_t *frame) -{ - assert(frame); - mmu_domain_dev_regs_region_t *region = frame->region; - uint32_t *regs_frame = frame->regs_frame; - - int offset = 0; - for (int i = 0; i < frame->region_num; i++) { - for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) { - REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset); - regs_frame[offset++] = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); - } - } -} - -static IRAM_ATTR void mmu_domain_dev_regs_restore(mmu_domain_dev_sleep_frame_t *frame) -{ - assert(frame); - mmu_domain_dev_regs_region_t *region = frame->region; - uint32_t *regs_frame = frame->regs_frame; - - int offset = 0; - for (int i = 0; i < frame->region_num; i++) { - for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) { - REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset); - REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0),regs_frame[offset++]); - } - } -} - -IRAM_ATTR void esp_sleep_mmu_retention(bool backup_or_restore) -{ - if (backup_or_restore) { - mmu_domain_dev_regs_save(s_mmu_retention.retent.mmu_table_frame); - } else { - mmu_domain_dev_regs_restore(s_mmu_retention.retent.mmu_table_frame); - } -} - -static esp_err_t esp_sleep_mmu_retention_deinit(void) -{ - if (s_mmu_retention.retent.mmu_table_frame) { - heap_caps_free((void *)s_mmu_retention.retent.mmu_table_frame); - s_mmu_retention.retent.mmu_table_frame = NULL; - } - return ESP_OK; -} - -static esp_err_t esp_sleep_mmu_retention_init(void) -{ - if (s_mmu_retention.retent.mmu_table_frame == NULL) { - void *frame = mmu_domain_mmu_table_sleep_frame_alloc_and_init(); - if (frame == NULL) { - goto err; - } - s_mmu_retention.retent.mmu_table_frame = (mmu_domain_dev_sleep_frame_t *)frame; - } - return ESP_OK; -err: - esp_sleep_mmu_retention_deinit(); - return ESP_ERR_NO_MEM; -} - -bool mmu_domain_pd_allowed(void) -{ - return (s_mmu_retention.retent.mmu_table_frame != NULL); -} - -ESP_SYSTEM_INIT_FN(sleep_mmu_startup_init, SECONDARY, BIT(0), 108) -{ - esp_err_t ret; - ret = esp_sleep_mmu_retention_init(); - if (ret != ESP_OK) { - ESP_EARLY_LOGW(TAG, "Failed to enable TOP power down during light sleep."); - } - return ESP_OK; -} diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 6672e26f42..cb86e90867 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -182,8 +182,8 @@ #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) #elif CONFIG_IDF_TARGET_ESP32C61 -#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) -#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (107) +#define DEFAULT_SLEEP_OUT_OVERHEAD_US (65) +#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (70) #elif CONFIG_IDF_TARGET_ESP32H2 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9) @@ -217,12 +217,8 @@ #endif #if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD -#if CONFIG_IDF_TARGET_ESP32C61 -#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1232) -#elif CONFIG_IDF_TARGET_ESP32C5 #define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1220) #endif -#endif #define RTC_MODULE_SLEEP_PREPARE_CYCLES (6) diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt index 77496a3f5f..0d68cf299d 100644 --- a/components/esp_system/system_init_fn.txt +++ b/components/esp_system/system_init_fn.txt @@ -88,7 +88,6 @@ SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/p SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c on BIT(0) SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0) SECONDARY: 108: sleep_mmu_startup_init in components/esp_hw_support/lowpower/port/esp32c5/sleep_mmu.c on BIT(0) -SECONDARY: 108: sleep_mmu_startup_init in components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c on BIT(0) # app_trace has to be initialized before systemview SECONDARY: 115: esp_apptrace_init in components/app_trace/app_trace.c on ESP_SYSTEM_INIT_ALL_CORES From 8205a4808ba82076c421a28951c6342303e18c74 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Fri, 13 Jun 2025 20:37:24 +0800 Subject: [PATCH 4/7] change(esp_phy): update phy retention context for esp32c61 --- components/esp_phy/esp32c61/phy_init_data.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/components/esp_phy/esp32c61/phy_init_data.c b/components/esp_phy/esp32c61/phy_init_data.c index 503fa18c79..a66aa09856 100644 --- a/components/esp_phy/esp32c61/phy_init_data.c +++ b/components/esp_phy/esp32c61/phy_init_data.c @@ -157,14 +157,15 @@ static const char* TAG = "phy_sleep"; static esp_err_t sleep_retention_wifi_bb_init(void *arg) { - #define N_REGS_WIFI_AGC() (121) - #define N_REGS_WIFI_TX() (14) - #define N_REGS_WIFI_NRX() (136) - #define N_REGS_WIFI_BB() (53) + #define N_REGS_WIFI_AGC() (130) + #define N_REGS_WIFI_TX() (30) + #define N_REGS_WIFI_NRX() (145) + #define N_REGS_WIFI_BB() (82) #define N_REGS_WIFI_BRX() (39) - #define N_REGS_WIFI_FE_COEX() (58) - #define N_REGS_WIFI_FE_DATA() (41) - #define N_REGS_WIFI_FE_CTRL() (87) + #define N_REGS_WIFI_FE_COEX() (21) + #define N_REGS_WIFI_FE_DATA() (34) + #define N_REGS_WIFI_FE_CTRL() (56) + #define N_REGS_WIFI_FE_WIFI() (21) const static sleep_retention_entries_config_t bb_regs_retention[] = { [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(), 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */ @@ -175,6 +176,7 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg) [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */ [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, N_REGS_WIFI_FE_DATA(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */ [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, N_REGS_WIFI_FE_CTRL(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */ + [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b09, 0x600a0c00, 0x600a0c00, N_REGS_WIFI_FE_WIFI(), 0, 0), .owner = BIT(0) | BIT(1) } /* FE WiFi DATA */ }; esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB); ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB"); From f336022a94d6981c14734dfe005fd9c826e91ff5 Mon Sep 17 00:00:00 2001 From: yinqingzhao Date: Tue, 24 Jun 2025 20:32:17 +0800 Subject: [PATCH 5/7] feat(phy): update libphy for esp32c61 support --- components/esp_phy/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_phy/lib b/components/esp_phy/lib index ac1326df80..ada08d173b 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit ac1326df8001dfafbbe7a83178da9803bcf973b6 +Subproject commit ada08d173b90188fc779ad05a75de2bb437b1a06 From c1c78f5838410ace780ec146aca65c39ff13a291 Mon Sep 17 00:00:00 2001 From: yinqingzhao Date: Wed, 18 Jun 2025 16:12:59 +0800 Subject: [PATCH 6/7] feat(wifi): add esp32c61 eco3 wifi support --- components/esp_phy/esp32c61/phy_init_data.c | 24 ++++---- .../esp32c61/ld/esp32c61.rom.net80211.ld | 2 +- .../esp_rom/esp32c61/ld/esp32c61.rom.pp.ld | 60 +++++++++---------- .../esp_private/esp_wifi_he_types_private.h | 22 +++++++ components/esp_wifi/lib | 2 +- .../test_apps/bin_size_apsta/README.md | 4 +- .../esp_wifi/test_apps/wifi_connect/README.md | 4 +- .../test_apps/wifi_function/README.md | 4 +- .../test_apps/wifi_nvs_config/README.md | 4 +- .../esp32c61/include/soc/Kconfig.soc_caps.in | 40 +++++++++++++ .../soc/esp32c61/include/soc/soc_caps.h | 20 +++---- components/wpa_supplicant/test_apps/README.md | 4 +- examples/bluetooth/blufi/README.md | 4 +- .../nimble/bleprph_wifi_coex/README.md | 4 +- .../mesh/internal_communication/README.md | 4 +- examples/mesh/ip_internal_network/README.md | 4 +- examples/mesh/manual_networking/README.md | 4 +- examples/network/eth2ap/README.md | 4 +- examples/network/simple_sniffer/README.md | 4 +- examples/network/sta2eth/README.md | 4 +- examples/openthread/ot_br/README.md | 4 +- examples/openthread/ot_trel/README.md | 4 +- .../i2c/i2c_slave_network_sensor/README.md | 4 +- .../http_server/captive_portal/README.md | 4 +- examples/provisioning/wifi_prov_mgr/README.md | 4 +- examples/wifi/espnow/README.md | 4 +- examples/wifi/fast_scan/README.md | 4 +- .../wifi/getting_started/softAP/README.md | 4 +- .../wifi/getting_started/station/README.md | 4 +- examples/wifi/iperf/README.md | 4 +- examples/wifi/itwt/README.md | 4 +- examples/wifi/power_save/README.md | 4 +- examples/wifi/roaming/roaming_11kvr/README.md | 4 +- examples/wifi/roaming/roaming_app/README.md | 4 +- examples/wifi/scan/README.md | 4 +- examples/wifi/smart_config/README.md | 4 +- examples/wifi/softap_sta/README.md | 4 +- .../wifi/wifi_aware/nan_console/README.md | 4 +- .../wifi/wifi_aware/nan_publisher/README.md | 4 +- .../wifi/wifi_aware/nan_subscriber/README.md | 4 +- examples/wifi/wifi_eap_fast/README.md | 4 +- .../wifi_easy_connect/dpp-enrollee/README.md | 4 +- examples/wifi/wifi_enterprise/README.md | 4 +- examples/wifi/wifi_nvs_config/README.md | 4 +- examples/wifi/wps/README.md | 4 +- examples/wifi/wps_softap_registrar/README.md | 4 +- .../test_apps/peripherals/i2c_wifi/README.md | 4 +- .../phy/phy_multi_init_data_test/README.md | 4 +- tools/test_apps/phy/phy_tsens/README.md | 4 +- 49 files changed, 200 insertions(+), 138 deletions(-) diff --git a/components/esp_phy/esp32c61/phy_init_data.c b/components/esp_phy/esp32c61/phy_init_data.c index a66aa09856..b06b158688 100644 --- a/components/esp_phy/esp32c61/phy_init_data.c +++ b/components/esp_phy/esp32c61/phy_init_data.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,24 +19,24 @@ const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_M const esp_phy_init_data_t phy_init_data= { { 0x1, 0x0, + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x34), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x34), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x44), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x30), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x30), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x28), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x2c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x2c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), 0x0, 0x00, 0x00, diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld index 1ca0e76803..dee1da091d 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld @@ -61,7 +61,7 @@ wifi_get_macaddr = 0x40000b2c; wifi_rf_phy_disable = 0x40000b30; wifi_rf_phy_enable = 0x40000b34; wifi_is_started = 0x40000b38; -sta_input = 0x40000b3c; +/*sta_input = 0x40000b3c;*/ sta_rx_eapol = 0x40000b40; sta_reset_beacon_timeout = 0x40000b44; sta_get_beacon_timeout = 0x40000b48; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld index e071531efe..bcdba8fbc5 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld @@ -23,7 +23,7 @@ esf_buf_recycle = 0x40000b64; GetAccess = 0x40000b68; hal_mac_is_low_rate_enabled = 0x40000b6c; hal_mac_tx_get_blockack = 0x40000b70; -hal_mac_tx_set_ppdu = 0x40000b74; +/*hal_mac_tx_set_ppdu = 0x40000b74;*/ hal_mac_tx_clr_mplen = 0x40000b78; hal_mac_get_txq_state = 0x40000b7c; hal_mac_clr_txq_state = 0x40000b80; @@ -72,7 +72,7 @@ lmacRecycleMPDU = 0x40000c30; lmacRxDone = 0x40000c34; lmacSetTxFrame = 0x40000c38; lmacTxDone = 0x40000c3c; -lmacTxFrame = 0x40000c40; +/*lmacTxFrame = 0x40000c40;*/ lmacDisableTransmit = 0x40000c44; lmacDiscardFrameExchangeSequence = 0x40000c48; lmacProcessCollision = 0x40000c4c; @@ -110,10 +110,10 @@ pm_mac_sleep = 0x40000cc8; pm_enable_active_timer = 0x40000ccc; pm_enable_sleep_delay_timer = 0x40000cd0; pm_local_tsf_process = 0x40000cd4; -pm_set_beacon_filter = 0x40000cd8; -pm_is_in_wifi_slice_threshold = 0x40000cdc; +/*pm_set_beacon_filter = 0x40000cd8;*/ +/*pm_is_in_wifi_slice_threshold = 0x40000cdc;*/ pm_is_waked = 0x40000ce0; -pm_keep_alive = 0x40000ce4; +/*pm_keep_alive = 0x40000ce4;*/ pm_on_beacon_rx = 0x40000ce8; pm_on_data_rx = 0x40000cec; pm_on_data_tx = 0x40000cf0; @@ -125,37 +125,37 @@ pm_on_isr_twt_wake = 0x40000d04; pm_on_tsf_timer = 0x40000d08; pm_on_twt_force_tx = 0x40000d0c; pm_parse_beacon = 0x40000d10; -pm_process_tim = 0x40000d14; +/*pm_process_tim = 0x40000d14;*/ pm_rx_beacon_process = 0x40000d18; pm_rx_data_process = 0x40000d1c; pm_sleep = 0x40000d20; pm_sleep_for = 0x40000d24; -pm_tbtt_process = 0x40000d28; +//pm_tbtt_process = 0x40000d28; pm_tx_data_done_process = 0x40000d2c; pm_allow_tx = 0x40000d30; pm_extend_tbtt_adaptive_servo = 0x40000d34; pm_scale_listen_interval = 0x40000d38; pm_parse_mbssid_element = 0x40000d3c; pm_disconnected_wake = 0x40000d40; -pm_tx_data_process = 0x40000d44; +/*pm_tx_data_process = 0x40000d44;*/ pm_is_twt_awake = 0x40000d48; pm_enable_twt_keep_alive = 0x40000d4c; pm_twt_on_tsf_timer = 0x40000d50; -pm_twt_process = 0x40000d54; +/*pm_twt_process = 0x40000d54;*/ pm_is_twt_start = 0x40000d58; pm_twt_set_target_wdev_time = 0x40000d5c; pm_twt_set_target_tsf = 0x40000d60; pm_enable_twt_keep_alive_timer = 0x40000d64; -pm_mac_try_enable_modem_state = 0x40000d68; +/*pm_mac_try_enable_modem_state = 0x40000d68;*/ pm_beacon_monitor_tbtt_timeout_process = 0x40000d6c; -pm_update_next_tbtt = 0x40000d70; +//pm_update_next_tbtt = 0x40000d70; pm_twt_disallow_tx = 0x40000d74; -pm_clear_wakeup_signal = 0x40000d78; -pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c; -pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80; -pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84; -pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88; -pm_mac_modem_params_rt_update = 0x40000d8c; +//pm_clear_wakeup_signal = 0x40000d78; +/*pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;*/ +/*pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80;*/ +/*pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;*/ +/*pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;*/ +/*pm_mac_modem_params_rt_update = 0x40000d8c;*/ pm_update_at_next_beacon = 0x40000d90; pm_get_null_max_tx_time = 0x40000d94; pm_coex_schm_overall_period_get = 0x40000d98; @@ -175,18 +175,18 @@ ppEmptyDelimiterLength = 0x40000dcc; ppEnqueueRxq = 0x40000dd0; ppEnqueueTxDone = 0x40000dd4; ppGetTxframe = 0x40000dd8; -ppMapTxQueue = 0x40000ddc; +/*ppMapTxQueue = 0x40000ddc;*/ ppProcTxSecFrame = 0x40000de0; ppProcessRxPktHdr = 0x40000de4; -ppProcessTxQ = 0x40000de8; +/*ppProcessTxQ = 0x40000de8;*/ ppRecordBarRRC = 0x40000dec; ppRecycleAmpdu = 0x40000df0; ppRecycleRxPkt = 0x40000df4; ppResortTxAMPDU = 0x40000df8; ppResumeTxAMPDU = 0x40000dfc; ppRxFragmentProc = 0x40000e00; -ppRxPkt = 0x40000e04; -ppRxProtoProc = 0x40000e08; +/*ppRxPkt = 0x40000e04;*/ +/*ppRxProtoProc = 0x40000e08;*/ ppSearchTxQueue = 0x40000e0c; ppSearchTxframe = 0x40000e10; ppSelectNextQueue = 0x40000e14; @@ -205,7 +205,7 @@ ppMapWaitTxq = 0x40000e44; ppProcessWaitingQueue = 0x40000e48; ppDisableQueue = 0x40000e4c; ppCheckTxRTS = 0x40000e50; -ppProcessLifeTime = 0x40000e54; +/*ppProcessLifeTime = 0x40000e54;*/ ppProcTxCallback = 0x40000e58; ppCalPreFecPaddingFactor = 0x40000e5c; ppCalDeliNum = 0x40000e60; @@ -229,7 +229,7 @@ rcampduuprate = 0x40000ea4; rcClearCurAMPDUSched = 0x40000ea8; rcClearCurSched = 0x40000eac; rcClearCurStat = 0x40000eb0; -rcGetSched = 0x40000eb4; +/*rcGetSched = 0x40000eb4;*/ rcLowerSched = 0x40000eb8; rcSetTxAmpduLimit = 0x40000ebc; rcTxUpdatePer = 0x40000ec0; @@ -269,7 +269,7 @@ wdev_mac_special_reg_store = 0x40000f44; wdev_mac_wakeup = 0x40000f48; wdev_mac_sleep = 0x40000f4c; wDev_ProcessFiq = 0x40000f50; -wDev_ProcessRxSucData = 0x40000f54; +/*wDev_ProcessRxSucData = 0x40000f54;*/ wdevProcessRxSucDataAll = 0x40000f58; wdev_csi_len_align = 0x40000f5c; wDev_IndicateBeaconMemoryFrame = 0x40000f60; @@ -447,7 +447,7 @@ s_tbttstart = 0x4084fc88; ***************************************/ /* Functions */ -pm_get_tbtt_count = 0x400014c8; +//pm_get_tbtt_count = 0x400014c8; tsf_hal_get_time = 0x400014cc; tsf_hal_get_counter_value = 0x400014d0; @@ -461,12 +461,12 @@ pm_beacon_offset_is_enabled = 0x40001554; pm_beacon_offset_is_sampling = 0x40001558; pm_beacon_offset_add_total_counter = 0x4000155c; pm_beacon_offset_add_loss_counter = 0x40001560; -pm_beacon_offset_check = 0x40001564; -pm_beacon_offset_get_average = 0x40001568; -pm_beacon_offset_get_expect = 0x4000156c; -pm_beacon_offset_get_params = 0x40001570; +//pm_beacon_offset_check = 0x40001564; +//pm_beacon_offset_get_average = 0x40001568; +//pm_beacon_offset_get_expect = 0x4000156c; +//pm_beacon_offset_get_params = 0x40001570; pm_beacon_monitor_tbtt_stop = 0x40001574; -pm_enable_max_idle_timer = 0x40001578; +/*pm_enable_max_idle_timer = 0x40001578;*/ /* Data (.data, .bss, .rodata) */ s_pm_beacon_offset_ptr = 0x4084fc64; s_pm_beacon_offset_config_ptr = 0x4084fc60; diff --git a/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h b/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h index 8e86bb3bd7..f6b7309e45 100644 --- a/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h +++ b/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h @@ -235,21 +235,43 @@ typedef struct { */ uint32_t mu_bw[3]; uint32_t mu_sigb_dump; +#if CONFIG_IDF_TARGET_ESP32C5 uint32_t vht; uint32_t vht_noeb; uint32_t vht_stbc; uint32_t vht_txbf; uint32_t vht_retry; +#endif uint32_t rx_isr; uint32_t rx_nblks; uint32_t rx_ndpa; uint32_t rx_reset_rxbase_cnt; uint32_t rx_base_null_cnt; +#if CONFIG_IDF_TARGET_ESP32C5 uint32_t vht_mu[64][4]; uint32_t vht_mu_noeb; uint32_t vht_mu_stbc; uint32_t vht_mu_retry[64][4]; uint16_t vht_mu_mcs[64][4][12]; +#endif + +#if CONFIG_IDF_TARGET_ESP32C61 + int8_t min_legacy_rssi; + int8_t max_legacy_rssi; + float avg_legacy_rssi; + + int8_t min_data_rssi; + int8_t max_data_rssi; + float avg_data_rssi; + + int8_t min_mu_legacy_rssi; + int8_t max_mu_legacy_rssi; + float avg_mu_legacy_rssi; + + int8_t min_mu_data_rssi; + int8_t max_mu_data_rssi; + float avg_mu_data_rssi; +#endif } esp_test_rx_statistics_t; //140 bytes #else diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 561f3904ef..38709b89a7 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 561f3904efa6fa3ac9fa6213985c118bcb9ed800 +Subproject commit 38709b89a7de0c8057a5dae03cffe936301f61a0 diff --git a/components/esp_wifi/test_apps/bin_size_apsta/README.md b/components/esp_wifi/test_apps/bin_size_apsta/README.md index 0c839f750c..1c35092948 100644 --- a/components/esp_wifi/test_apps/bin_size_apsta/README.md +++ b/components/esp_wifi/test_apps/bin_size_apsta/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_wifi/test_apps/wifi_connect/README.md b/components/esp_wifi/test_apps/wifi_connect/README.md index 0c839f750c..1c35092948 100644 --- a/components/esp_wifi/test_apps/wifi_connect/README.md +++ b/components/esp_wifi/test_apps/wifi_connect/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_wifi/test_apps/wifi_function/README.md b/components/esp_wifi/test_apps/wifi_function/README.md index 097edbf0c4..aa42f91b6b 100644 --- a/components/esp_wifi/test_apps/wifi_function/README.md +++ b/components/esp_wifi/test_apps/wifi_function/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_wifi/test_apps/wifi_nvs_config/README.md b/components/esp_wifi/test_apps/wifi_nvs_config/README.md index 0c839f750c..1c35092948 100644 --- a/components/esp_wifi/test_apps/wifi_nvs_config/README.md +++ b/components/esp_wifi/test_apps/wifi_nvs_config/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 2eecd3321b..2dd1e92153 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -51,6 +51,10 @@ config SOC_PHY_SUPPORTED bool default y +config SOC_WIFI_SUPPORTED + bool + default y + config SOC_SUPPORTS_SECURE_DL_MODE bool default y @@ -1239,6 +1243,42 @@ config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN bool default y +config SOC_WIFI_HW_TSF + bool + default y + +config SOC_WIFI_FTM_SUPPORT + bool + default n + +config SOC_WIFI_GCMP_SUPPORT + bool + default y + +config SOC_WIFI_WAPI_SUPPORT + bool + default y + +config SOC_WIFI_CSI_SUPPORT + bool + default y + +config SOC_WIFI_MESH_SUPPORT + bool + default y + +config SOC_WIFI_HE_SUPPORT + bool + default y + +config SOC_WIFI_MAC_VERSION_NUM + int + default 3 + +config SOC_WIFI_NAN_SUPPORT + bool + default y + config SOC_BLE_SUPPORTED bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 6d973829bf..c77d066e46 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -30,7 +30,7 @@ #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 #define SOC_PHY_SUPPORTED 1 -// #define SOC_WIFI_SUPPORTED 1 //TODO: IDF-13138, re-open on c61 eco3 +#define SOC_WIFI_SUPPORTED 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_SUPPORTED 1 @@ -510,15 +510,15 @@ /*------------------------------------ WI-FI CAPS ------------------------------------*/ //TODO: IDF-13138, re-open on c61 eco3 -// #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ -// #define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */ -// #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ -// #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ -// #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ -// #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ -// #define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */ -// #define SOC_WIFI_MAC_VERSION_NUM (3) /*!< Wi-Fi MAC version num is 3 */ -// #define SOC_WIFI_NAN_SUPPORT (1) /*!< Support WIFI Aware (NAN) */ +#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ +#define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */ +#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ +#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ +#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ +#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ +#define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */ +#define SOC_WIFI_MAC_VERSION_NUM (3) /*!< Wi-Fi MAC version num is 3 */ +#define SOC_WIFI_NAN_SUPPORT (1) /*!< Support WIFI Aware (NAN) */ // /*---------------------------------- Bluetooth CAPS ----------------------------------*/ #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ diff --git a/components/wpa_supplicant/test_apps/README.md b/components/wpa_supplicant/test_apps/README.md index 57661ca258..e5c31559f2 100644 --- a/components/wpa_supplicant/test_apps/README.md +++ b/components/wpa_supplicant/test_apps/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # wpa_supplicant unit test diff --git a/examples/bluetooth/blufi/README.md b/examples/bluetooth/blufi/README.md index 589638c202..6a07013c72 100644 --- a/examples/bluetooth/blufi/README.md +++ b/examples/bluetooth/blufi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | # ESP-IDF Blufi Example diff --git a/examples/bluetooth/nimble/bleprph_wifi_coex/README.md b/examples/bluetooth/nimble/bleprph_wifi_coex/README.md index dc6e3d215d..1ae1277e48 100644 --- a/examples/bluetooth/nimble/bleprph_wifi_coex/README.md +++ b/examples/bluetooth/nimble/bleprph_wifi_coex/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | # BLE Peripheral with ICMP Echo-Reply diff --git a/examples/mesh/internal_communication/README.md b/examples/mesh/internal_communication/README.md index a86b04351c..c2a5b5f488 100644 --- a/examples/mesh/internal_communication/README.md +++ b/examples/mesh/internal_communication/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | # Mesh Internal Communication Example diff --git a/examples/mesh/ip_internal_network/README.md b/examples/mesh/ip_internal_network/README.md index 2cbf75ed58..394e9622b8 100644 --- a/examples/mesh/ip_internal_network/README.md +++ b/examples/mesh/ip_internal_network/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | # Mesh IP Internal Networking example diff --git a/examples/mesh/manual_networking/README.md b/examples/mesh/manual_networking/README.md index 276ea16130..5fc60d9bf9 100644 --- a/examples/mesh/manual_networking/README.md +++ b/examples/mesh/manual_networking/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | # Mesh Manual Networking Example diff --git a/examples/network/eth2ap/README.md b/examples/network/eth2ap/README.md index 20306fa973..f6437c1728 100644 --- a/examples/network/eth2ap/README.md +++ b/examples/network/eth2ap/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # eth2ap Example (See the README.md file in the upper level 'examples' directory for more information about examples. To try a more complex application about Ethernet to WiFi data forwarding, please go to [iot-solution](https://github.com/espressif/esp-iot-solution/tree/release/v1.0/examples/eth2wifi).) diff --git a/examples/network/simple_sniffer/README.md b/examples/network/simple_sniffer/README.md index 9503435084..2af07bb096 100644 --- a/examples/network/simple_sniffer/README.md +++ b/examples/network/simple_sniffer/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Simple Sniffer Example diff --git a/examples/network/sta2eth/README.md b/examples/network/sta2eth/README.md index ac29de800a..2665071dca 100644 --- a/examples/network/sta2eth/README.md +++ b/examples/network/sta2eth/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # WiFi station to "Wired" interface L2 forwarder diff --git a/examples/openthread/ot_br/README.md b/examples/openthread/ot_br/README.md index 29f4f7b060..718fbd86d4 100644 --- a/examples/openthread/ot_br/README.md +++ b/examples/openthread/ot_br/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # OpenThread Border Router Example diff --git a/examples/openthread/ot_trel/README.md b/examples/openthread/ot_trel/README.md index 2ce050140b..5cc60dfa2f 100644 --- a/examples/openthread/ot_trel/README.md +++ b/examples/openthread/ot_trel/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Thread Radio Encapsulation Link Example diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/README.md b/examples/peripherals/i2c/i2c_slave_network_sensor/README.md index 4f1ad29e2c..91c3ef9314 100644 --- a/examples/peripherals/i2c/i2c_slave_network_sensor/README.md +++ b/examples/peripherals/i2c/i2c_slave_network_sensor/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # I2C slave example diff --git a/examples/protocols/http_server/captive_portal/README.md b/examples/protocols/http_server/captive_portal/README.md index 41f1840b05..7b13b555fb 100644 --- a/examples/protocols/http_server/captive_portal/README.md +++ b/examples/protocols/http_server/captive_portal/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Captive Portal Example diff --git a/examples/provisioning/wifi_prov_mgr/README.md b/examples/provisioning/wifi_prov_mgr/README.md index c6fce08bb5..4987bf6ba0 100644 --- a/examples/provisioning/wifi_prov_mgr/README.md +++ b/examples/provisioning/wifi_prov_mgr/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi Provisioning Manager Example diff --git a/examples/wifi/espnow/README.md b/examples/wifi/espnow/README.md index 198522d838..c9880f6fbe 100644 --- a/examples/wifi/espnow/README.md +++ b/examples/wifi/espnow/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # ESPNOW Example diff --git a/examples/wifi/fast_scan/README.md b/examples/wifi/fast_scan/README.md index 2be7009b42..003351dba6 100644 --- a/examples/wifi/fast_scan/README.md +++ b/examples/wifi/fast_scan/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi Fast Scan Example diff --git a/examples/wifi/getting_started/softAP/README.md b/examples/wifi/getting_started/softAP/README.md index 7a7277cfa5..4c9713eadb 100644 --- a/examples/wifi/getting_started/softAP/README.md +++ b/examples/wifi/getting_started/softAP/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi SoftAP Example diff --git a/examples/wifi/getting_started/station/README.md b/examples/wifi/getting_started/station/README.md index 6a35555d95..07ca4f962a 100644 --- a/examples/wifi/getting_started/station/README.md +++ b/examples/wifi/getting_started/station/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi Station Example diff --git a/examples/wifi/iperf/README.md b/examples/wifi/iperf/README.md index 30998b94d6..cdebd8865e 100644 --- a/examples/wifi/iperf/README.md +++ b/examples/wifi/iperf/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # Iperf Example diff --git a/examples/wifi/itwt/README.md b/examples/wifi/itwt/README.md index 49ba38a5c2..74079c36be 100644 --- a/examples/wifi/itwt/README.md +++ b/examples/wifi/itwt/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | +| ----------------- | -------- | -------- | --------- | # Wifi itwt Example diff --git a/examples/wifi/power_save/README.md b/examples/wifi/power_save/README.md index 50df4b8e6e..473379d265 100644 --- a/examples/wifi/power_save/README.md +++ b/examples/wifi/power_save/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wifi Power Save Example diff --git a/examples/wifi/roaming/roaming_11kvr/README.md b/examples/wifi/roaming/roaming_11kvr/README.md index 5e069f0a10..de083f2f4c 100644 --- a/examples/wifi/roaming/roaming_11kvr/README.md +++ b/examples/wifi/roaming/roaming_11kvr/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Roaming Example diff --git a/examples/wifi/roaming/roaming_app/README.md b/examples/wifi/roaming/roaming_app/README.md index 5484547e09..6a26485be5 100644 --- a/examples/wifi/roaming/roaming_app/README.md +++ b/examples/wifi/roaming/roaming_app/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi Station Example diff --git a/examples/wifi/scan/README.md b/examples/wifi/scan/README.md index 44fe4c7fe7..f69e8a56b6 100644 --- a/examples/wifi/scan/README.md +++ b/examples/wifi/scan/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi Scan Example diff --git a/examples/wifi/smart_config/README.md b/examples/wifi/smart_config/README.md index 822c52226b..191d3d085e 100644 --- a/examples/wifi/smart_config/README.md +++ b/examples/wifi/smart_config/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # smartconfig Example diff --git a/examples/wifi/softap_sta/README.md b/examples/wifi/softap_sta/README.md index 21a5098a2a..1c7e046959 100644 --- a/examples/wifi/softap_sta/README.md +++ b/examples/wifi/softap_sta/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi SoftAP & Station Example diff --git a/examples/wifi/wifi_aware/nan_console/README.md b/examples/wifi/wifi_aware/nan_console/README.md index f203f2effe..2601c22a5c 100644 --- a/examples/wifi/wifi_aware/nan_console/README.md +++ b/examples/wifi/wifi_aware/nan_console/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-S2 | -| ----------------- | ----- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-S2 | +| ----------------- | ----- | -------- | --------- | -------- | # NAN Console Example diff --git a/examples/wifi/wifi_aware/nan_publisher/README.md b/examples/wifi/wifi_aware/nan_publisher/README.md index a5013be5db..a50dd05847 100644 --- a/examples/wifi/wifi_aware/nan_publisher/README.md +++ b/examples/wifi/wifi_aware/nan_publisher/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-S2 | -| ----------------- | ----- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-S2 | +| ----------------- | ----- | -------- | --------- | -------- | # NAN Publisher Example diff --git a/examples/wifi/wifi_aware/nan_subscriber/README.md b/examples/wifi/wifi_aware/nan_subscriber/README.md index 02fe1a1feb..c648c75ab7 100644 --- a/examples/wifi/wifi_aware/nan_subscriber/README.md +++ b/examples/wifi/wifi_aware/nan_subscriber/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-S2 | -| ----------------- | ----- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-S2 | +| ----------------- | ----- | -------- | --------- | -------- | # NAN Subscriber Example diff --git a/examples/wifi/wifi_eap_fast/README.md b/examples/wifi/wifi_eap_fast/README.md index 670c852fcf..ea048f9146 100644 --- a/examples/wifi/wifi_eap_fast/README.md +++ b/examples/wifi/wifi_eap_fast/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # WPA2 Enterprise Example diff --git a/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md b/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md index 5e6740aa28..859ccb2f77 100644 --- a/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md +++ b/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Device Provisioning Protocol (Enrollee) Example diff --git a/examples/wifi/wifi_enterprise/README.md b/examples/wifi/wifi_enterprise/README.md index 06404b82c5..c9b821f295 100644 --- a/examples/wifi/wifi_enterprise/README.md +++ b/examples/wifi/wifi_enterprise/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Understanding different WiFi enterprise modes: diff --git a/examples/wifi/wifi_nvs_config/README.md b/examples/wifi/wifi_nvs_config/README.md index c0043ba5a8..ccab6ce2cd 100644 --- a/examples/wifi/wifi_nvs_config/README.md +++ b/examples/wifi/wifi_nvs_config/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # WiFi NVS Config Example diff --git a/examples/wifi/wps/README.md b/examples/wifi/wps/README.md index 089f1fd0f1..4260e86dfa 100644 --- a/examples/wifi/wps/README.md +++ b/examples/wifi/wps/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi WPS Example diff --git a/examples/wifi/wps_softap_registrar/README.md b/examples/wifi/wps_softap_registrar/README.md index 1af61b74d8..e6dcd9da91 100644 --- a/examples/wifi/wps_softap_registrar/README.md +++ b/examples/wifi/wps_softap_registrar/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wi-Fi WPS Registrar Example diff --git a/tools/test_apps/peripherals/i2c_wifi/README.md b/tools/test_apps/peripherals/i2c_wifi/README.md index e2fe908965..fd5ce5dc51 100644 --- a/tools/test_apps/peripherals/i2c_wifi/README.md +++ b/tools/test_apps/peripherals/i2c_wifi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # I2C-WIFI Test diff --git a/tools/test_apps/phy/phy_multi_init_data_test/README.md b/tools/test_apps/phy/phy_multi_init_data_test/README.md index 0c839f750c..1c35092948 100644 --- a/tools/test_apps/phy/phy_multi_init_data_test/README.md +++ b/tools/test_apps/phy/phy_multi_init_data_test/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/tools/test_apps/phy/phy_tsens/README.md b/tools/test_apps/phy/phy_tsens/README.md index 30a51ab995..c9e6beeb01 100644 --- a/tools/test_apps/phy/phy_tsens/README.md +++ b/tools/test_apps/phy/phy_tsens/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | From 5103944449c90107aaf74391ea963b279ce36608 Mon Sep 17 00:00:00 2001 From: Xu Si Yu Date: Fri, 27 Jun 2025 10:40:37 +0800 Subject: [PATCH 7/7] feat(openthread): disable esp32c61 support for ot_br example --- examples/openthread/.build-test-rules.yml | 2 +- examples/openthread/ot_br/README.md | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml index 559a7957ce..91a0809a18 100644 --- a/examples/openthread/.build-test-rules.yml +++ b/examples/openthread/.build-test-rules.yml @@ -23,7 +23,7 @@ examples/openthread/ot_br: enable: - - if: (SOC_WIFI_SUPPORTED == 1 or IDF_TARGET == "esp32p4") and CONFIG_NAME != "native_radio" + - if: ((SOC_WIFI_SUPPORTED == 1 and IDF_TARGET != "esp32c61") or IDF_TARGET == "esp32p4") and CONFIG_NAME != "native_radio" - if: SOC_WIFI_SUPPORTED == 1 and (SOC_IEEE802154_SUPPORTED == 1 and CONFIG_NAME == "native_radio") disable_test: - if: IDF_TARGET not in ["esp32s3"] diff --git a/examples/openthread/ot_br/README.md b/examples/openthread/ot_br/README.md index 718fbd86d4..29f4f7b060 100644 --- a/examples/openthread/ot_br/README.md +++ b/examples/openthread/ot_br/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # OpenThread Border Router Example