Merge branch 'bugfix/i2c_example_esp32s3' into 'master'

i2c: bringup on ESP32-S3

Closes IDF-3232 and IDF-3292

See merge request espressif/esp-idf!13985

components/driver/test/test_i2c.c

@@ -23,13 +23,14 @@
 #include "driver/periph_ctrl.h"
 #include "esp_rom_gpio.h"
 #include "hal/gpio_hal.h"
+#include "hal/uart_ll.h"
 
 
 #define DATA_LENGTH          512  /*!<Data buffer length for test buffer*/
 #define RW_TEST_LENGTH       129  /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
 #define DELAY_TIME_BETWEEN_ITEMS_MS   1234 /*!< delay time between different test items */
 
-#if CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
 #define I2C_SLAVE_SCL_IO     5     /*!<gpio number for i2c slave clock  */
 #define I2C_SLAVE_SDA_IO     6     /*!<gpio number for i2c slave data */
 #else
@@ -44,6 +45,9 @@
 #if CONFIG_IDF_TARGET_ESP32C3
 #define I2C_MASTER_SCL_IO     5     /*!<gpio number for i2c master clock  */
 #define I2C_MASTER_SDA_IO     6     /*!<gpio number for i2c master data */
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define I2C_MASTER_SCL_IO     2     /*!<gpio number for i2c master clock  */
+#define I2C_MASTER_SDA_IO     1     /*!<gpio number for i2c master data */
 #else
 #define I2C_MASTER_SCL_IO    19     /*!< gpio number for I2C master clock */
 #define I2C_MASTER_SDA_IO    18     /*!< gpio number for I2C master data  */
@@ -662,9 +666,10 @@ static void uart_aut_baud_det_init(int rxd_io_num)
     esp_rom_gpio_connect_out_signal(rxd_io_num, I2CEXT1_SCL_OUT_IDX, 0, 0);
     esp_rom_gpio_connect_in_signal(rxd_io_num, U1RXD_IN_IDX, 0);
     periph_module_enable(PERIPH_UART1_MODULE);
-    UART1.int_ena.val = 0;
+    /* Reset all the bits */
-    UART1.int_clr.val = ~0;
+    uart_ll_disable_intr_mask(&UART1, ~0);
-    UART1.auto_baud.en = 1;
+    uart_ll_clr_intsts_mask(&UART1, ~0);
+    uart_ll_set_autobaud_en(&UART1, true);
 }
 
 //Calculate I2C scl freq
@@ -672,11 +677,11 @@ static void i2c_scl_freq_cal(void)
 {
     const int i2c_source_clk_freq = 80000000;
     const float i2c_cource_clk_period = 0.0125;
-    int edg_cnt = UART1.rxd_cnt.edge_cnt;
+    int edg_cnt = uart_ll_get_rxd_edge_cnt(&UART1);
-    int pospulse_cnt =  UART1.pospulse.min_cnt;
+    int pospulse_cnt = uart_ll_get_pos_pulse_cnt(&UART1);
-    int negpulse_cnt =  UART1.negpulse.min_cnt;
+    int negpulse_cnt = uart_ll_get_neg_pulse_cnt(&UART1);
-    int high_period_cnt =  UART1.highpulse.min_cnt;
+    int high_period_cnt = uart_ll_get_high_pulse_cnt(&UART1);
-    int low_period_cnt =  UART1.lowpulse.min_cnt;
+    int low_period_cnt = uart_ll_get_low_pulse_cnt(&UART1);
     if(edg_cnt != 542) {
         printf("\nedg_cnt != 542, test fail\n");
         return;
@@ -684,7 +689,7 @@ static void i2c_scl_freq_cal(void)
     printf("\nDetected SCL frequency: %d Hz\n", i2c_source_clk_freq / ((pospulse_cnt + negpulse_cnt) / 2) );
 
     printf("\nSCL high period %.3f (us), SCL low_period %.3f (us)\n\n", (float)(i2c_cource_clk_period * high_period_cnt), (float)(i2c_cource_clk_period * low_period_cnt));
-    UART1.auto_baud.en = 0;
+    uart_ll_set_autobaud_en(&UART1, false);
     periph_module_disable(PERIPH_UART1_MODULE);
 }
 
@@ -717,4 +722,4 @@ TEST_CASE("I2C SCL freq test (local test)", "[i2c][ignore]")
     TEST_ESP_OK(i2c_driver_delete(i2c_num));
 }
 
-#endif // TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
+#endif // TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3)

components/hal/esp32/include/hal/uart_ll.h

@@ -895,6 +895,67 @@ FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
     return tout_thrd;
 }
 
+/**
+ * @brief  Configure the auto baudrate.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ * @param  enable Boolean marking whether the auto baudrate should be enabled or not.
+ */
+FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
+{
+    hw->auto_baud.en = enable ? 1 : 0;
+}
+
+/**
+ * @brief  Get the RXD edge count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
+{
+    return hw->rxd_cnt.edge_cnt;
+}
+
+/**
+ * @brief  Get the positive pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->pospulse.min_cnt;
+}
+
+/**
+ * @brief  Get the negative pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->negpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the high pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->highpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the low pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->lowpulse.min_cnt;
+}
+
 /**
  * @brief  Force UART xoff.
  *

components/hal/esp32c3/include/hal/uart_ll.h

@@ -890,6 +890,67 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
     return UART_RX_TOUT_THRHD_V;
 }
 
+/**
+ * @brief  Configure the auto baudrate.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ * @param  enable Boolean marking whether the auto baudrate should be enabled or not.
+ */
+static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
+{
+    hw->conf0.autobaud_en = enable ? 1 : 0;
+}
+
+/**
+ * @brief  Get the RXD edge count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
+{
+    return hw->rxd_cnt.edge_cnt;
+}
+
+/**
+ * @brief  Get the positive pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->pospulse.min_cnt;
+}
+
+/**
+ * @brief  Get the negative pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->negpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the high pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->highpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the low pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->lowpulse.min_cnt;
+}
+
 /**
  * @brief  Force UART xoff.
  *

components/hal/esp32h2/include/hal/uart_ll.h

@@ -890,6 +890,67 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
     return UART_RX_TOUT_THRHD_V;
 }
 
+/**
+ * @brief  Configure the auto baudrate.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ * @param  enable Boolean marking whether the auto baudrate should be enabled or not.
+ */
+static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
+{
+    hw->conf0.autobaud_en = enable ? 1 : 0;
+}
+
+/**
+ * @brief  Get the RXD edge count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
+{
+    return hw->rxd_cnt.edge_cnt;
+}
+
+/**
+ * @brief  Get the positive pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->pospulse.min_cnt;
+}
+
+/**
+ * @brief  Get the negative pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->negpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the high pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->highpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the low pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->lowpulse.min_cnt;
+}
+
 /**
  * @brief  Force UART xoff.
  *

components/hal/esp32s2/include/hal/uart_ll.h

@@ -827,6 +827,67 @@ FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
     return UART_RX_TOUT_THRHD_V;
 }
 
+/**
+ * @brief  Configure the auto baudrate.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ * @param  enable Boolean marking whether the auto baudrate should be enabled or not.
+ */
+FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
+{
+    hw->auto_baud.en = enable ? 1 : 0;
+}
+
+/**
+ * @brief  Get the RXD edge count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
+{
+    return hw->rxd_cnt.edge_cnt;
+}
+
+/**
+ * @brief  Get the positive pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->pospulse.min_cnt;
+}
+
+/**
+ * @brief  Get the negative pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->negpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the high pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->highpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the low pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->lowpulse.min_cnt;
+}
+
 /**
  * @brief  Force UART xoff.
  *

components/hal/esp32s3/include/hal/i2c_ll.h

@@ -58,7 +58,7 @@ typedef enum {
  * @brief Data structure for calculating I2C bus timing.
  */
 typedef struct {
-    uint16_t clkm_div;          /*!< I2C core clock devider */
+    uint16_t clkm_div;          /*!< I2C core clock divider */
     uint16_t scl_low;           /*!< I2C scl low period */
     uint16_t scl_high;          /*!< I2C scl hight period */
     uint16_t scl_wait_high;     /*!< I2C scl wait_high period */
@@ -150,19 +150,19 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
 {
     hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1;
     //scl period
-    hw->scl_low_period.period = bus_cfg->scl_low - 1;
+    hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1;
-    hw->scl_high_period.period = bus_cfg->scl_high;
+    hw->scl_high_period.scl_high_period = bus_cfg->scl_high;
     //sda sample
-    hw->sda_hold.time = bus_cfg->sda_hold;
+    hw->sda_hold.sda_hold_time = bus_cfg->sda_hold;
-    hw->sda_sample.time = bus_cfg->sda_sample;
+    hw->sda_sample.sda_sample_time = bus_cfg->sda_sample;
     //setup
-    hw->scl_rstart_setup.time = bus_cfg->setup;
+    hw->scl_rstart_setup.scl_rstart_setup_time = bus_cfg->setup;
-    hw->scl_stop_setup.time = bus_cfg->setup;
+    hw->scl_stop_setup.scl_stop_setup_time = bus_cfg->setup;
     //hold
-    hw->scl_start_hold.time = bus_cfg->hold - 1;
+    hw->scl_start_hold.scl_start_hold_time = bus_cfg->hold - 1;
-    hw->scl_stop_hold.time = bus_cfg->hold;
+    hw->scl_stop_hold.scl_stop_hold_time = bus_cfg->hold;
-    hw->timeout.tout = bus_cfg->tout;
+    hw->to.time_out_value = bus_cfg->tout;
-    hw->timeout.time_out_en = 1;
+    hw->to.time_out_en = 1;
 }
 
 /**
@@ -203,8 +203,8 @@ static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw)
 static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int high_period, int low_period)
 {
     int high_period_output = high_period - 10; // The rising edge by open-drain output + internal pullup (about 50K) is slow
-    hw->scl_low_period.period = low_period - 1;
+    hw->scl_low_period.scl_low_period = low_period - 1;
-    hw->scl_high_period.period = high_period_output;
+    hw->scl_high_period.scl_high_period = high_period_output;
     hw->scl_high_period.scl_wait_high_period = high_period - high_period_output;
 }
 
@@ -282,7 +282,7 @@ static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
  */
 static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
 {
-    hw->timeout.tout = tout;
+    hw->to.time_out_value = tout;
 }
 
 /**
@@ -296,8 +296,8 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
  */
 static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, bool addr_10bit_en)
 {
-    hw->slave_addr.addr = slave_addr;
+    hw->slave_addr.slave_addr = slave_addr;
-    hw->slave_addr.en_10bit = addr_10bit_en;
+    hw->slave_addr.addr_10bit_en = addr_10bit_en;
 }
 
 /**
@@ -311,7 +311,10 @@ static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, boo
  */
 static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_hw_cmd_t cmd, int cmd_idx)
 {
-    hw->command[cmd_idx].val = cmd.val;
+    _Static_assert(sizeof(i2c_comd0_reg_t) == sizeof(i2c_hw_cmd_t),
+                   "i2c_comdX_reg_t structure size must be equal to i2c_hw_cmd_t structure size");
+    volatile i2c_hw_cmd_t* commands = (volatile i2c_hw_cmd_t*) &hw->comd0;
+    commands[cmd_idx].val = cmd.val;
 }
 
 /**
@@ -325,8 +328,8 @@ static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_hw_cmd_t cmd, int cmd
  */
 static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
 {
-    hw->scl_rstart_setup.time = start_setup;
+    hw->scl_rstart_setup.scl_rstart_setup_time = start_setup;
-    hw->scl_start_hold.time = start_hold - 1;
+    hw->scl_start_hold.scl_start_hold_time = start_hold - 1;
 }
 
 /**
@@ -340,8 +343,8 @@ static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int s
  */
 static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int stop_hold)
 {
-    hw->scl_stop_setup.time = stop_setup;
+    hw->scl_stop_setup.scl_stop_setup_time = stop_setup;
-    hw->scl_stop_hold.time = stop_hold;
+    hw->scl_stop_hold.scl_stop_hold_time = stop_hold;
 }
 
 /**
@@ -355,8 +358,8 @@ static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int sto
  */
 static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_hold)
 {
-    hw->sda_hold.time = sda_hold;
+    hw->sda_hold.sda_hold_time = sda_hold;
-    hw->sda_sample.time = sda_sample;
+    hw->sda_sample.sda_sample_time = sda_sample;
 }
 
 /**
@@ -369,7 +372,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
  */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
-    hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr;
+    hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
 }
 
 /**
@@ -382,7 +385,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
  */
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
-    hw->fifo_conf.rx_fifo_wm_thrhd = full_thr;
+    hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
 }
 
 /**
@@ -426,8 +429,8 @@ static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode
  */
 static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold)
 {
-    *sda_hold = hw->sda_hold.time;
+    *sda_hold = hw->sda_hold.sda_hold_time;
-    *sda_sample = hw->sda_sample.time;
+    *sda_sample = hw->sda_sample.sda_sample_time;
 }
 
 /**
@@ -439,7 +442,7 @@ static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sd
  */
 static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw)
 {
-    return hw->date;
+    return hw->date.val;
 }
 
 /**
@@ -475,7 +478,7 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw)
  */
 static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
 {
-    return hw->sr.rx_fifo_cnt;
+    return hw->sr.rxfifo_cnt;
 }
 
 /**
@@ -487,7 +490,7 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
  */
 static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
 {
-    return SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt;
+    return SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
 }
 
 /**
@@ -499,7 +502,7 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
  */
 static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw)
 {
-    return hw->timeout.tout;
+    return hw->to.time_out_value;
 }
 
 /**
@@ -525,8 +528,8 @@ static inline void i2c_ll_trans_start(i2c_dev_t *hw)
  */
 static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
 {
-    *setup_time = hw->scl_rstart_setup.time;
+    *setup_time = hw->scl_rstart_setup.scl_rstart_setup_time;
-    *hold_time = hw->scl_start_hold.time + 1;
+    *hold_time = hw->scl_start_hold.scl_start_hold_time + 1;
 }
 
 /**
@@ -540,8 +543,8 @@ static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *
  */
 static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
 {
-    *setup_time = hw->scl_stop_setup.time;
+    *setup_time = hw->scl_stop_setup.scl_stop_setup_time;
-    *hold_time = hw->scl_stop_hold.time;
+    *hold_time = hw->scl_stop_hold.scl_stop_hold_time;
 }
 
 /**
@@ -555,8 +558,8 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
  */
 static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period)
 {
-    *high_period = hw->scl_high_period.period + hw->scl_high_period.scl_wait_high_period;
+    *high_period = hw->scl_high_period.scl_high_period + hw->scl_high_period.scl_wait_high_period;
-    *low_period = hw->scl_low_period.period + 1;
+    *low_period = hw->scl_low_period.scl_low_period + 1;
 }
 
 /**
@@ -571,7 +574,7 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i< len; i++) {
-        hw->fifo_data.data = ptr[i];
+        hw->data.fifo_rdata = ptr[i];
     }
 }
 
@@ -587,7 +590,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for(int i = 0; i < len; i++) {
-        ptr[i] = hw->fifo_data.data;
+        ptr[i] = hw->data.fifo_rdata;
     }
 }
 
@@ -603,13 +606,13 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num)
 {
     if (filter_num > 0) {
-        hw->filter_cfg.scl_thres = filter_num;
+        hw->filter_cfg.scl_filter_thres = filter_num;
-        hw->filter_cfg.sda_thres = filter_num;
+        hw->filter_cfg.sda_filter_thres = filter_num;
-        hw->filter_cfg.scl_en = 1;
+        hw->filter_cfg.scl_filter_en = 1;
-        hw->filter_cfg.sda_en = 1;
+        hw->filter_cfg.sda_filter_en = 1;
     } else {
-        hw->filter_cfg.scl_en = 0;
+        hw->filter_cfg.scl_filter_en = 0;
-        hw->filter_cfg.sda_en = 0;
+        hw->filter_cfg.sda_filter_en = 0;
     }
 }
 
@@ -622,7 +625,7 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num)
  */
 static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw)
 {
-    return hw->filter_cfg.scl_thres;
+    return hw->filter_cfg.scl_filter_thres;
 }
 
 /**
@@ -825,15 +828,15 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_sclk_t src_clk)
 static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
 {
     typeof(hw->int_status) int_sts = hw->int_status;
-    if (int_sts.arbitration_lost) {
+    if (int_sts.arbitration_lost_int_st) {
         *event = I2C_INTR_EVENT_ARBIT_LOST;
-    } else if (int_sts.nack) {
+    } else if (int_sts.nack_int_st) {
         *event = I2C_INTR_EVENT_NACK;
-    } else if (int_sts.time_out) {
+    } else if (int_sts.time_out_int_st) {
         *event = I2C_INTR_EVENT_TOUT;
-    } else if (int_sts.end_detect) {
+    } else if (int_sts.end_detect_int_st) {
         *event = I2C_INTR_EVENT_END_DET;
-    } else if (int_sts.trans_complete) {
+    } else if (int_sts.trans_complete_int_st) {
         *event = I2C_INTR_EVENT_TRANS_DONE;
     } else {
         *event = I2C_INTR_EVENT_ERR;
@@ -851,11 +854,11 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
 static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
 {
     typeof(hw->int_status) int_sts = hw->int_status;
-    if (int_sts.tx_fifo_wm) {
+    if (int_sts.txfifo_wm_int_st) {
         *event = I2C_INTR_EVENT_TXFIFO_EMPTY;
-    } else if (int_sts.trans_complete) {
+    } else if (int_sts.trans_complete_int_st) {
         *event = I2C_INTR_EVENT_TRANS_DONE;
-    } else if (int_sts.rx_fifo_wm) {
+    } else if (int_sts.rxfifo_wm_int_st) {
         *event = I2C_INTR_EVENT_RXFIFO_FULL;
     } else {
         *event = I2C_INTR_EVENT_ERR;

components/hal/esp32s3/include/hal/uart_ll.h

@@ -861,6 +861,67 @@ FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
     return UART_RX_TOUT_THRHD_V;
 }
 
+/**
+ * @brief  Configure the auto baudrate.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ * @param  enable Boolean marking whether the auto baudrate should be enabled or not.
+ */
+FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
+{
+    hw->conf0.autobaud_en = enable ? 1 : 0;
+}
+
+/**
+ * @brief  Get the RXD edge count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
+{
+    return hw->rxd_cnt.edge_cnt;
+}
+
+/**
+ * @brief  Get the positive pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->pospulse.min_cnt;
+}
+
+/**
+ * @brief  Get the negative pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->negpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the high pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->highpulse.min_cnt;
+}
+
+/**
+ * @brief  Get the low pulse minimum count.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
+{
+    return hw->lowpulse.min_cnt;
+}
+
 /**
  * @brief  Force UART xoff.
  *

components/soc/esp32s3/include/soc/rtc_i2c_struct.h

@@ -1,232 +1,780 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
-//
+ *
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *  Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+ *  you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
+ *  You may obtain a copy of the License at
-//
+ *
-//     http://www.apache.org/licenses/LICENSE-2.0
+ *      http://www.apache.org/licenses/LICENSE-2.0
-//
+ *
-// Unless required by applicable law or agreed to in writing, software
+ *  Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
+ *  distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
+ *  See the License for the specific language governing permissions and
-// limitations under the License.
+ *  limitations under the License.
-#ifndef _SOC_RTC_I2C_STRUCT_H_
+ */
-#define _SOC_RTC_I2C_STRUCT_H_
+#pragma once
-
 
 #include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct {
+/** Group: Configure Registers */
-    union {
+/** Type of i2c_scl_low register
+ *  configure low scl period
+ */
+typedef union {
     struct {
-            uint32_t period                        :    20;  /*time period that scl = 0*/
+        /** i2c_scl_low_period_reg : R/W; bitpos: [19:0]; default: 256;
-            uint32_t reserved20                    :    12;
+         *  time period that scl =0
+         */
+        uint32_t i2c_scl_low_period_reg:20;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
-    } scl_low;
+} rtc_i2c_scl_low_reg_t;
-    union {
+
+/** Type of i2c_ctrl register
+ *  configure i2c ctrl
+ */
+typedef union {
     struct {
-            uint32_t sda_force_out                 :    1;  /*1=push pull, 0=open drain*/
+        /** i2c_sda_force_out : R/W; bitpos: [0]; default: 0;
-            uint32_t scl_force_out                 :    1;  /*1=push pull, 0=open drain*/
+         *  1=push pull,0=open drain
-            uint32_t ms_mode                       :    1;  /*1=master, 0=slave*/
+         */
-            uint32_t trans_start                   :    1;  /*force start*/
+        uint32_t i2c_sda_force_out:1;
-            uint32_t tx_lsb_first                  :    1;  /*transit lsb first*/
+        /** i2c_scl_force_out : R/W; bitpos: [1]; default: 0;
-            uint32_t rx_lsb_first                  :    1;  /*receive lsb first*/
+         *  1=push pull,0=open drain
-            uint32_t reserved6                     :    23;
+         */
-            uint32_t i2c_ctrl_clk_gate_en          :    1;
+        uint32_t i2c_scl_force_out:1;
-            uint32_t i2c_reset                     :    1;  /*rtc i2c sw reset*/
+        /** i2c_ms_mode : R/W; bitpos: [2]; default: 0;
-            uint32_t i2cclk_en                     :    1;  /*rtc i2c reg clk gating*/
+         *  1=master,0=slave
+         */
+        uint32_t i2c_ms_mode:1;
+        /** i2c_trans_start : R/W; bitpos: [3]; default: 0;
+         *  force start
+         */
+        uint32_t i2c_trans_start:1;
+        /** i2c_tx_lsb_first : R/W; bitpos: [4]; default: 0;
+         *  transit lsb first
+         */
+        uint32_t i2c_tx_lsb_first:1;
+        /** i2c_rx_lsb_first : R/W; bitpos: [5]; default: 0;
+         *  receive lsb first
+         */
+        uint32_t i2c_rx_lsb_first:1;
+        uint32_t reserved_6:23;
+        /** i2c_i2c_ctrl_clk_gate_en : R/W; bitpos: [29]; default: 0;
+         *  configure i2c ctrl clk enable
+         */
+        uint32_t i2c_i2c_ctrl_clk_gate_en:1;
+        /** i2c_i2c_reset : R/W; bitpos: [30]; default: 0;
+         *  rtc i2c sw reset
+         */
+        uint32_t i2c_i2c_reset:1;
+        /** i2c_i2cclk_en : R/W; bitpos: [31]; default: 0;
+         *  rtc i2c reg clk gating
+         */
+        uint32_t i2c_i2cclk_en:1;
     };
     uint32_t val;
-    } ctrl;
+} rtc_i2c_ctrl_reg_t;
-    union {
+
+/** Type of i2c_to register
+ *  configure time out
+ */
+typedef union {
     struct {
-            uint32_t ack_rec                       :    1;  /*ack response*/
+        /** i2c_time_out_reg : R/W; bitpos: [19:0]; default: 65536;
-            uint32_t slave_rw                      :    1;  /*slave read or write*/
+         *  time out threshold
-            uint32_t arb_lost                      :    1;  /*arbitration is lost*/
+         */
-            uint32_t bus_busy                      :    1;  /*bus is busy*/
+        uint32_t i2c_time_out_reg:20;
-            uint32_t slave_addressed               :    1;  /*slave reg sub address*/
+        uint32_t reserved_20:12;
-            uint32_t byte_trans                    :    1;  /*One byte transit done*/
-            uint32_t op_cnt                        :    2;  /*which operation is working*/
-            uint32_t reserved8                     :    8;
-            uint32_t shift                         :    8;  /*shifter content*/
-            uint32_t scl_main_state_last           :    3;  /*i2c last main status*/
-            uint32_t reserved27                    :    1;
-            uint32_t scl_state_last                :    3;  /*scl last status*/
-            uint32_t reserved31                    :    1;
     };
     uint32_t val;
-    } status;
+} rtc_i2c_to_reg_t;
-    union {
+
+/** Type of i2c_slave_addr register
+ *  configure slave id
+ */
+typedef union {
     struct {
-            uint32_t time_out                      :    20;  /*time out threshold*/
+        /** i2c_slave_addr : R/W; bitpos: [14:0]; default: 0;
-            uint32_t reserved20                    :    12;
+         *  slave address
+         */
+        uint32_t i2c_slave_addr:15;
+        uint32_t reserved_15:16;
+        /** i2c_addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  i2c 10bit mode enable
+         */
+        uint32_t i2c_addr_10bit_en:1;
     };
     uint32_t val;
-    } timeout;
+} rtc_i2c_slave_addr_reg_t;
-    union {
+
+/** Type of i2c_scl_high register
+ *  configure high scl period
+ */
+typedef union {
     struct {
-            uint32_t addr                          :    15;  /*slave address*/
+        /** i2c_scl_high_period_reg : R/W; bitpos: [19:0]; default: 256;
-            uint32_t reserved15                    :    16;
+         *  time period that scl = 1
-            uint32_t en_10bit                      :    1;  /*i2c 10bit mode enable*/
+         */
+        uint32_t i2c_scl_high_period_reg:20;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
-    } slave_addr;
+} rtc_i2c_scl_high_reg_t;
-    union {
+
+/** Type of i2c_sda_duty register
+ *  configure sda duty
+ */
+typedef union {
     struct {
-            uint32_t period                        :    20;  /*time period that scl = 1*/
+        /** i2c_sda_duty_num : R/W; bitpos: [19:0]; default: 16;
-            uint32_t reserved20                    :    12;
+         *  time period for SDA to toggle after SCL goes low
+         */
+        uint32_t i2c_sda_duty_num:20;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
-    } scl_high;
+} rtc_i2c_sda_duty_reg_t;
-    union {
+
+/** Type of i2c_scl_start_period register
+ *  configure scl start period
+ */
+typedef union {
     struct {
-            uint32_t sda_duty_num                  :    20;  /*time period for SDA to toggle after SCL goes low*/
+        /** i2c_scl_start_period : R/W; bitpos: [19:0]; default: 8;
-            uint32_t reserved20                    :    12;
+         *  time period for SCL to toggle after I2C start is triggered
+         */
+        uint32_t i2c_scl_start_period:20;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
-    } sda_duty;
+} rtc_i2c_scl_start_period_reg_t;
-    union {
+
+/** Type of i2c_scl_stop_period register
+ *  configure scl stop period
+ */
+typedef union {
     struct {
-            uint32_t scl_start_period              :    20;  /*time period for SCL to toggle after I2C start is triggered*/
+        /** i2c_scl_stop_period : R/W; bitpos: [19:0]; default: 8;
-            uint32_t reserved20                    :    12;
+         *  time period for SCL to stop after I2C end is triggered
+         */
+        uint32_t i2c_scl_stop_period:20;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
-    } scl_start_period;
+} rtc_i2c_scl_stop_period_reg_t;
-    union {
+
+/** Type of i2c_data register
+ *  get i2c data status
+ */
+typedef union {
     struct {
-            uint32_t scl_stop_period               :    20;  /*time period for SCL to stop after I2C end is triggered*/
+        /** i2c_i2c_rdata : RO; bitpos: [7:0]; default: 0;
-            uint32_t reserved20                    :    12;
+         *  data received
+         */
+        uint32_t i2c_i2c_rdata:8;
+        /** i2c_slave_tx_data : R/W; bitpos: [15:8]; default: 0;
+         *  data sent by slave
+         */
+        uint32_t i2c_slave_tx_data:8;
+        uint32_t reserved_16:15;
+        /** i2c_i2c_done : RO; bitpos: [31]; default: 0;
+         *  i2c done
+         */
+        uint32_t i2c_i2c_done:1;
     };
     uint32_t val;
-    } scl_stop_period;
+} rtc_i2c_data_reg_t;
-    union {
+
+/** Type of i2c_cmd0 register
+ *  i2c commond0 register
+ */
+typedef union {
     struct {
-            uint32_t slave_tran_comp               :    1;  /*clear slave transit complete interrupt*/
+        /** i2c_command0 : R/W; bitpos: [13:0]; default: 2307;
-            uint32_t arbitration_lost              :    1;  /*clear arbitration lost interrupt*/
+         *  command0
-            uint32_t master_tran_comp              :    1;  /*clear master transit complete interrupt*/
+         */
-            uint32_t trans_complete                :    1;  /*clear transit complete interrupt*/
+        uint32_t i2c_command0:14;
-            uint32_t time_out                      :    1;  /*clear time out interrupt*/
+        uint32_t reserved_14:17;
-            uint32_t ack_err                       :    1;  /*clear ack error interrupt*/
+        /** i2c_command0_done : RO; bitpos: [31]; default: 0;
-            uint32_t rx_data                       :    1;  /*clear receive data interrupt*/
+         *  command0_done
-            uint32_t tx_data                       :    1;  /*clear transit load data complete interrupt*/
+         */
-            uint32_t detect_start                  :    1;  /*clear detect start interrupt*/
+        uint32_t i2c_command0_done:1;
-            uint32_t reserved9                     :    23;
     };
     uint32_t val;
-    } int_clr;
+} rtc_i2c_cmd0_reg_t;
-    union {
+
+/** Type of i2c_cmd1 register
+ *  i2c commond1 register
+ */
+typedef union {
     struct {
-            uint32_t slave_tran_comp               :    1;  /*slave transit complete interrupt raw*/
+        /** i2c_command1 : R/W; bitpos: [13:0]; default: 6401;
-            uint32_t arbitration_lost              :    1;  /*arbitration lost interrupt raw*/
+         *  command1
-            uint32_t master_tran_comp              :    1;  /*master transit complete interrupt raw*/
+         */
-            uint32_t trans_complete                :    1;  /*transit complete interrupt raw*/
+        uint32_t i2c_command1:14;
-            uint32_t time_out                      :    1;  /*time out interrupt raw*/
+        uint32_t reserved_14:17;
-            uint32_t ack_err                       :    1;  /*ack error interrupt raw*/
+        /** i2c_command1_done : RO; bitpos: [31]; default: 0;
-            uint32_t rx_data                       :    1;  /*receive data interrupt raw*/
+         *  command1_done
-            uint32_t tx_data                       :    1;  /*transit data interrupt raw*/
+         */
-            uint32_t detect_start                  :    1;  /*detect start interrupt raw*/
+        uint32_t i2c_command1_done:1;
-            uint32_t reserved9                     :    23;
     };
     uint32_t val;
-    } int_raw;
+} rtc_i2c_cmd1_reg_t;
-    union {
+
+/** Type of i2c_cmd2 register
+ *  i2c commond2 register
+ */
+typedef union {
     struct {
-            uint32_t slave_tran_comp               :    1;  /*slave transit complete interrupt state*/
+        /** i2c_command2 : R/W; bitpos: [13:0]; default: 2306;
-            uint32_t arbitration_lost              :    1;  /*arbitration lost interrupt state*/
+         *  command2
-            uint32_t master_tran_comp              :    1;  /*master transit complete interrupt state*/
+         */
-            uint32_t trans_complete                :    1;  /*transit complete interrupt state*/
+        uint32_t i2c_command2:14;
-            uint32_t time_out                      :    1;  /*time out interrupt state*/
+        uint32_t reserved_14:17;
-            uint32_t ack_err                       :    1;  /*ack error interrupt state*/
+        /** i2c_command2_done : RO; bitpos: [31]; default: 0;
-            uint32_t rx_data                       :    1;  /*receive data interrupt state*/
+         *  command2_done
-            uint32_t tx_data                       :    1;  /*transit data interrupt state*/
+         */
-            uint32_t detect_start                  :    1;  /*detect start interrupt state*/
+        uint32_t i2c_command2_done:1;
-            uint32_t reserved9                     :    23;
     };
     uint32_t val;
-    } int_st;
+} rtc_i2c_cmd2_reg_t;
-    union {
+
+/** Type of i2c_cmd3 register
+ *  i2c commond3 register
+ */
+typedef union {
     struct {
-            uint32_t slave_tran_comp               :    1;  /*enable slave transit complete interrupt*/
+        /** i2c_command3 : R/W; bitpos: [13:0]; default: 257;
-            uint32_t arbitration_lost              :    1;  /*enable arbitration lost interrupt*/
+         *  command3
-            uint32_t master_tran_comp              :    1;  /*enable master transit complete interrupt*/
+         */
-            uint32_t trans_complete                :    1;  /*enable transit complete interrupt*/
+        uint32_t i2c_command3:14;
-            uint32_t time_out                      :    1;  /*enable time out interrupt*/
+        uint32_t reserved_14:17;
-            uint32_t ack_err                       :    1;  /*enable eack error interrupt*/
+        /** i2c_command3_done : RO; bitpos: [31]; default: 0;
-            uint32_t rx_data                       :    1;  /*enable receive data interrupt*/
+         *  command3_done
-            uint32_t tx_data                       :    1;  /*enable transit data interrupt*/
+         */
-            uint32_t detect_start                  :    1;  /*enable detect start interrupt*/
+        uint32_t i2c_command3_done:1;
-            uint32_t reserved9                     :    23;
     };
     uint32_t val;
-    } int_ena;
+} rtc_i2c_cmd3_reg_t;
-    union {
+
+/** Type of i2c_cmd4 register
+ *  i2c commond4 register
+ */
+typedef union {
     struct {
-            uint32_t i2c_rdata                     :    8;  /*data received*/
+        /** i2c_command4 : R/W; bitpos: [13:0]; default: 2305;
-            uint32_t slave_tx_data                 :    8;  /*data sent by slave*/
+         *  command4
-            uint32_t reserved16                    :    15;
+         */
-            uint32_t i2c_done                      :    1;  /*i2c done*/
+        uint32_t i2c_command4:14;
+        uint32_t reserved_14:17;
+        /** i2c_command4_done : RO; bitpos: [31]; default: 0;
+         *  command4_done
+         */
+        uint32_t i2c_command4_done:1;
     };
     uint32_t val;
-    } fifo_data;
+} rtc_i2c_cmd4_reg_t;
-    union {
+
+/** Type of i2c_cmd5 register
+ *  i2c commond5_register
+ */
+typedef union {
     struct {
-            uint32_t command0                      :    14;  /* command0*/
+        /** i2c_command5 : R/W; bitpos: [13:0]; default: 5889;
-            uint32_t reserved14                    :    17;
+         *  command5
-            uint32_t done                          :    1;  /* command0_done*/
+         */
+        uint32_t i2c_command5:14;
+        uint32_t reserved_14:17;
+        /** i2c_command5_done : RO; bitpos: [31]; default: 0;
+         *  command5_done
+         */
+        uint32_t i2c_command5_done:1;
     };
     uint32_t val;
-    } command[16];
+} rtc_i2c_cmd5_reg_t;
-    uint32_t reserved_78;
+
-    uint32_t reserved_7c;
+/** Type of i2c_cmd6 register
-    uint32_t reserved_80;
+ *  i2c commond6 register
-    uint32_t reserved_84;
+ */
-    uint32_t reserved_88;
+typedef union {
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    union {
     struct {
-            uint32_t i2c_date                      :    28;
+        /** i2c_command6 : R/W; bitpos: [13:0]; default: 6401;
-            uint32_t reserved28                    :    4;
+         *  command6
+         */
+        uint32_t i2c_command6:14;
+        uint32_t reserved_14:17;
+        /** i2c_command6_done : RO; bitpos: [31]; default: 0;
+         *  command6_done
+         */
+        uint32_t i2c_command6_done:1;
     };
     uint32_t val;
-    } date;
+} rtc_i2c_cmd6_reg_t;
-} rtc_i2c_dev_t;
+
-extern rtc_i2c_dev_t RTC_I2C;
+/** Type of i2c_cmd7 register
+ *  i2c commond7 register
+ */
+typedef union {
+    struct {
+        /** i2c_command7 : R/W; bitpos: [13:0]; default: 2308;
+         *  command7
+         */
+        uint32_t i2c_command7:14;
+        uint32_t reserved_14:17;
+        /** i2c_command7_done : RO; bitpos: [31]; default: 0;
+         *  command7_done
+         */
+        uint32_t i2c_command7_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd7_reg_t;
+
+/** Type of i2c_cmd8 register
+ *  i2c commond8 register
+ */
+typedef union {
+    struct {
+        /** i2c_command8 : R/W; bitpos: [13:0]; default: 6401;
+         *  command8
+         */
+        uint32_t i2c_command8:14;
+        uint32_t reserved_14:17;
+        /** i2c_command8_done : RO; bitpos: [31]; default: 0;
+         *  command8_done
+         */
+        uint32_t i2c_command8_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd8_reg_t;
+
+/** Type of i2c_cmd9 register
+ *  i2c commond9 register
+ */
+typedef union {
+    struct {
+        /** i2c_command9 : R/W; bitpos: [13:0]; default: 2307;
+         *  command9
+         */
+        uint32_t i2c_command9:14;
+        uint32_t reserved_14:17;
+        /** i2c_command9_done : RO; bitpos: [31]; default: 0;
+         *  command9_done
+         */
+        uint32_t i2c_command9_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd9_reg_t;
+
+/** Type of i2c_cmd10 register
+ *  i2c commond10 register
+ */
+typedef union {
+    struct {
+        /** i2c_command10 : R/W; bitpos: [13:0]; default: 257;
+         *  command10
+         */
+        uint32_t i2c_command10:14;
+        uint32_t reserved_14:17;
+        /** i2c_command10_done : RO; bitpos: [31]; default: 0;
+         *  command10_done
+         */
+        uint32_t i2c_command10_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd10_reg_t;
+
+/** Type of i2c_cmd11 register
+ *  i2c commond11 register
+ */
+typedef union {
+    struct {
+        /** i2c_command11 : R/W; bitpos: [13:0]; default: 2305;
+         *  command11
+         */
+        uint32_t i2c_command11:14;
+        uint32_t reserved_14:17;
+        /** i2c_command11_done : RO; bitpos: [31]; default: 0;
+         *  command11_done
+         */
+        uint32_t i2c_command11_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd11_reg_t;
+
+/** Type of i2c_cmd12 register
+ *  i2c commond12 register
+ */
+typedef union {
+    struct {
+        /** i2c_command12 : R/W; bitpos: [13:0]; default: 5889;
+         *  command12
+         */
+        uint32_t i2c_command12:14;
+        uint32_t reserved_14:17;
+        /** i2c_command12_done : RO; bitpos: [31]; default: 0;
+         *  command12_done
+         */
+        uint32_t i2c_command12_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd12_reg_t;
+
+/** Type of i2c_cmd13 register
+ *  i2c commond13 register
+ */
+typedef union {
+    struct {
+        /** i2c_command13 : R/W; bitpos: [13:0]; default: 6401;
+         *  command13
+         */
+        uint32_t i2c_command13:14;
+        uint32_t reserved_14:17;
+        /** i2c_command13_done : RO; bitpos: [31]; default: 0;
+         *  command13_done
+         */
+        uint32_t i2c_command13_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd13_reg_t;
+
+/** Type of i2c_cmd14 register
+ *  i2c commond14 register
+ */
+typedef union {
+    struct {
+        /** i2c_command14 : R/W; bitpos: [13:0]; default: 0;
+         *  command14
+         */
+        uint32_t i2c_command14:14;
+        uint32_t reserved_14:17;
+        /** i2c_command14_done : RO; bitpos: [31]; default: 0;
+         *  command14_done
+         */
+        uint32_t i2c_command14_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd14_reg_t;
+
+/** Type of i2c_cmd15 register
+ *  i2c commond15 register
+ */
+typedef union {
+    struct {
+        /** i2c_command15 : R/W; bitpos: [13:0]; default: 0;
+         *  command15
+         */
+        uint32_t i2c_command15:14;
+        uint32_t reserved_14:17;
+        /** i2c_command15_done : RO; bitpos: [31]; default: 0;
+         *  command15_done
+         */
+        uint32_t i2c_command15_done:1;
+    };
+    uint32_t val;
+} rtc_i2c_cmd15_reg_t;
+
+
+/** Group: status register */
+/** Type of i2c_status register
+ *  get i2c status
+ */
+typedef union {
+    struct {
+        /** i2c_ack_rec : RO; bitpos: [0]; default: 0;
+         *  ack response
+         */
+        uint32_t i2c_ack_rec:1;
+        /** i2c_slave_rw : RO; bitpos: [1]; default: 0;
+         *  slave read or write
+         */
+        uint32_t i2c_slave_rw:1;
+        /** i2c_arb_lost : RO; bitpos: [2]; default: 0;
+         *  arbitration is lost
+         */
+        uint32_t i2c_arb_lost:1;
+        /** i2c_bus_busy : RO; bitpos: [3]; default: 0;
+         *  bus is busy
+         */
+        uint32_t i2c_bus_busy:1;
+        /** i2c_slave_addressed : RO; bitpos: [4]; default: 0;
+         *  slave reg sub address
+         */
+        uint32_t i2c_slave_addressed:1;
+        /** i2c_byte_trans : RO; bitpos: [5]; default: 0;
+         *  One byte transit done
+         */
+        uint32_t i2c_byte_trans:1;
+        /** i2c_op_cnt : RO; bitpos: [7:6]; default: 0;
+         *  which operation is working
+         */
+        uint32_t i2c_op_cnt:2;
+        uint32_t reserved_8:8;
+        /** i2c_shift_reg : RO; bitpos: [23:16]; default: 0;
+         *  shifter content
+         */
+        uint32_t i2c_shift_reg:8;
+        /** i2c_scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  i2c last main status
+         */
+        uint32_t i2c_scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** i2c_scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  scl last status
+         */
+        uint32_t i2c_scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} rtc_i2c_status_reg_t;
+
+
+/** Group: interrupt Register */
+/** Type of i2c_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** i2c_slave_tran_comp_int_clr : WO; bitpos: [0]; default: 0;
+         *  clear slave transit complete interrupt
+         */
+        uint32_t i2c_slave_tran_comp_int_clr:1;
+        /** i2c_arbitration_lost_int_clr : WO; bitpos: [1]; default: 0;
+         *  clear arbitration lost interrupt
+         */
+        uint32_t i2c_arbitration_lost_int_clr:1;
+        /** i2c_master_tran_comp_int_clr : WO; bitpos: [2]; default: 0;
+         *  clear master transit complete interrupt
+         */
+        uint32_t i2c_master_tran_comp_int_clr:1;
+        /** i2c_trans_complete_int_clr : WO; bitpos: [3]; default: 0;
+         *  clear transit complete interrupt
+         */
+        uint32_t i2c_trans_complete_int_clr:1;
+        /** i2c_time_out_int_clr : WO; bitpos: [4]; default: 0;
+         *  clear time out interrupt
+         */
+        uint32_t i2c_time_out_int_clr:1;
+        /** i2c_ack_err_int_clr : WO; bitpos: [5]; default: 0;
+         *  clear ack error interrupt
+         */
+        uint32_t i2c_ack_err_int_clr:1;
+        /** i2c_rx_data_int_clr : WO; bitpos: [6]; default: 0;
+         *  clear receive data interrupt
+         */
+        uint32_t i2c_rx_data_int_clr:1;
+        /** i2c_tx_data_int_clr : WO; bitpos: [7]; default: 0;
+         *  clear transit load data complete interrupt
+         */
+        uint32_t i2c_tx_data_int_clr:1;
+        /** i2c_detect_start_int_clr : WO; bitpos: [8]; default: 0;
+         *  clear detect start interrupt
+         */
+        uint32_t i2c_detect_start_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} rtc_i2c_int_clr_reg_t;
+
+/** Type of i2c_int_raw register
+ *  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** i2c_slave_tran_comp_int_raw : RO; bitpos: [0]; default: 0;
+         *  slave transit complete interrupt raw
+         */
+        uint32_t i2c_slave_tran_comp_int_raw:1;
+        /** i2c_arbitration_lost_int_raw : RO; bitpos: [1]; default: 0;
+         *  arbitration lost interrupt raw
+         */
+        uint32_t i2c_arbitration_lost_int_raw:1;
+        /** i2c_master_tran_comp_int_raw : RO; bitpos: [2]; default: 0;
+         *  master transit complete interrupt raw
+         */
+        uint32_t i2c_master_tran_comp_int_raw:1;
+        /** i2c_trans_complete_int_raw : RO; bitpos: [3]; default: 0;
+         *  transit complete interrupt raw
+         */
+        uint32_t i2c_trans_complete_int_raw:1;
+        /** i2c_time_out_int_raw : RO; bitpos: [4]; default: 0;
+         *  time out interrupt raw
+         */
+        uint32_t i2c_time_out_int_raw:1;
+        /** i2c_ack_err_int_raw : RO; bitpos: [5]; default: 0;
+         *  ack error interrupt raw
+         */
+        uint32_t i2c_ack_err_int_raw:1;
+        /** i2c_rx_data_int_raw : RO; bitpos: [6]; default: 0;
+         *  receive data interrupt raw
+         */
+        uint32_t i2c_rx_data_int_raw:1;
+        /** i2c_tx_data_int_raw : RO; bitpos: [7]; default: 0;
+         *  transit data interrupt raw
+         */
+        uint32_t i2c_tx_data_int_raw:1;
+        /** i2c_detect_start_int_raw : RO; bitpos: [8]; default: 0;
+         *  detect start interrupt raw
+         */
+        uint32_t i2c_detect_start_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} rtc_i2c_int_raw_reg_t;
+
+/** Type of i2c_int_st register
+ *  interrupt state register
+ */
+typedef union {
+    struct {
+        /** i2c_slave_tran_comp_int_st : RO; bitpos: [0]; default: 0;
+         *  slave transit complete interrupt state
+         */
+        uint32_t i2c_slave_tran_comp_int_st:1;
+        /** i2c_arbitration_lost_int_st : RO; bitpos: [1]; default: 0;
+         *  arbitration lost interrupt state
+         */
+        uint32_t i2c_arbitration_lost_int_st:1;
+        /** i2c_master_tran_comp_int_st : RO; bitpos: [2]; default: 0;
+         *  master transit complete interrupt state
+         */
+        uint32_t i2c_master_tran_comp_int_st:1;
+        /** i2c_trans_complete_int_st : RO; bitpos: [3]; default: 0;
+         *  transit complete interrupt state
+         */
+        uint32_t i2c_trans_complete_int_st:1;
+        /** i2c_time_out_int_st : RO; bitpos: [4]; default: 0;
+         *  time out interrupt state
+         */
+        uint32_t i2c_time_out_int_st:1;
+        /** i2c_ack_err_int_st : RO; bitpos: [5]; default: 0;
+         *  ack error interrupt state
+         */
+        uint32_t i2c_ack_err_int_st:1;
+        /** i2c_rx_data_int_st : RO; bitpos: [6]; default: 0;
+         *  receive data interrupt state
+         */
+        uint32_t i2c_rx_data_int_st:1;
+        /** i2c_tx_data_int_st : RO; bitpos: [7]; default: 0;
+         *  transit data interrupt state
+         */
+        uint32_t i2c_tx_data_int_st:1;
+        /** i2c_detect_start_int_st : RO; bitpos: [8]; default: 0;
+         *  detect start interrupt state
+         */
+        uint32_t i2c_detect_start_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} rtc_i2c_int_st_reg_t;
+
+/** Type of i2c_int_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** i2c_slave_tran_comp_int_ena : R/W; bitpos: [0]; default: 0;
+         *  enable slave transit complete interrupt
+         */
+        uint32_t i2c_slave_tran_comp_int_ena:1;
+        /** i2c_arbitration_lost_int_ena : R/W; bitpos: [1]; default: 0;
+         *  enable arbitration lost interrupt
+         */
+        uint32_t i2c_arbitration_lost_int_ena:1;
+        /** i2c_master_tran_comp_int_ena : R/W; bitpos: [2]; default: 0;
+         *  enable master transit complete interrupt
+         */
+        uint32_t i2c_master_tran_comp_int_ena:1;
+        /** i2c_trans_complete_int_ena : R/W; bitpos: [3]; default: 0;
+         *  enable transit complete interrupt
+         */
+        uint32_t i2c_trans_complete_int_ena:1;
+        /** i2c_time_out_int_ena : R/W; bitpos: [4]; default: 0;
+         *  enable time out interrupt
+         */
+        uint32_t i2c_time_out_int_ena:1;
+        /** i2c_ack_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  enable eack error interrupt
+         */
+        uint32_t i2c_ack_err_int_ena:1;
+        /** i2c_rx_data_int_ena : R/W; bitpos: [6]; default: 0;
+         *  enable receive data interrupt
+         */
+        uint32_t i2c_rx_data_int_ena:1;
+        /** i2c_tx_data_int_ena : R/W; bitpos: [7]; default: 0;
+         *  enable transit data interrupt
+         */
+        uint32_t i2c_tx_data_int_ena:1;
+        /** i2c_detect_start_int_ena : R/W; bitpos: [8]; default: 0;
+         *  enable detect start interrupt
+         */
+        uint32_t i2c_detect_start_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} rtc_i2c_int_ena_reg_t;
+
+
+/** Group: version Registers */
+/** Type of i2c_date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** i2c_i2c_date : R/W; bitpos: [27:0]; default: 26235664;
+         *  version
+         */
+        uint32_t i2c_i2c_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} rtc_i2c_date_reg_t;
+
+
+typedef struct {
+    volatile rtc_i2c_scl_low_reg_t i2c_scl_low;
+    volatile rtc_i2c_ctrl_reg_t i2c_ctrl;
+    volatile rtc_i2c_status_reg_t i2c_status;
+    volatile rtc_i2c_to_reg_t i2c_to;
+    volatile rtc_i2c_slave_addr_reg_t i2c_slave_addr;
+    volatile rtc_i2c_scl_high_reg_t i2c_scl_high;
+    volatile rtc_i2c_sda_duty_reg_t i2c_sda_duty;
+    volatile rtc_i2c_scl_start_period_reg_t i2c_scl_start_period;
+    volatile rtc_i2c_scl_stop_period_reg_t i2c_scl_stop_period;
+    volatile rtc_i2c_int_clr_reg_t i2c_int_clr;
+    volatile rtc_i2c_int_raw_reg_t i2c_int_raw;
+    volatile rtc_i2c_int_st_reg_t i2c_int_st;
+    volatile rtc_i2c_int_ena_reg_t i2c_int_ena;
+    volatile rtc_i2c_data_reg_t i2c_data;
+    volatile rtc_i2c_cmd0_reg_t i2c_cmd0;
+    volatile rtc_i2c_cmd1_reg_t i2c_cmd1;
+    volatile rtc_i2c_cmd2_reg_t i2c_cmd2;
+    volatile rtc_i2c_cmd3_reg_t i2c_cmd3;
+    volatile rtc_i2c_cmd4_reg_t i2c_cmd4;
+    volatile rtc_i2c_cmd5_reg_t i2c_cmd5;
+    volatile rtc_i2c_cmd6_reg_t i2c_cmd6;
+    volatile rtc_i2c_cmd7_reg_t i2c_cmd7;
+    volatile rtc_i2c_cmd8_reg_t i2c_cmd8;
+    volatile rtc_i2c_cmd9_reg_t i2c_cmd9;
+    volatile rtc_i2c_cmd10_reg_t i2c_cmd10;
+    volatile rtc_i2c_cmd11_reg_t i2c_cmd11;
+    volatile rtc_i2c_cmd12_reg_t i2c_cmd12;
+    volatile rtc_i2c_cmd13_reg_t i2c_cmd13;
+    volatile rtc_i2c_cmd14_reg_t i2c_cmd14;
+    volatile rtc_i2c_cmd15_reg_t i2c_cmd15;
+    uint32_t reserved_078[33];
+    volatile rtc_i2c_date_reg_t i2c_date;
+} rtc_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtc_dev_t) == 0x100, "Invalid size of rtc_dev_t structure");
+#endif
+
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_RTC_I2C_STRUCT_H_ */

docs/en/api-reference/peripherals/i2c.rst

@@ -148,6 +148,25 @@ When :cpp:member:`i2c_config_t::clk_flags` is 0, the clock allocator will select
     1. :c:macro:`I2C_SCLK_SRC_FLAG_AWARE_DFS`: Clock's baud rate will not change while APB clock is changing.
     2. :c:macro:`I2C_SCLK_SRC_FLAG_LIGHT_SLEEP`: It supports Light-sleep mode, which APB clock cannot do.
 
+.. only:: esp32s3
+
+    .. list-table:: Characteristics of {IDF_TARGET_NAME} clock sources
+       :widths: 5 5 50 20
+       :header-rows: 1
+
+       * - Clock name
+         - Clock frequency
+         - MAX freq for SCL
+         - Clock capabilities
+       * - XTAL clock
+         - 40 MHz
+         - 2 MHz
+         - /
+       * - RTC clock
+         - 20 MHz
+         - 1 MHz
+         - :c:macro:`I2C_SCLK_SRC_FLAG_AWARE_DFS`, :c:macro:`I2C_SCLK_SRC_FLAG_LIGHT_SLEEP`
+
 .. only:: esp32c3
 
     .. list-table:: Characteristics of {IDF_TARGET_NAME} clock sources

examples/peripherals/i2c/i2c_self_test/README.md

@@ -19,7 +19,7 @@ To run this example, you should have one ESP development board (e.g. ESP32-WROVE
 
 #### Pin Assignment(esp32, esp32s2):
 
-**Note:** The following pin assignments are used by default, yout can change these  in the `menuconfig` .
+**Note:** The following pin assignments are used by default, you can change these  in the `menuconfig` .
 
 |                           | SDA    | SCL    |
 | ------------------------- | ------ | ------ |
@@ -41,6 +41,30 @@ To run this example, you should have one ESP development board (e.g. ESP32-WROVE
 
 **Note:** It is recommended to add external pull-up resistors for SDA/SCL pins to make the communication more stable, though the driver will enable internal pull-up resistors.
 
+#### Pin Assignment(esp32s3):
+
+**Note:** The following pin assignments are used by default, you can change these  in the `menuconfig` .
+
+|                           | SDA    | SCL    |
+| ------------------------- | ------ | ------ |
+| ESP32-S3 I2C Master       | GPIO1  | GPIO2  |
+| ESP32-S3 I2C Slave        | GPIO4  | GPIO5  |
+| BH1750 Sensor             | SDA    | SCL    |
+
+- slave:
+  - GPIO4 is assigned as the data signal of I2C slave port
+  - GPIO5 is assigned as the clock signal of I2C slave port
+- master:
+  - GPIO1 is assigned as the data signal of I2C master port
+  - GPIO2 is assigned as the clock signal of I2C master port
+
+- Connection:
+  - connect GPIO1 with GPIO4
+  - connect GPIO2 with GPIO5
+  - connect SDA/SCL of BH1750 sensor with GPIO18/GPIO19
+
+**Note:** It is recommended to add external pull-up resistors for SDA/SCL pins to make the communication more stable, though the driver will enable internal pull-up resistors.
+
 #### Pin Assignment(esp32c3):
 
 **Note:** The following pin assignments are used by default, you can change these in the `menuconfig` .

examples/peripherals/i2c/i2c_self_test/main/Kconfig.projbuild

@@ -4,14 +4,16 @@ menu "Example Configuration"
         config I2C_MASTER_SCL
             int "SCL GPIO Num"
             default 6 if IDF_TARGET_ESP32C3
-            default 19 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+            default 2 if  IDF_TARGET_ESP32S3
+            default 19 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2
             help
                 GPIO number for I2C Master clock line.
 
         config I2C_MASTER_SDA
             int "SDA GPIO Num"
             default 5 if IDF_TARGET_ESP32C3
-            default 18 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+            default 1 if  IDF_TARGET_ESP32S3
+            default 18 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2
             help
                 GPIO number for I2C Master data line.
 

examples/peripherals/i2c/i2c_tools/README.md

@@ -18,15 +18,18 @@ If you have some trouble in developing I2C related applications, or just want to
 
 ### Hardware Required
 
-To run this example, you should have one ESP32 dev board (e.g. ESP32-WROVER Kit) or ESP32 core board (e.g. ESP32-DevKitC). For test purpose, you should have a kind of device with I2C interface as well. Here we will take the CCS811 sensor as an example to show how to test the function of this sensor without writing any code (just use the command-line tools supported by this example). For more information about CCS811, you can consult the [online datasheet](http://ams.com/ccs811).
+To run this example, you should have any ESP32, ESP32-S and ESP32-C based development board. For test purpose, you should have a kind of device with I2C interface as well. Here we will take the CCS811 sensor as an example to show how to test the function of this sensor without writing any code (just use the command-line tools supported by this example). For more information about CCS811, you can consult the [online datasheet](http://ams.com/ccs811).
 
 #### Pin Assignment:
 
 **Note:** The following pin assignments are used by default, you can change them with `i2cconfig` command at any time.
 
 |                     | SDA    | SCL    | GND  | Other | VCC  |
-| ---------------- | ------ | ------ | ---- | ----- | ---- |
+| ------------------- | ------ | ------ | ---- | ----- | ---- |
 | ESP32 I2C Master    | GPIO18 | GPIO19 | GND  | GND   | 3.3V |
+| ESP32-S2 I2C Master | GPIO18 | GPIO19 | GND  | GND   | 3.3V |
+| ESP32-S3 I2C Master | GPIO1  | GPIO2  | GND  | GND   | 3.3V |
+| ESP32-C3 I2C Master | GPIO5  | GPIO6  | GND  | GND   | 3.3V |
 | Sensor              | SDA    | SCL    | GND  | WAK   | VCC  |
 
 **Note: ** There’s no need to add an external pull-up resistors for SDA/SCL pin, because the driver will enable the internal pull-up resistors itself.

examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c

@@ -23,8 +23,17 @@
 
 static const char *TAG = "cmd_i2ctools";
 
+#if CONFIG_IDF_TARGET_ESP32S3
+static gpio_num_t i2c_gpio_sda = 1;
+static gpio_num_t i2c_gpio_scl = 2;
+#elif CONFIG_IDF_TARGET_ESP32C3
+static gpio_num_t i2c_gpio_sda = 5;
+static gpio_num_t i2c_gpio_scl = 6;
+#else
 static gpio_num_t i2c_gpio_sda = 18;
 static gpio_num_t i2c_gpio_scl = 19;
+#endif
+
 static uint32_t i2c_frequency = 100000;
 static i2c_port_t i2c_port = I2C_NUM_0;