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fix(console): enable to select UART1 port for console output

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This feature was only enabled for esp32, esp32s2, esp32s3 previously.
Now, enabling this feature for all targets.
This commit is contained in:
Song Ruo Jing
2023-10-24 11:40:35 +08:00
parent c90d14c979
commit 55ed548cc6
28 changed files with 132 additions and 149 deletions
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12
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@@ -363,6 +363,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 21
config SOC_GPIO_OUT_RANGE_MAX
int
default 21
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
@@ -907,10 +915,6 @@ config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_REQUIRE_CORE_RESET
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y

5
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -169,6 +169,10 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
@@ -392,7 +396,6 @@
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_REQUIRE_CORE_RESET (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)