From 56e992095872bf873157304e897a266619af30c7 Mon Sep 17 00:00:00 2001 From: Chen Yi Qun Date: Thu, 22 Jul 2021 18:10:30 +0800 Subject: [PATCH] uart: add wakeup event for esp32c3 --- components/driver/include/driver/uart.h | 3 +++ components/driver/uart.c | 18 +++++++++++++++++- components/hal/esp32c3/include/hal/uart_ll.h | 1 + components/soc/esp32c3/include/soc/soc_caps.h | 1 + 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/components/driver/include/driver/uart.h b/components/driver/include/driver/uart.h index 76aa424fa2..45e2104f80 100644 --- a/components/driver/include/driver/uart.h +++ b/components/driver/include/driver/uart.h @@ -58,6 +58,9 @@ typedef enum { UART_PARITY_ERR, /*!< UART RX parity event*/ UART_DATA_BREAK, /*!< UART TX data and break event*/ UART_PATTERN_DET, /*!< UART pattern detected */ +#if SOC_UART_SUPPORT_WAKEUP + UART_WAKEUP, /*!< UART wakeup event */ +#endif UART_EVENT_MAX, /*!< UART event max index*/ } uart_event_type_t; diff --git a/components/driver/uart.c b/components/driver/uart.c index cc133237cf..22bc7fa81e 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -47,11 +47,20 @@ static const char *UART_TAG = "uart"; #define UART_PATTERN_DET_QLEN_DEFAULT (10) #define UART_MIN_WAKEUP_THRESH (UART_LL_MIN_WAKEUP_THRESH) +#if SOC_UART_SUPPORT_WAKEUP +#define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \ + | (UART_INTR_RXFIFO_TOUT) \ + | (UART_INTR_RXFIFO_OVF) \ + | (UART_INTR_BRK_DET) \ + | (UART_INTR_PARITY_ERR)) \ + | (UART_INTR_WAKEUP) +#else #define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \ | (UART_INTR_RXFIFO_TOUT) \ | (UART_INTR_RXFIFO_OVF) \ | (UART_INTR_BRK_DET) \ | (UART_INTR_PARITY_ERR)) +#endif #define UART_ENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux) #define UART_EXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux) @@ -1081,7 +1090,14 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken); } - } else { + } + #if SOC_UART_SUPPORT_WAKEUP + else if (uart_intr_status & UART_INTR_WAKEUP) { + uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_WAKEUP); + uart_event.type = UART_WAKEUP; + } + #endif + else { uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), uart_intr_status); /*simply clear all other intr status*/ uart_event.type = UART_EVENT_MAX; } diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index f94296327a..25f36d6e48 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -59,6 +59,7 @@ typedef enum { UART_INTR_RS485_FRM_ERR = (0x1 << 16), UART_INTR_RS485_CLASH = (0x1 << 17), UART_INTR_CMD_CHAR_DET = (0x1 << 18), + UART_INTR_WAKEUP = (0x1 << 19), } uart_intr_t; static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) { diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index f3395bb06b..30a5369c10 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -288,6 +288,7 @@ #define SOC_UART_SUPPORT_RTC_CLK (1) #define SOC_UART_SUPPORT_XTAL_CLK (1) +#define SOC_UART_SUPPORT_WAKEUP (1) #define SOC_UART_REQUIRE_CORE_RESET (1) // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled