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remove(essl): remove essl related files

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Chen Jichang
2025-07-01 11:29:34 +08:00
parent e5d11d11f9
commit 5909a4d685
41 changed files with 18 additions and 3584 deletions
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2
CMakeLists.txt
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@@ -105,8 +105,6 @@ if(CMAKE_C_COMPILER_ID MATCHES "Clang")
list(APPEND compile_options "-Wno-char-subscripts") list(APPEND compile_options "-Wno-char-subscripts")
# Clang seems to notice format string issues which GCC doesn't. # Clang seems to notice format string issues which GCC doesn't.
list(APPEND compile_options "-Wno-format-security") list(APPEND compile_options "-Wno-format-security")
# Logic bug in essl component
list(APPEND compile_options "-Wno-tautological-overlap-compare")
# Some pointer checks in mDNS component check addresses which can't be NULL # Some pointer checks in mDNS component check addresses which can't be NULL
list(APPEND compile_options "-Wno-tautological-pointer-compare") list(APPEND compile_options "-Wno-tautological-pointer-compare")
# Similar to the above, in tcp_transport # Similar to the above, in tcp_transport

10
components/driver/test_apps/components/esp_serial_slave_link/CMakeLists.txt
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@@ -1,10 +0,0 @@
idf_component_register(SRCS "essl.c"
"essl_sdio.c"
"essl_spi.c"
"essl_sdio_defs.c"
INCLUDE_DIRS "include"
REQUIRES "sdmmc"
"driver"
PRIV_INCLUDE_DIRS "."
"include/esp_serial_slave_link"
)

202
components/driver/test_apps/components/esp_serial_slave_link/LICENSE
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@@ -1,202 +0,0 @@
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16
components/driver/test_apps/components/esp_serial_slave_link/README.md
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@@ -1,16 +0,0 @@
# Espressif Serial Slave Link (ESSL) component
This component used to reside in [esp-idf](https://github.com/espressif/esp-idf) project as its component.
It's used on the HOST, to communicate with ESP chips as SLAVE via SDIO/SPI slave HD mode.
The port layer (`essl_sdio.c/essl_spi.c`) are currently only written to run on ESP chips in master mode, but you may also modify them to work on more platforms.
See more documentation: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/protocols/esp_serial_slave_link.html
But it's going to be an idf-extra-component, and should be pulled-in by an idf_component.yml (See `examples/peripherals/sdio/host/main/idf_component.yml`).
This folder is here for two purposes:
1. Fix a version for tests, to make them stable and not affected by external factors such as network, changes in idf-extra-components, etc.
2. Build Programming Guide from ESP-IDF before ESSL actually have a place to put the documents.

232
components/driver/test_apps/components/esp_serial_slave_link/essl.c
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@@ -1,232 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "essl.h"
#include "essl_internal.h"
#define TIME_EXPIRED_SINCE_CORE(start, end, timeout, max) (bool)((end)>=(start)? \
((end)-(start)>(timeout)) :\
((max)-(timeout)>(start)-(end)))
#define TIME_EXPIRED_SINCE(start, end, timeout) TIME_EXPIRED_SINCE_CORE(start, end, timeout, UINT32_MAX)
#define MINUS_UNTIL_ZERO(a, b) ( ((a) > (b)) ? ((a)-(b)): 0)
#define TIME_REMAIN_CORE(start, end, timeout, max) ((end)>=(start)?\
MINUS_UNTIL_ZERO(timeout, (end)-(start)):\
MINUS_UNTIL_ZERO((start)-(end), (max)-(timeout)))
#define TIME_REMAIN(start, end, timeout) TIME_REMAIN_CORE(start, end, timeout, UINT32_MAX)
#define ESSL_MIN(a, b) ((a) < (b) ? (a) : (b))
__attribute__((unused)) static const char TAG[] = "esp_serial_slave_link";
#define _CHECK_EXECUTE_CMD(DEV, CMD, STR, ...) do{ \
if ((DEV) == NULL) { \
return ESP_ERR_INVALID_ARG; \
} \
if ((DEV)->CMD) { \
return (DEV)->CMD((DEV)->args,##__VA_ARGS__); \
} else { \
ESP_LOGE(TAG, STR); \
return ESP_ERR_NOT_SUPPORTED; \
} } while(0)
#define CHECK_EXECUTE_CMD(DEV, CMD, ...) _CHECK_EXECUTE_CMD(DEV, CMD, #CMD" not supported for the current device.",##__VA_ARGS__)
esp_err_t essl_init(essl_handle_t handle, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, init, wait_ms);
}
esp_err_t essl_wait_for_ready(essl_handle_t handle, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, wait_for_ready, wait_ms);
}
esp_err_t essl_send_packet(essl_handle_t handle, const void *start, size_t length, uint32_t wait_ms)
{
if (handle == NULL || start == NULL || length == 0) {
return ESP_ERR_INVALID_ARG;
}
if (handle->send_packet == NULL) {
return ESP_ERR_NOT_SUPPORTED;
}
esp_err_t err;
const uint32_t timeout_ticks = pdMS_TO_TICKS(wait_ms);
uint32_t pre = xTaskGetTickCount();
uint32_t now;
uint32_t remain_wait_ms = 0;
do {
now = xTaskGetTickCount();
remain_wait_ms = pdTICKS_TO_MS(TIME_REMAIN(pre, now, timeout_ticks));
err = handle->send_packet(handle->args, start, length, remain_wait_ms);
if (err == ESP_OK) {
break;
} else if (err != ESP_ERR_NOT_FOUND) {
return err;
} // else ESP_ERR_NOT_FOUND
//the slave is not ready, retry
} while (remain_wait_ms > 0);
return err;
}
esp_err_t essl_get_packet(essl_handle_t handle, void *out_data, size_t size, size_t *out_length, uint32_t wait_ms)
{
if (handle == NULL) {
return ESP_ERR_INVALID_ARG;
}
if (out_data == NULL || size == 0 || out_length == NULL) {
return ESP_ERR_INVALID_ARG;
}
if (handle->get_packet == NULL || handle->update_rx_data_size == NULL || handle->get_rx_data_size == NULL) {
return ESP_ERR_NOT_SUPPORTED;
}
esp_err_t err;
const uint32_t timeout_ticks = pdMS_TO_TICKS(wait_ms);
uint32_t pre = xTaskGetTickCount();
uint32_t now = 3;
uint32_t wait_remain_ms = 0;
int data_available = handle->get_rx_data_size(handle->args);
// if there is already enough data to read, skip the length update.
if (data_available < size) {
//loop until timeout, or there is at least one byte
do {
now = xTaskGetTickCount();
wait_remain_ms = pdTICKS_TO_MS(TIME_REMAIN(pre, now, timeout_ticks));
err = handle->update_rx_data_size(handle->args, wait_remain_ms);
if (err != ESP_OK) {
return err;
}
data_available = handle->get_rx_data_size(handle->args);
if (data_available > 0) {
break;
}
} while (wait_remain_ms > 0);
}
if (data_available == 0) {
//the slave has no data to send
return ESP_ERR_NOT_FOUND;
}
int len = ESSL_MIN(data_available, size);
now = xTaskGetTickCount();
wait_remain_ms = pdTICKS_TO_MS(TIME_REMAIN(pre, now, timeout_ticks));
err = handle->get_packet(handle->args, out_data, len, wait_remain_ms);
if (err != ESP_OK) {
return err;
}
*out_length = len;
if (len < data_available) {
return ESP_ERR_NOT_FINISHED;
}
return ESP_OK;
}
esp_err_t essl_get_tx_buffer_num(essl_handle_t handle, uint32_t *out_tx_num, uint32_t wait_ms)
{
if (handle == NULL || out_tx_num == NULL) {
return ESP_ERR_INVALID_ARG;
}
if (handle->update_tx_buffer_num == NULL || handle->get_tx_buffer_num == NULL) {
return ESP_ERR_NOT_SUPPORTED;
}
esp_err_t err = handle->update_tx_buffer_num(handle->args, wait_ms);
if (err != ESP_OK) {
return err;
}
*out_tx_num = handle->get_tx_buffer_num(handle->args);
return ESP_OK;
}
esp_err_t essl_get_rx_data_size(essl_handle_t handle, uint32_t *out_rx_size, uint32_t wait_ms)
{
if (handle == NULL || out_rx_size == NULL) {
return ESP_ERR_INVALID_ARG;
}
if (handle->update_rx_data_size == NULL || handle->get_rx_data_size == NULL) {
return ESP_ERR_NOT_SUPPORTED;
}
esp_err_t err = handle->update_rx_data_size(handle->args, wait_ms);
if (err != ESP_OK) {
return err;
}
*out_rx_size = handle->get_rx_data_size(handle->args);
return ESP_OK;
}
esp_err_t essl_write_reg(essl_handle_t handle, uint8_t addr, uint8_t value, uint8_t *value_o, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, write_reg, addr, value, value_o, wait_ms);
}
esp_err_t essl_read_reg(essl_handle_t handle, uint8_t add, uint8_t *value_o, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, read_reg, add, value_o, wait_ms);
}
esp_err_t essl_wait_int(essl_handle_t handle, TickType_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, wait_int, wait_ms);
}
esp_err_t essl_reset_cnt(essl_handle_t handle)
{
if (handle == NULL) {
return ESP_ERR_INVALID_ARG;
}
if (handle->reset_cnt == NULL) {
return ESP_ERR_NOT_SUPPORTED;
}
handle->reset_cnt(handle->args);
return ESP_OK;
}
esp_err_t essl_clear_intr(essl_handle_t handle, uint32_t intr_mask, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, clear_intr, intr_mask, wait_ms);
}
esp_err_t essl_get_intr(essl_handle_t handle, uint32_t *intr_raw, uint32_t *intr_st, uint32_t wait_ms)
{
if (intr_raw == NULL && intr_st == NULL) {
return ESP_ERR_INVALID_ARG;
}
CHECK_EXECUTE_CMD(handle, get_intr, intr_raw, intr_st, wait_ms);
}
esp_err_t essl_set_intr_ena(essl_handle_t handle, uint32_t ena_mask, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, set_intr_ena, ena_mask, wait_ms);
}
esp_err_t essl_get_intr_ena(essl_handle_t handle, uint32_t *ena_mask_o, uint32_t wait_ms)
{
if (ena_mask_o == NULL) {
return ESP_ERR_INVALID_ARG;
}
CHECK_EXECUTE_CMD(handle, get_intr_ena, ena_mask_o, wait_ms);
}
esp_err_t essl_send_slave_intr(essl_handle_t handle, uint32_t intr_mask, uint32_t wait_ms)
{
CHECK_EXECUTE_CMD(handle, send_slave_intr, intr_mask, wait_ms);
}

38
components/driver/test_apps/components/esp_serial_slave_link/essl_internal.h
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@@ -1,38 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <esp_types.h>
#include <esp_err.h>
/** Context used by the ``esp_serial_slave_link`` component.
*/
struct essl_dev_t {
void *args;
esp_err_t (*init)(void *ctx, uint32_t wait_ms);
esp_err_t (*wait_for_ready)(void *ctx, uint32_t wait_ms);
esp_err_t (*update_tx_buffer_num)(void *ctx, uint32_t wait_ms);
esp_err_t (*update_rx_data_size)(void *ctx, uint32_t wait_ms);
esp_err_t (*send_packet)(void *ctx, const void *start, size_t length, uint32_t wait_ms);
esp_err_t (*get_packet)(void *ctx, void *out_data, size_t size, uint32_t wait_ms);
esp_err_t (*write_reg)(void *ctx, uint8_t addr, uint8_t value, uint8_t *value_o, uint32_t wait_ms);
esp_err_t (*read_reg)(void *ctx, uint8_t add, uint8_t *value_o, uint32_t wait_ms);
esp_err_t (*wait_int)(void *ctx, uint32_t wait_ms);
esp_err_t (*clear_intr)(void *ctx, uint32_t intr_mask, uint32_t wait_ms);
esp_err_t (*get_intr)(void *ctx, uint32_t *intr_raw, uint32_t *intr_st, uint32_t wait_ms);
esp_err_t (*set_intr_ena)(void *ctx, uint32_t ena_mask, uint32_t wait_ms);
esp_err_t (*get_intr_ena)(void *ctx, uint32_t *ena_mask_o, uint32_t wait_ms);
esp_err_t (*send_slave_intr)(void *ctx, uint32_t intr_mask, uint32_t wait_ms);
uint32_t (*get_tx_buffer_num)(void *ctx);
uint32_t (*get_rx_data_size)(void *ctx);
void (*reset_cnt)(void *ctx);
};
typedef struct essl_dev_t essl_dev_t;

506
components/driver/test_apps/components/esp_serial_slave_link/essl_sdio.c
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@@ -1,506 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "esp_log.h"
#include "sdmmc_cmd.h"
#include "driver/sdmmc_defs.h"
#include "essl_internal.h"
#include "essl_sdio.h"
static const char TAG[] = "essl_sdio";
#ifndef DR_REG_SLCHOST_BASE
#define DR_REG_SLCHOST_BASE 0 //The SDIO slave only check the least significant 10 bits, this doesn't matter
#endif
//This should be consistent with the macro in soc/host_reg.h
#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
#define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
#define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
#define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
#define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C)
#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C)
#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4)
#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC)
#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
#define ESSL_CMD53_END_ADDR 0x1f800
#define TX_BUFFER_MAX 0x1000
#define TX_BUFFER_MASK 0xFFF
#define RX_BYTE_MAX 0x100000
#define RX_BYTE_MASK 0xFFFFF
#define FUNC1_EN_MASK (BIT(1))
/**
* Initialize ``void`` over SDIO by this macro.
*/
#define ESSL_SDIO_DEFAULT_CONTEXT() (essl_dev_t){\
.init = essl_sdio_init, \
.wait_for_ready = essl_sdio_wait_for_ready, \
.get_tx_buffer_num = essl_sdio_get_tx_buffer_num,\
.update_tx_buffer_num = essl_sdio_update_tx_buffer_num,\
.get_rx_data_size = essl_sdio_get_rx_data_size,\
.update_rx_data_size = essl_sdio_update_rx_data_size,\
.send_packet = essl_sdio_send_packet,\
.get_packet = essl_sdio_get_packet,\
.write_reg = essl_sdio_write_reg,\
.read_reg = essl_sdio_read_reg,\
.wait_int = essl_sdio_wait_int,\
.send_slave_intr = essl_sdio_send_slave_intr, \
.get_intr = essl_sdio_get_intr, \
.clear_intr = essl_sdio_clear_intr, \
.set_intr_ena = essl_sdio_set_intr_ena, \
.reset_cnt = essl_sdio_reset_cnt, \
}
typedef struct {
//common part
uint16_t buffer_size;
///< All data that do not fully fill a buffer is still counted as one buffer. E.g. 10 bytes data costs 2 buffers if the size is 8 bytes per buffer.
///< Buffer size of the slave pre-defined between host and slave before communication.
size_t tx_sent_buffers; ///< Counter holding the amount of buffers already sent to ESP32 slave. Should be set to 0 when initialization.
size_t tx_sent_buffers_latest; ///< The latest reading (from the slave) of counter holding the amount of buffers loaded. Should be set to 0 when initialization.
size_t rx_got_bytes; ///< Counter holding the amount of bytes already received from ESP32 slave. Should be set to 0 when initialization.
size_t rx_got_bytes_latest; ///< The latest reading (from the slave) of counter holding the amount of bytes to send. Should be set to 0 when initialization.
sdmmc_card_t *card; ///< Initialized sdmmc_cmd card
uint16_t block_size;
///< If this is too large, it takes time to send stuff bits; while if too small, intervals between blocks cost much.
///< Should be set according to length of data, and larger than ``TRANS_LEN_MAX/511``.
///< Block size of the SDIO function 1. After the initialization this will hold the value the slave really do. Valid value is 1-2048.
} essl_sdio_context_t;
esp_err_t essl_sdio_update_tx_buffer_num(void *arg, uint32_t wait_ms);
esp_err_t essl_sdio_update_rx_data_size(void *arg, uint32_t wait_ms);
static inline esp_err_t essl_sdio_write_byte(sdmmc_card_t *card, uint32_t addr, uint8_t val, uint8_t *val_o)
{
return sdmmc_io_write_byte(card, 1, addr & 0x3FF, val, val_o);
}
static inline esp_err_t essl_sdio_write_bytes(sdmmc_card_t *card, uint32_t addr, uint8_t *val, int len)
{
return sdmmc_io_write_bytes(card, 1, addr & 0x3FF, val, len);
}
static inline esp_err_t essl_sdio_read_byte(sdmmc_card_t *card, uint32_t addr, uint8_t *val_o)
{
return sdmmc_io_read_byte(card, 1, addr & 0x3FF, val_o);
}
static inline esp_err_t essl_sdio_read_bytes(sdmmc_card_t *card, uint32_t addr, uint8_t *val_o, int len)
{
return sdmmc_io_read_bytes(card, 1, addr & 0x3FF, val_o, len);
}
esp_err_t essl_sdio_init_dev(essl_handle_t *out_handle, const essl_sdio_config_t *config)
{
esp_err_t ret = ESP_OK;
essl_sdio_context_t *arg = NULL;
essl_dev_t *dev = NULL;
arg = (essl_sdio_context_t *)heap_caps_malloc(sizeof(essl_sdio_context_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
dev = (essl_dev_t *)heap_caps_malloc(sizeof(essl_dev_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
if (arg == NULL || dev == NULL) {
ret = ESP_ERR_NO_MEM;
goto cleanup;
}
*dev = ESSL_SDIO_DEFAULT_CONTEXT();
dev->args = arg;
*arg = (essl_sdio_context_t) {
.card = config->card,
.block_size = 0x200,
.buffer_size = config->recv_buffer_size,
.tx_sent_buffers = 0,
.rx_got_bytes = 0,
};
*out_handle = dev;
return ESP_OK;
cleanup:
free(arg);
free(dev);
return ret;
}
esp_err_t essl_sdio_deinit_dev(essl_handle_t handle)
{
if (handle) {
free(handle->args);
}
free(handle);
return ESP_OK;
}
esp_err_t essl_sdio_init(void *arg, uint32_t wait_ms)
{
essl_sdio_context_t *ctx = arg;
esp_err_t err;
uint8_t ioe = 0;
sdmmc_card_t *card = ctx->card;
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "IOE: 0x%02"PRIx8, ioe);
uint8_t ior = 0;
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "IOR: 0x%02"PRIx8, ior);
// enable function 1
ioe |= FUNC1_EN_MASK;
err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_FN_ENABLE, ioe, &ioe);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "IOE: 0x%02"PRIx8, ioe);
// wait for the card to become ready
while ((ior & FUNC1_EN_MASK) == 0) {
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "IOR: 0x%02"PRIx8, ior);
}
// get interrupt status
uint8_t ie = 0;
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "IE: 0x%02"PRIx8, ie);
// enable interrupts for function 1&2 and master enable
ie |= BIT(0) | FUNC1_EN_MASK;
err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_INT_ENABLE, ie, &ie);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "IE: 0x%02"PRIx8, ie);
// get bus width register
uint8_t bus_width = 0;
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_BUS_WIDTH, &bus_width);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "BUS_WIDTH: 0x%02"PRIx8, bus_width);
// enable continuous SPI interrupts
bus_width |= CCCR_BUS_WIDTH_ECSI;
err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_BUS_WIDTH, bus_width, &bus_width);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "BUS_WIDTH: 0x%02"PRIx8, bus_width);
uint16_t bs = 512;
const uint8_t *bs_u8 = (const uint8_t *) &bs;
uint16_t bs_read = 0;
uint8_t *bs_read_u8 = (uint8_t *) &bs_read;
// Set block sizes for functions 0 to 512 bytes
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0]));
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1]));
ESP_LOGD(TAG, "Function 0 BS: %d", (unsigned int) bs_read);
ESP_ERROR_CHECK(sdmmc_io_write_byte(card, 0, SD_IO_CCCR_BLKSIZEL, bs_u8[0], NULL));
ESP_ERROR_CHECK(sdmmc_io_write_byte(card, 0, SD_IO_CCCR_BLKSIZEH, bs_u8[1], NULL));
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0]));
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1]));
ESP_LOGD(TAG, "Function 0 BS: %d", (unsigned int) bs_read);
// Set block sizes for functions 1 to given value (default value = 512).
if (ctx->block_size > 0 && ctx->block_size <= 2048) {
bs = ctx->block_size;
} else {
bs = 512;
}
size_t offset = SD_IO_FBR_START * 1;
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0]));
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1]));
ESP_LOGD(TAG, "Function 1 BS: %d", (unsigned int) bs_read);
ESP_ERROR_CHECK(sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, bs_u8[0], NULL));
ESP_ERROR_CHECK(sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, bs_u8[1], NULL));
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0]));
ESP_ERROR_CHECK(sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1]));
ESP_LOGD(TAG, "Function 1 BS: %d", (unsigned int) bs_read);
if (bs_read != ctx->block_size) {
ESP_LOGW(TAG, "Function1 block size %d different than set value %d", bs_read, ctx->block_size);
ctx->block_size = bs_read;
}
return ESP_OK;
}
esp_err_t essl_sdio_wait_for_ready(void *arg, uint32_t wait_ms)
{
ESP_LOGV(TAG, "wait_for_ioready");
esp_err_t err;
sdmmc_card_t *card = ((essl_sdio_context_t *)arg)->card;
// wait for the card to become ready
uint8_t ior = 0;
while ((ior & FUNC1_EN_MASK) == 0) {
err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior);
if (err != ESP_OK) {
return err;
}
ESP_LOGD(TAG, "IOR: 0x%02x", ior);
}
return ESP_OK;
}
esp_err_t essl_sdio_send_packet(void *arg, const void *start, size_t length, uint32_t wait_ms)
{
essl_sdio_context_t *ctx = arg;
uint16_t buffer_size = ctx->buffer_size;
int buffer_used = (length + buffer_size - 1) / buffer_size;
esp_err_t err;
if (essl_sdio_get_tx_buffer_num(arg) < buffer_used) {
//slave has no enough buffer, try update for once
esp_err_t err = essl_sdio_update_tx_buffer_num(arg, wait_ms);
if (err != ESP_OK) {
return err;
}
if (essl_sdio_get_tx_buffer_num(arg) < buffer_used) {
ESP_LOGV(TAG, "buffer is not enough: %d, %d required.", ctx->tx_sent_buffers_latest, ctx->tx_sent_buffers + buffer_used);
return ESP_ERR_NOT_FOUND;
}
}
ESP_LOGV(TAG, "send_packet: len: %d", length);
uint8_t *start_ptr = (uint8_t *)start;
uint32_t len_remain = length;
do {
const int block_size = 512;
/* Though the driver supports to split packet of unaligned size into
* length of 4x and 1~3, we still send aligned size of data to get
* higher efficiency. The length is determined by the SDIO address, and
* the remainning will be discard by the slave hardware.
*/
int block_n = len_remain / block_size;
int len_to_send;
if (block_n) {
len_to_send = block_n * block_size;
err = sdmmc_io_write_blocks(ctx->card, 1, ESSL_CMD53_END_ADDR - len_remain, start_ptr, len_to_send);
} else {
len_to_send = len_remain;
err = sdmmc_io_write_bytes(ctx->card, 1, ESSL_CMD53_END_ADDR - len_remain, start_ptr, (len_to_send + 3) & (~3));
}
if (err != ESP_OK) {
return err;
}
start_ptr += len_to_send;
len_remain -= len_to_send;
} while (len_remain);
ctx->tx_sent_buffers += buffer_used;
return ESP_OK;
}
esp_err_t essl_sdio_get_packet(void *arg, void *out_data, size_t size, uint32_t wait_ms)
{
essl_sdio_context_t *ctx = arg;
esp_err_t err;
ESP_LOGV(TAG, "get_packet: read size=%d", size);
if (essl_sdio_get_rx_data_size(arg) < size) {
err = essl_sdio_update_rx_data_size(arg, wait_ms);
if (err != ESP_OK) {
return err;
}
if (essl_sdio_get_rx_data_size(arg) < size) {
return ESP_ERR_NOT_FOUND;
}
}
uint8_t *start = out_data;
uint32_t len_remain = size;
do {
const int block_size = 512; //currently our driver don't support block size other than 512
int len_to_send;
int block_n = len_remain / block_size;
if (block_n != 0) {
len_to_send = block_n * block_size;
err = sdmmc_io_read_blocks(ctx->card, 1, ESSL_CMD53_END_ADDR - len_remain, start, len_to_send);
} else {
len_to_send = len_remain;
/* though the driver supports to split packet of unaligned size into length
* of 4x and 1~3, we still get aligned size of data to get higher
* efficiency. The length is determined by the SDIO address, and the
* remainning will be ignored by the slave hardware.
*/
err = sdmmc_io_read_bytes(ctx->card, 1, ESSL_CMD53_END_ADDR - len_remain, start, (len_to_send + 3) & (~3));
}
if (err != ESP_OK) {
return err;
}
start += len_to_send;
len_remain -= len_to_send;
ctx->rx_got_bytes += len_to_send;
} while (len_remain != 0);
return err;
}
uint32_t essl_sdio_get_tx_buffer_num(void *arg)
{
essl_sdio_context_t *ctx = arg;
ESP_LOGV(TAG, "tx latest: %d, sent: %d", ctx->tx_sent_buffers_latest, ctx->tx_sent_buffers);
return (ctx->tx_sent_buffers_latest + TX_BUFFER_MAX - ctx->tx_sent_buffers) % TX_BUFFER_MAX;
}
esp_err_t essl_sdio_update_tx_buffer_num(void *arg, uint32_t wait_ms)
{
essl_sdio_context_t *ctx = arg;
uint32_t len;
esp_err_t err;
err = essl_sdio_read_bytes(ctx->card, HOST_SLC0HOST_TOKEN_RDATA_REG, (uint8_t *) &len, 4);
if (err != ESP_OK) {
return err;
}
len = (len >> 16)&TX_BUFFER_MASK;
ctx->tx_sent_buffers_latest = len;
ESP_LOGV(TAG, "update_tx_buffer_num: %d", (unsigned int)len);
return ESP_OK;
}
uint32_t essl_sdio_get_rx_data_size(void *arg)
{
essl_sdio_context_t *ctx = arg;
ESP_LOGV(TAG, "rx latest: %d, read: %d", ctx->rx_got_bytes_latest, ctx->rx_got_bytes);
return (ctx->rx_got_bytes_latest + RX_BYTE_MAX - ctx->rx_got_bytes) % RX_BYTE_MAX;
}
esp_err_t essl_sdio_update_rx_data_size(void *arg, uint32_t wait_ms)
{
essl_sdio_context_t *ctx = arg;
uint32_t len;
esp_err_t err;
ESP_LOGV(TAG, "get_rx_data_size: got_bytes: %d", ctx->rx_got_bytes);
err = essl_sdio_read_bytes(ctx->card, HOST_SLCHOST_PKT_LEN_REG, (uint8_t *) &len, 4);
if (err != ESP_OK) {
return err;
}
len &= RX_BYTE_MASK;
ctx->rx_got_bytes_latest = len;
return ESP_OK;
}
esp_err_t essl_sdio_write_reg(void *arg, uint8_t addr, uint8_t value, uint8_t *value_o, uint32_t wait_ms)
{
ESP_LOGV(TAG, "write_reg: 0x%02"PRIX8, value);
// address over range
if (addr >= 60) {
return ESP_ERR_INVALID_ARG;
}
//W7 is reserved for interrupts
if (addr >= 28) {
addr += 4;
}
return essl_sdio_write_byte(((essl_sdio_context_t *)arg)->card, HOST_SLCHOST_CONF_W_REG(addr), value, value_o);
}
esp_err_t essl_sdio_read_reg(void *arg, uint8_t add, uint8_t *value_o, uint32_t wait_ms)
{
ESP_LOGV(TAG, "read_reg");
// address over range
if (add >= 60) {
return ESP_ERR_INVALID_ARG;
}
//W7 is reserved for interrupts
if (add >= 28) {
add += 4;
}
esp_err_t ret = essl_sdio_read_byte(((essl_sdio_context_t *)arg)->card, HOST_SLCHOST_CONF_W_REG(add), value_o);
ESP_LOGV(TAG, "reg: %02"PRIX8, *value_o);
return ret;
}
esp_err_t essl_sdio_clear_intr(void *arg, uint32_t intr_mask, uint32_t wait_ms)
{
ESP_LOGV(TAG, "clear_intr: %08"PRIX32, intr_mask);
return essl_sdio_write_bytes(((essl_sdio_context_t *) arg)->card, HOST_SLC0HOST_INT_CLR_REG, (uint8_t *) &intr_mask, 4);
}
esp_err_t essl_sdio_get_intr(void *arg, uint32_t *intr_raw, uint32_t *intr_st, uint32_t wait_ms)
{
essl_sdio_context_t *ctx = arg;
esp_err_t r;
ESP_LOGV(TAG, "get_intr");
if (intr_raw == NULL && intr_st == NULL) {
return ESP_ERR_INVALID_ARG;
}
if (intr_raw != NULL) {
r = essl_sdio_read_bytes(ctx->card, HOST_SLC0HOST_INT_RAW_REG, (uint8_t *) intr_raw, 4);
if (r != ESP_OK) {
return r;
}
}
if (intr_st != NULL) {
r = essl_sdio_read_bytes(ctx->card, HOST_SLC0HOST_INT_ST_REG, (uint8_t *) intr_st, 4);
if (r != ESP_OK) {
return r;
}
}
return ESP_OK;
}
esp_err_t essl_sdio_set_intr_ena(void *arg, uint32_t ena_mask, uint32_t wait_ms)
{
ESP_LOGV(TAG, "set_intr_ena: %08"PRIX32, ena_mask);
return essl_sdio_write_bytes(((essl_sdio_context_t *)arg)->card, HOST_SLC0HOST_FUNC1_INT_ENA_REG,
(uint8_t *) &ena_mask, 4);
}
esp_err_t essl_sdio_get_intr_ena(void *arg, uint32_t *ena_mask_o, uint32_t wait_ms)
{
ESP_LOGV(TAG, "get_intr_ena");
esp_err_t ret = essl_sdio_read_bytes(((essl_sdio_context_t *)arg)->card, HOST_SLC0HOST_FUNC1_INT_ENA_REG,
(uint8_t *) ena_mask_o, 4);
ESP_LOGV(TAG, "ena: %08"PRIX32, *ena_mask_o);
return ret;
}
esp_err_t essl_sdio_send_slave_intr(void *arg, uint32_t intr_mask, uint32_t wait_ms)
{
//Only 8 bits available
ESP_LOGV(TAG, "send_slave_intr: %02"PRIx8, (uint8_t)intr_mask);
return essl_sdio_write_byte(((essl_sdio_context_t *)arg)->card, HOST_SLCHOST_CONF_W7_REG + 0, (uint8_t)intr_mask, NULL);
}
esp_err_t essl_sdio_wait_int(void *arg, uint32_t wait_ms)
{
return sdmmc_io_wait_int(((essl_sdio_context_t *)arg)->card, wait_ms);
}
void essl_sdio_reset_cnt(void *arg)
{
essl_sdio_context_t *ctx = arg;
ctx->rx_got_bytes = 0;
ctx->tx_sent_buffers = 0;
}

17
components/driver/test_apps/components/esp_serial_slave_link/essl_sdio_defs.c
View File

@@ -1,17 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Definitions of Espressif SDIO Slave hardware
#include "essl_sdio.h"
essl_sdio_def_t ESSL_SDIO_DEF_ESP32 = {
.new_packet_intr_mask = BIT(23),
};
essl_sdio_def_t ESSL_SDIO_DEF_ESP32C6 = {
.new_packet_intr_mask = BIT(23),
};

491
components/driver/test_apps/components/esp_serial_slave_link/essl_spi.c
View File

@@ -1,491 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <sys/param.h>
#include "esp_log.h"
#include "esp_check.h"
#include "esp_memory_utils.h"
#include "esp_private/periph_ctrl.h"
#include "driver/spi_master.h"
#include "hal/spi_types.h"
#include "hal/spi_ll.h"
#include "essl_internal.h"
#include "essl_spi.h"
/**
* Initialise device function list of SPI by this macro.
*/
#define ESSL_SPI_DEFAULT_DEV_FUNC() (essl_dev_t) {\
.get_tx_buffer_num = essl_spi_get_tx_buffer_num,\
.update_tx_buffer_num = essl_spi_update_tx_buffer_num,\
.get_rx_data_size = essl_spi_get_rx_data_size,\
.update_rx_data_size = essl_spi_update_rx_data_size,\
.send_packet = essl_spi_send_packet,\
.get_packet = essl_spi_get_packet,\
.write_reg = essl_spi_write_reg,\
.read_reg = essl_spi_read_reg,\
}
static const char TAG[] = "essl_spi";
typedef struct {
spi_device_handle_t spi; // Pointer to SPI device handle.
/* Master TX, Slave RX */
struct {
size_t sent_buf_num; // Number of TX buffers that has been sent out by the master.
size_t slave_rx_buf_num; // Number of RX buffers loaded by the slave.
uint16_t tx_buffer_size; /* Buffer size for Master TX / Slave RX direction.
* Data with length within this size will still be regarded as one buffer.
* E.g. 10 bytes data costs 2 buffers if the size is 8 bytes per buffer. */
uint8_t tx_sync_reg; // The pre-negotiated register ID for Master-TX-SLAVE-RX synchronization. 1 word (4 Bytes) will be reserved for the synchronization.
} master_out;
/* Master RX, Slave TX */
struct {
size_t received_bytes; // Number of the RX bytes that has been received by the Master.
size_t slave_tx_bytes; // Number of the TX bytes that has been loaded by the Slave
uint8_t rx_sync_reg; // The pre-negotiated register ID for Master-RX-SLAVE-TX synchronization. 1 word (4 Bytes) will be reserved for the synchronization.
} master_in;
} essl_spi_context_t;
static uint16_t get_hd_command(spi_command_t cmd_t, uint32_t flags)
{
spi_line_mode_t line_mode = {
.cmd_lines = 1,
};
if (flags & SPI_TRANS_MODE_DIO) {
line_mode.data_lines = 2;
if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
line_mode.addr_lines = 2;
} else {
line_mode.addr_lines = 1;
}
} else if (flags & SPI_TRANS_MODE_QIO) {
line_mode.data_lines = 4;
if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
line_mode.addr_lines = 4;
} else {
line_mode.addr_lines = 1;
}
} else {
line_mode.data_lines = 1;
line_mode.addr_lines = 1;
}
return spi_ll_get_slave_hd_command(cmd_t, line_mode);
}
static int get_hd_dummy_bits(uint32_t flags)
{
spi_line_mode_t line_mode = {};
if (flags & SPI_TRANS_MODE_DIO) {
line_mode.data_lines = 2;
} else if (flags & SPI_TRANS_MODE_QIO) {
line_mode.data_lines = 4;
} else {
line_mode.data_lines = 1;
}
return spi_ll_get_slave_hd_dummy_bits(line_mode);
}
esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags)
{
spi_transaction_ext_t t = {
.base = {
.cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags),
.addr = addr % 72,
.rxlength = len * 8,
.rx_buffer = out_data,
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
},
.dummy_bits = get_hd_dummy_bits(flags),
};
return spi_device_transmit(spi, (spi_transaction_t *)&t);
}
esp_err_t essl_spi_rdbuf_polling(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags)
{
spi_transaction_ext_t t = {
.base = {
.cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags),
.addr = addr % 72,
.rxlength = len * 8,
.rx_buffer = out_data,
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
},
.dummy_bits = get_hd_dummy_bits(flags),
};
return spi_device_polling_transmit(spi, (spi_transaction_t *)&t);
}
esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags)
{
spi_transaction_ext_t t = {
.base = {
.cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags),
.addr = addr % 72,
.length = len * 8,
.tx_buffer = data,
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
},
.dummy_bits = get_hd_dummy_bits(flags),
};
return spi_device_transmit(spi, (spi_transaction_t *)&t);
}
esp_err_t essl_spi_wrbuf_polling(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags)
{
spi_transaction_ext_t t = {
.base = {
.cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags),
.addr = addr % 72,
.length = len * 8,
.tx_buffer = data,
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
},
.dummy_bits = get_hd_dummy_bits(flags),
};
return spi_device_polling_transmit(spi, (spi_transaction_t *)&t);
}
esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg_len, uint32_t flags)
{
spi_transaction_ext_t t = {
.base = {
.cmd = get_hd_command(SPI_CMD_HD_RDDMA, flags),
.rxlength = seg_len * 8,
.rx_buffer = out_data,
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
},
.dummy_bits = get_hd_dummy_bits(flags),
};
return spi_device_transmit(spi, (spi_transaction_t *)&t);
}
esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags)
{
spi_transaction_t end_t = {
.cmd = get_hd_command(SPI_CMD_HD_INT0, flags),
.flags = flags,
};
return spi_device_transmit(spi, &end_t);
}
esp_err_t essl_spi_rddma(spi_device_handle_t spi, uint8_t *out_data, int len, int seg_len, uint32_t flags)
{
if (!esp_ptr_dma_capable(out_data) || ((intptr_t)out_data % 4) != 0) {
return ESP_ERR_INVALID_ARG;
}
seg_len = (seg_len > 0) ? seg_len : len;
uint8_t *read_ptr = out_data;
esp_err_t ret = ESP_OK;
while (len > 0) {
int send_len = MIN(seg_len, len);
ret = essl_spi_rddma_seg(spi, read_ptr, send_len, flags);
if (ret != ESP_OK) {
return ret;
}
len -= send_len;
read_ptr += send_len;
}
return essl_spi_rddma_done(spi, flags);
}
esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int seg_len, uint32_t flags)
{
spi_transaction_ext_t t = {
.base = {
.cmd = get_hd_command(SPI_CMD_HD_WRDMA, flags),
.length = seg_len * 8,
.tx_buffer = data,
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
},
.dummy_bits = get_hd_dummy_bits(flags),
};
return spi_device_transmit(spi, (spi_transaction_t *)&t);
}
esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags)
{
spi_transaction_t end_t = {
.cmd = get_hd_command(SPI_CMD_HD_WR_END, flags),
.flags = flags,
};
return spi_device_transmit(spi, &end_t);
}
esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len, int seg_len, uint32_t flags)
{
if (!esp_ptr_dma_capable(data)) {
return ESP_ERR_INVALID_ARG;
}
seg_len = (seg_len > 0) ? seg_len : len;
while (len > 0) {
int send_len = MIN(seg_len, len);
esp_err_t ret = essl_spi_wrdma_seg(spi, data, send_len, flags);
if (ret != ESP_OK) {
return ret;
}
len -= send_len;
data += send_len;
}
return essl_spi_wrdma_done(spi, flags);
}
esp_err_t essl_spi_int(spi_device_handle_t spi, int int_n, uint32_t flags)
{
spi_transaction_t end_t = {
.cmd = get_hd_command(SPI_CMD_HD_INT0 + int_n, flags),
.flags = flags,
};
return spi_device_transmit(spi, &end_t);
}
//------------------------------------ APPEND MODE ----------------------------------//
static uint32_t essl_spi_get_rx_data_size(void *arg);
static esp_err_t essl_spi_update_rx_data_size(void *arg, uint32_t wait_ms);
static uint32_t essl_spi_get_tx_buffer_num(void *arg);
static esp_err_t essl_spi_update_tx_buffer_num(void *arg, uint32_t wait_ms);
esp_err_t essl_spi_init_dev(essl_handle_t *out_handle, const essl_spi_config_t *init_config)
{
ESP_RETURN_ON_FALSE(init_config->spi, ESP_ERR_INVALID_STATE, TAG, "Check SPI initialization first");
ESP_RETURN_ON_FALSE(init_config->tx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
ESP_RETURN_ON_FALSE(init_config->rx_sync_reg <= (SOC_SPI_MAXIMUM_BUFFER_SIZE - 1) * 4, ESP_ERR_INVALID_ARG, TAG, "GPSPI supports %d-byte-width internal registers", SOC_SPI_MAXIMUM_BUFFER_SIZE);
ESP_RETURN_ON_FALSE(init_config->tx_sync_reg != init_config->rx_sync_reg, ESP_ERR_INVALID_ARG, TAG, "Should use different word of registers for synchronization");
essl_spi_context_t *context = calloc(1, sizeof(essl_spi_context_t));
essl_dev_t *dev = calloc(1, sizeof(essl_dev_t));
if (!context || !dev) {
free(context);
free(dev);
return ESP_ERR_NO_MEM;
}
*context = (essl_spi_context_t) {
.spi = *init_config->spi,
.master_out.tx_buffer_size = init_config->tx_buf_size,
.master_out.tx_sync_reg = init_config->tx_sync_reg,
.master_in.rx_sync_reg = init_config->rx_sync_reg
};
*dev = ESSL_SPI_DEFAULT_DEV_FUNC();
dev->args = context;
*out_handle = dev;
return ESP_OK;
}
esp_err_t essl_spi_deinit_dev(essl_handle_t handle)
{
ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, TAG, "ESSL SPI is not in use");
free(handle->args);
free(handle);
return ESP_OK;
}
void essl_spi_reset_cnt(void *arg)
{
essl_spi_context_t *ctx = arg;
if (ctx) {
ctx->master_out.sent_buf_num = 0;
ctx->master_in.received_bytes = 0;
}
}
//------------------------------------ RX ----------------------------------//
esp_err_t essl_spi_read_reg(void *arg, uint8_t addr, uint8_t *out_value, uint32_t wait_ms)
{
essl_spi_context_t *ctx = arg;
ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
uint8_t reserved_1_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_out.tx_sync_reg : ctx->master_in.rx_sync_reg;
uint8_t reserved_1_tail = reserved_1_head + 3;
uint8_t reserved_2_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_in.rx_sync_reg : ctx->master_out.tx_sync_reg;
uint8_t reserved_2_tail = reserved_2_head + 3;
ESP_RETURN_ON_FALSE(addr < reserved_1_head || (addr > reserved_1_tail && addr < reserved_2_head) || addr > reserved_2_tail, ESP_ERR_INVALID_ARG, TAG, "Invalid address");
return essl_spi_rdbuf(ctx->spi, out_value, addr, sizeof(uint8_t), 0);
}
static uint32_t essl_spi_get_rx_data_size(void *arg)
{
essl_spi_context_t *ctx = arg;
ESP_LOGV(TAG, "slave tx buffer: %d bytes, master has read: %d bytes", ctx->master_in.slave_tx_bytes, ctx->master_in.received_bytes);
return ctx->master_in.slave_tx_bytes - ctx->master_in.received_bytes;
}
static esp_err_t essl_spi_update_rx_data_size(void *arg, uint32_t wait_ms)
{
essl_spi_context_t *ctx = arg;
uint32_t updated_size = 0;
uint32_t previous_size = 0;
esp_err_t ret;
ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&previous_size, ctx->master_in.rx_sync_reg, sizeof(uint32_t), 0);
if (ret != ESP_OK) {
return ret;
}
/**
* Read until the last 2 reading result are same. Reason:
* SPI transaction is carried on per 1 Byte. So when Master is reading the shared register, if the
* register value is changed by Slave at this time, Master may get wrong data.
*/
while (1) {
ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&updated_size, ctx->master_in.rx_sync_reg, sizeof(uint32_t), 0);
if (ret != ESP_OK) {
return ret;
}
if (updated_size == previous_size) {
ctx->master_in.slave_tx_bytes = updated_size;
ESP_LOGV(TAG, "updated: slave prepared tx buffer is: %d bytes", (unsigned int)updated_size);
return ret;
}
previous_size = updated_size;
}
}
esp_err_t essl_spi_get_packet(void *arg, void *out_data, size_t size, uint32_t wait_ms)
{
ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
if (!esp_ptr_dma_capable(out_data) || ((intptr_t)out_data % 4) != 0) {
return ESP_ERR_INVALID_ARG;
}
essl_spi_context_t *ctx = arg;
esp_err_t ret;
if (essl_spi_get_rx_data_size(arg) < size) {
/**
* For realistic situation, usually there will be a large overhead (Slave will load large amount of data),
* so here we only update the Slave's TX size when the last-updated size is smaller than what Master requires.
*/
ret = essl_spi_update_rx_data_size(arg, wait_ms);
if (ret != ESP_OK) {
return ret;
}
//Slave still did not load enough size of buffer
if (essl_spi_get_rx_data_size(arg) < size) {
ESP_LOGV(TAG, "slave buffer: %d is not enough, %d is required", ctx->master_in.slave_tx_bytes, ctx->master_in.received_bytes + size);
return ESP_ERR_NOT_FOUND;
}
}
ESP_LOGV(TAG, "get_packet: size to read is: %d", size);
ret = essl_spi_rddma_seg(ctx->spi, out_data, size, 0);
if (ret != ESP_OK) {
return ret;
}
ctx->master_in.received_bytes += size;
return ESP_OK;
}
//------------------------------------ TX ----------------------------------//
esp_err_t essl_spi_write_reg(void *arg, uint8_t addr, uint8_t value, uint8_t *out_value, uint32_t wait_ms)
{
essl_spi_context_t *ctx = arg;
ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
uint8_t reserved_1_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_out.tx_sync_reg : ctx->master_in.rx_sync_reg;
uint8_t reserved_1_tail = reserved_1_head + 3;
uint8_t reserved_2_head = ctx->master_out.tx_sync_reg < ctx->master_in.rx_sync_reg ? ctx->master_in.rx_sync_reg : ctx->master_out.tx_sync_reg;
uint8_t reserved_2_tail = reserved_2_head + 3;
ESP_RETURN_ON_FALSE(addr < reserved_1_head || (addr > reserved_1_tail && addr < reserved_2_head) || addr > reserved_2_tail, ESP_ERR_INVALID_ARG, TAG, "Invalid address");
ESP_RETURN_ON_FALSE(out_value == NULL, ESP_ERR_NOT_SUPPORTED, TAG, "This feature is not supported");
return essl_spi_wrbuf(ctx->spi, &value, addr, sizeof(uint8_t), 0);
}
static uint32_t essl_spi_get_tx_buffer_num(void *arg)
{
essl_spi_context_t *ctx = arg;
ESP_LOGV(TAG, "slave rx buffer: %d, master has sent: %d", ctx->master_out.slave_rx_buf_num, ctx->master_out.sent_buf_num);
return ctx->master_out.slave_rx_buf_num - ctx->master_out.sent_buf_num;
}
static esp_err_t essl_spi_update_tx_buffer_num(void *arg, uint32_t wait_ms)
{
essl_spi_context_t *ctx = arg;
uint32_t updated_num = 0;
uint32_t previous_size = 0;
esp_err_t ret;
ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&previous_size, ctx->master_out.tx_sync_reg, sizeof(uint32_t), 0);
if (ret != ESP_OK) {
return ret;
}
/**
* Read until the last 2 reading result are same. Reason:
* SPI transaction is carried on per 1 Byte. So when Master is reading the shared register, if the
* register value is changed by Slave at this time, Master may get wrong data.
*/
while (1) {
ret = essl_spi_rdbuf_polling(ctx->spi, (uint8_t *)&updated_num, ctx->master_out.tx_sync_reg, sizeof(uint32_t), 0);
if (ret != ESP_OK) {
return ret;
}
if (updated_num == previous_size) {
ctx->master_out.slave_rx_buf_num = updated_num;
ESP_LOGV(TAG, "updated: slave prepared rx buffer: %d", (unsigned int)updated_num);
return ret;
}
previous_size = updated_num;
}
}
esp_err_t essl_spi_send_packet(void *arg, const void *data, size_t size, uint32_t wait_ms)
{
ESP_RETURN_ON_FALSE(arg, ESP_ERR_INVALID_STATE, TAG, "Check ESSL SPI initialization first");
if (!esp_ptr_dma_capable(data)) {
return ESP_ERR_INVALID_ARG;
}
essl_spi_context_t *ctx = arg;
esp_err_t ret;
uint32_t buf_num_to_use = (size + ctx->master_out.tx_buffer_size - 1) / ctx->master_out.tx_buffer_size;
if (essl_spi_get_tx_buffer_num(arg) < buf_num_to_use) {
/**
* For realistic situation, usually there will be a large overhead (Slave will load enough number of RX buffers),
* so here we only update the Slave's RX buffer number when the last-updated number is smaller than what Master requires.
*/
ret = essl_spi_update_tx_buffer_num(arg, wait_ms);
if (ret != ESP_OK) {
return ret;
}
//Slave still did not load a sufficient amount of buffers
if (essl_spi_get_tx_buffer_num(arg) < buf_num_to_use) {
ESP_LOGV(TAG, "slave buffer: %"PRIu32" is not enough, %"PRIu32" is required", (uint32_t)ctx->master_out.slave_rx_buf_num, (uint32_t)ctx->master_out.sent_buf_num + buf_num_to_use);
return ESP_ERR_NOT_FOUND;
}
}
ESP_LOGV(TAG, "send_packet: size to write is: %zu", size);
ret = essl_spi_wrdma_seg(ctx->spi, data, size, 0);
if (ret != ESP_OK) {
return ret;
}
ctx->master_out.sent_buf_num += buf_num_to_use;
return essl_spi_wrdma_done(ctx->spi, 0);
}

224
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h
View File

@@ -1,224 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
struct essl_dev_t;
/// Handle of an ESSL device
typedef struct essl_dev_t *essl_handle_t;
/**
* @brief Initialize the slave.
*
* @param handle Handle of an ESSL device.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
* @return
* - ESP_OK: If success
* - ESP_ERR_NOT_SUPPORTED: Current device does not support this function.
* - Other value returned from lower layer `init`.
*/
esp_err_t essl_init(essl_handle_t handle, uint32_t wait_ms);
/** Wait for interrupt of an ESSL slave device.
*
* @param handle Handle of an ESSL device.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: If success
* - ESP_ERR_NOT_SUPPORTED: Current device does not support this function.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_wait_for_ready(essl_handle_t handle, uint32_t wait_ms);
/** Get buffer num for the host to send data to the slave. The buffers are size of ``buffer_size``.
*
* @param handle Handle of a ESSL device.
* @param out_tx_num Output of buffer num that host can send data to ESSL slave.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: Success
* - ESP_ERR_NOT_SUPPORTED: This API is not supported in this mode
* - One of the error codes from SDMMC/SPI host controller
*/
esp_err_t essl_get_tx_buffer_num(essl_handle_t handle, uint32_t *out_tx_num, uint32_t wait_ms);
/** Get the size, in bytes, of the data that the ESSL slave is ready to send
*
* @param handle Handle of an ESSL device.
* @param out_rx_size Output of data size to read from slave, in bytes
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: Success
* - ESP_ERR_NOT_SUPPORTED: This API is not supported in this mode
* - One of the error codes from SDMMC/SPI host controller
*/
esp_err_t essl_get_rx_data_size(essl_handle_t handle, uint32_t *out_rx_size, uint32_t wait_ms);
/** Reset the counters of this component. Usually you don't need to do this unless you know the slave is reset.
*
* @param handle Handle of an ESSL device.
*
* @return
* - ESP_OK: Success
* - ESP_ERR_NOT_SUPPORTED: This API is not supported in this mode
* - ESP_ERR_INVALID_ARG: Invalid argument, handle is not init.
*/
esp_err_t essl_reset_cnt(essl_handle_t handle);
/** Send a packet to the ESSL Slave. The Slave receives the packet into buffers whose size is ``buffer_size`` (configured during initialization).
*
* @param handle Handle of an ESSL device.
* @param start Start address of the packet to send
* @param length Length of data to send, if the packet is over-size, the it will be divided into blocks and hold into different buffers automatically.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG: Invalid argument, handle is not init or other argument is not valid.
* - ESP_ERR_TIMEOUT: No buffer to use, or error ftrom SDMMC host controller.
* - ESP_ERR_NOT_FOUND: Slave is not ready for receiving.
* - ESP_ERR_NOT_SUPPORTED: This API is not supported in this mode
* - One of the error codes from SDMMC/SPI host controller.
*/
esp_err_t essl_send_packet(essl_handle_t handle, const void *start, size_t length, uint32_t wait_ms);
/** Get a packet from ESSL slave.
*
* @param handle Handle of an ESSL device.
* @param[out] out_data Data output address
* @param size The size of the output buffer, if the buffer is smaller than the size of data to receive from slave, the driver returns ``ESP_ERR_NOT_FINISHED``
* @param[out] out_length Output of length the data actually received from slave.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK Success: All the data has been read from the slave.
* - ESP_ERR_INVALID_ARG: Invalid argument, The handle is not initialized or the other arguments are invalid.
* - ESP_ERR_NOT_FINISHED: Read was successful, but there is still data remaining.
* - ESP_ERR_NOT_FOUND: Slave is not ready to send data.
* - ESP_ERR_NOT_SUPPORTED: This API is not supported in this mode
* - One of the error codes from SDMMC/SPI host controller.
*/
esp_err_t essl_get_packet(essl_handle_t handle, void *out_data, size_t size, size_t *out_length, uint32_t wait_ms);
/** Write general purpose R/W registers (8-bit) of ESSL slave.
*
* @param handle Handle of an ESSL device.
* @param addr Address of register to write. For SDIO, valid address: 0-59. For SPI, see ``essl_spi.h``
* @param value Value to write to the register.
* @param value_o Output of the returned written value.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @note sdio 28-31 are reserved, the lower API helps to skip.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC/SPI host controller
*/
esp_err_t essl_write_reg(essl_handle_t handle, uint8_t addr, uint8_t value, uint8_t *value_o, uint32_t wait_ms);
/** Read general purpose R/W registers (8-bit) of ESSL slave.
*
* @param handle Handle of a ``essl`` device.
* @param add Address of register to read. For SDIO, Valid address: 0-27, 32-63 (28-31 reserved, return interrupt bits on read). For SPI, see ``essl_spi.h``
* @param value_o Output value read from the register.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC/SPI host controller
*/
esp_err_t essl_read_reg(essl_handle_t handle, uint8_t add, uint8_t *value_o, uint32_t wait_ms);
/** wait for an interrupt of the slave
*
* @param handle Handle of an ESSL device.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: If interrupt is triggered.
* - ESP_ERR_NOT_SUPPORTED: Current device does not support this function.
* - ESP_ERR_TIMEOUT: No interrupts before timeout.
*/
esp_err_t essl_wait_int(essl_handle_t handle, uint32_t wait_ms);
/** Clear interrupt bits of ESSL slave. All the bits set in the mask will be cleared, while other bits will stay the same.
*
* @param handle Handle of an ESSL device.
* @param intr_mask Mask of interrupt bits to clear.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: Success
* - ESP_ERR_NOT_SUPPORTED: Current device does not support this function.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_clear_intr(essl_handle_t handle, uint32_t intr_mask, uint32_t wait_ms);
/** Get interrupt bits of ESSL slave.
*
* @param handle Handle of an ESSL device.
* @param intr_raw Output of the raw interrupt bits. Set to NULL if only masked bits are read.
* @param intr_st Output of the masked interrupt bits. set to NULL if only raw bits are read.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: Success
* - ESP_INVALID_ARG: If both ``intr_raw`` and ``intr_st`` are NULL.
* - ESP_ERR_NOT_SUPPORTED: Current device does not support this function.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_get_intr(essl_handle_t handle, uint32_t *intr_raw, uint32_t *intr_st, uint32_t wait_ms);
/** Set interrupt enable bits of ESSL slave. The slave only sends interrupt on the line when there is a bit both the raw status and the enable are set.
*
* @param handle Handle of an ESSL device.
* @param ena_mask Mask of the interrupt bits to enable.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: Success
* - ESP_ERR_NOT_SUPPORTED: Current device does not support this function.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_set_intr_ena(essl_handle_t handle, uint32_t ena_mask, uint32_t wait_ms);
/** Get interrupt enable bits of ESSL slave.
*
* @param handle Handle of an ESSL device.
* @param ena_mask_o Output of interrupt bit enable mask.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_get_intr_ena(essl_handle_t handle, uint32_t *ena_mask_o, uint32_t wait_ms);
/** Send interrupts to slave. Each bit of the interrupt will be triggered.
*
* @param handle Handle of an ESSL device.
* @param intr_mask Mask of interrupt bits to send to slave.
* @param wait_ms Millisecond to wait before timeout, will not wait at all if set to 0-9.
*
* @return
* - ESP_OK: Success
* - ESP_ERR_NOT_SUPPORTED: Current device does not support this function.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_send_slave_intr(essl_handle_t handle, uint32_t intr_mask, uint32_t wait_ms);
#ifdef __cplusplus
}
#endif

249
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h
View File

@@ -1,249 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// ESP SDIO slave link used by the ESP host to communicate with ESP SDIO slave.
#pragma once
#include "esp_err.h"
#include "driver/sdmmc_types.h"
#include "driver/sdmmc_host.h"
#include "esp_serial_slave_link/essl.h"
#include "essl_sdio_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Configuration for the ESSL SDIO device
typedef struct {
sdmmc_card_t *card; ///< The initialized sdmmc card pointer of the slave.
int recv_buffer_size; ///< The pre-negotiated recv buffer size used by both the host and the slave.
} essl_sdio_config_t;
/**
* @brief Initialize the ESSL SDIO device and get its handle.
*
* @param out_handle Output of the handle.
* @param config Configuration for the ESSL SDIO device.
* @return
* - ESP_OK: on success
* - ESP_ERR_NO_MEM: memory exhausted.
*/
esp_err_t essl_sdio_init_dev(essl_handle_t *out_handle, const essl_sdio_config_t *config);
/**
* @brief Deinitialize and free the space used by the ESSL SDIO device.
*
* @param handle Handle of the ESSL SDIO device to deinit.
* @return
* - ESP_OK: on success
* - ESP_ERR_INVALID_ARG: wrong handle passed
*/
esp_err_t essl_sdio_deinit_dev(essl_handle_t handle);
//Please call `essl_` functions without `sdio` instead of calling these functions directly.
/** @cond */
/**
* SDIO Initialize process of an ESSL SDIO slave device.
*
* @param arg Context of the ``essl`` component. Send to other functions later.
* @param wait_ms Time to wait before operation is done, in ms.
*
* @return
* - ESP_OK if success
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_init(void *arg, uint32_t wait_ms);
/**
* Wait for interrupt of an ESSL SDIO slave device.
*
* @param arg Context of the ``essl`` component.
* @param wait_ms Time to wait before operation is done, in ms.
*
* @return
* - ESP_OK if success
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_wait_for_ready(void *arg, uint32_t wait_ms);
/**
* Get buffer num for the host to send data to the slave. The buffers are size of ``buffer_size``.
*
* @param arg Context of the component.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC host controller
*/
uint32_t essl_sdio_get_tx_buffer_num(void *arg);
/** Get amount of data the ESSL SDIO slave preparing to send to host.
*
* @param arg Context of the component.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC host controller
*/
uint32_t essl_sdio_get_rx_data_size(void *arg);
/**
* Send a packet to the ESSL SDIO slave. The slave receive the packet into buffers whose size is ``buffer_size`` in the arg.
*
* @param arg Context of the component.
* @param start Start address of the packet to send
* @param length Length of data to send, if the packet is over-size, the it will be divided into blocks and hold into different buffers automatically.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - ESP_ERR_TIMEOUT No buffer to use, or error ftrom SDMMC host controller
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_send_packet(void *arg, const void *start, size_t length, uint32_t wait_ms);
/**
* Get a packet from an ESSL SDIO slave.
*
* @param arg Context of the component.
* @param[out] out_data Data output address
* @param size The size of the output buffer, if the buffer is smaller than the size of data to receive from slave, the driver returns ``ESP_ERR_NOT_FINISHED``
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success, all the data are read from the slave.
* - ESP_ERR_NOT_FINISHED Read success, while there're data remaining.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_get_packet(void *arg, void *out_data, size_t size, uint32_t wait_ms);
/**
* Wait for the interrupt from the SDIO slave.
*
* @param arg Context of the component.
* @param wait_ms Time to wait before timeout, in ms.
* @return
* - ESP_ERR_NOT_SUPPORTED: if the interrupt line is not initialized properly.
* - ESP_OK: if interrupt happened
* - ESP_ERR_TIMEOUT: if timeout before interrupt happened.
* - or other values returned from the `io_int_wait` member of the `card->host` structure.
*/
esp_err_t essl_sdio_wait_int(void *arg, uint32_t wait_ms);
/**
* Clear interrupt bits of an ESSL SDIO slave. All the bits set in the mask will be cleared, while other bits will stay the same.
*
* @param arg Context of the component.
* @param intr_mask Mask of interrupt bits to clear.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_clear_intr(void *arg, uint32_t intr_mask, uint32_t wait_ms);
/**
* Get interrupt bits of an ESSL SDIO slave.
*
* @param arg Context of the component.
* @param intr_raw Output of the raw interrupt bits. Set to NULL if only masked bits are read.
* @param intr_st Output of the masked interrupt bits. set to NULL if only raw bits are read.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - ESP_INVALID_ARG if both ``intr_raw`` and ``intr_st`` are NULL.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_get_intr(void *arg, uint32_t *intr_raw, uint32_t *intr_st, uint32_t wait_ms);
/**
* Set interrupt enable bits of an ESSL SDIO slave. The slave only sends interrupt on the line when there is a bit both the raw status and the enable are set.
*
* @param arg Context of the component.
* @param ena_mask Mask of the interrupt bits to enable.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_set_intr_ena(void *arg, uint32_t ena_mask, uint32_t wait_ms);
/**
* Get interrupt enable bits of an ESSL SDIO slave.
*
* @param arg Context of the component.
* @param ena_mask_o Output of interrupt bit enable mask.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_get_intr_ena(void *arg, uint32_t *ena_mask_o, uint32_t wait_ms);
/**
* Write general purpose R/W registers (8-bit) of an ESSL SDIO slave.
*
* @param arg Context of the component.
* @param addr Address of register to write. Valid address: 0-27, 32-63 (28-31 reserved).
* @param value Value to write to the register.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Address not valid.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_write_reg(void *arg, uint8_t addr, uint8_t value, uint8_t *value_o, uint32_t wait_ms);
/**
* Read general purpose R/W registers (8-bit) of an ESSL SDIO slave.
*
* @param arg Context of the component.
* @param add Address of register to read. Valid address: 0-27, 32-63 (28-31 reserved, return interrupt bits on read).
* @param value Output value read from the register.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Address not valid.
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_read_reg(void *arg, uint8_t add, uint8_t *value_o, uint32_t wait_ms);
/**
* Send interrupts to slave. Each bit of the interrupt will be triggered.
*
* @param arg Context of the component.
* @param intr_mask Mask of interrupt bits to send to slave.
* @param wait_ms Time to wait before timeout, in ms.
*
* @return
* - ESP_OK Success
* - One of the error codes from SDMMC host controller
*/
esp_err_t essl_sdio_send_slave_intr(void *arg, uint32_t intr_mask, uint32_t wait_ms);
/**
* @brief Reset the counter on the host side.
*
* @note Only call when you know the slave has reset its counter, or there will be inconsistent between the master and the slave.
*
* @param arg Context of the component.
*/
void essl_sdio_reset_cnt(void *arg);
/** @endcond */
#ifdef __cplusplus
}
#endif

30
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio_defs.h
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* This file contains SDIO Slave hardware specific requirements
*/
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
//interrupts
uint32_t new_packet_intr_mask;
} essl_sdio_def_t;
/// Definitions of ESP32 SDIO Slave hardware
extern essl_sdio_def_t ESSL_SDIO_DEF_ESP32;
/// Definitions of ESP32C6 SDIO Slave hardware
extern essl_sdio_def_t ESSL_SDIO_DEF_ESP32C6;
#ifdef __cplusplus
}
#endif

312
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_err.h"
#include "driver/spi_master.h"
#include "esp_serial_slave_link/essl.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Configuration of ESSL SPI device
typedef struct {
spi_device_handle_t *spi; ///< Pointer to SPI device handle.
uint32_t tx_buf_size; ///< The pre-negotiated Master TX buffer size used by both the host and the slave.
uint8_t tx_sync_reg; ///< The pre-negotiated register ID for Master-TX-SLAVE-RX synchronization. 1 word (4 Bytes) will be reserved for the synchronization.
uint8_t rx_sync_reg; ///< The pre-negotiated register ID for Master-RX-Slave-TX synchronization. 1 word (4 Bytes) will be reserved for the synchronization.
} essl_spi_config_t;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// APIs for DMA Append Mode
// This mode has a better performance for continuous Half Duplex SPI transactions.
//
// * You can use the ``essl_spi_init_dev`` and ``essl_spi_deinit_dev`` together with APIs in ``essl.h`` to communicate
// with ESP SPI Slaves in Half Duplex DMA Append Mode. See example for SPI SLAVE HALFDUPLEX APPEND MODE.
// * You can also use the following APIs to create your own logic.
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/**
* @brief Initialize the ESSL SPI device function list and get its handle
*
* @param[out] out_handle Output of the handle
* @param init_config Configuration for the ESSL SPI device
* @return
* - ESP_OK: On success
* - ESP_ERR_NO_MEM: Memory exhausted
* - ESP_ERR_INVALID_STATE: SPI driver is not initialized
* - ESP_ERR_INVALID_ARG: Wrong register ID
*/
esp_err_t essl_spi_init_dev(essl_handle_t *out_handle, const essl_spi_config_t *init_config);
/**
* @brief Deinitialize the ESSL SPI device and free the memory used by the device
*
* @param handle Handle of the ESSL SPI device
* @return
* - ESP_OK: On success
* - ESP_ERR_INVALID_STATE: ESSL SPI is not in use
*/
esp_err_t essl_spi_deinit_dev(essl_handle_t handle);
/**
* @brief Read from the shared registers
*
* @note The registers for Master/Slave synchronization are reserved. Do not use them. (see `rx_sync_reg` in `essl_spi_config_t`)
*
* @param arg Context of the component. (Member ``arg`` from ``essl_handle_t``)
* @param addr Address of the shared registers. (Valid: 0 ~ SOC_SPI_MAXIMUM_BUFFER_SIZE, registers for M/S sync are reserved, see note1).
* @param[out] out_value Read buffer for the shared registers.
* @param wait_ms Time to wait before timeout (reserved for future use, user should set this to 0).
* @return
* - ESP_OK: success
* - ESP_ERR_INVALID_STATE: ESSL SPI has not been initialized.
* - ESP_ERR_INVALID_ARG: The address argument is not valid. See note 1.
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_read_reg(void *arg, uint8_t addr, uint8_t *out_value, uint32_t wait_ms);
/**
* @brief Get a packet from Slave
*
* @param arg Context of the component. (Member ``arg`` from ``essl_handle_t``)
* @param[out] out_data Output data address
* @param size The size of the output data.
* @param wait_ms Time to wait before timeout (reserved for future use, user should set this to 0).
* @return
* - ESP_OK: On Success
* - ESP_ERR_INVALID_STATE: ESSL SPI has not been initialized.
* - ESP_ERR_INVALID_ARG: The output data address is neither DMA capable nor 4 byte-aligned
* - ESP_ERR_INVALID_SIZE: Master requires ``size`` bytes of data but Slave did not load enough bytes.
*/
esp_err_t essl_spi_get_packet(void *arg, void *out_data, size_t size, uint32_t wait_ms);
/**
* @brief Write to the shared registers
*
* @note The registers for Master/Slave synchronization are reserved. Do not use them. (see `tx_sync_reg` in `essl_spi_config_t`)
* @note Feature of checking the actual written value (``out_value``) is not supported.
*
* @param arg Context of the component. (Member ``arg`` from ``essl_handle_t``)
* @param addr Address of the shared registers. (Valid: 0 ~ SOC_SPI_MAXIMUM_BUFFER_SIZE, registers for M/S sync are reserved, see note1)
* @param value Buffer for data to send, should be align to 4.
* @param[out] out_value Not supported, should be set to NULL.
* @param wait_ms Time to wait before timeout (reserved for future use, user should set this to 0).
* @return
* - ESP_OK: success
* - ESP_ERR_INVALID_STATE: ESSL SPI has not been initialized.
* - ESP_ERR_INVALID_ARG: The address argument is not valid. See note 1.
* - ESP_ERR_NOT_SUPPORTED: Should set ``out_value`` to NULL. See note 2.
* - or other return value from :cpp:func:`spi_device_transmit`.
*
*/
esp_err_t essl_spi_write_reg(void *arg, uint8_t addr, uint8_t value, uint8_t *out_value, uint32_t wait_ms);
/**
* @brief Send a packet to Slave
*
* @param arg Context of the component. (Member ``arg`` from ``essl_handle_t``)
* @param data Address of the data to send
* @param size Size of the data to send.
* @param wait_ms Time to wait before timeout (reserved for future use, user should set this to 0).
* @return
* - ESP_OK: On success
* - ESP_ERR_INVALID_STATE: ESSL SPI has not been initialized.
* - ESP_ERR_INVALID_ARG: The data address is not DMA capable
* - ESP_ERR_INVALID_SIZE: Master will send ``size`` bytes of data but Slave did not load enough RX buffer
*/
esp_err_t essl_spi_send_packet(void *arg, const void *data, size_t size, uint32_t wait_ms);
/**
* @brief Reset the counter in Master context
*
* @note Shall only be called if the slave has reset its counter. Else, Slave and Master would be desynchronized
*
* @param arg Context of the component. (Member ``arg`` from ``essl_handle_t``)
*/
void essl_spi_reset_cnt(void *arg);
////////////////////////////////////////////////////////////////////////////////
// Basic commands to communicate with the SPI Slave HD on ESP32-S2
////////////////////////////////////////////////////////////////////////////////
/**
* @brief Read the shared buffer from the slave in ISR way
*
* @note The slave's HW doesn't guarantee the data in one SPI transaction is consistent. It sends data in unit of byte.
* In other words, if the slave SW attempts to update the shared register when a rdbuf SPI transaction is in-flight,
* the data got by the master will be the combination of bytes of different writes of slave SW.
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
* overwritten, even the ``len`` is shorter than a word.
*
* @param spi SPI device handle representing the slave
* @param[out] out_data Buffer for read data, strongly suggested to be in the DRAM and aligned to 4
* @param addr Address of the slave shared buffer
* @param len Length to read
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: on success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags);
/**
* @brief Read the shared buffer from the slave in polling way
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
* overwritten, even the ``len`` is shorter than a word.
*
* @param spi SPI device handle representing the slave
* @param[out] out_data Buffer for read data, strongly suggested to be in the DRAM and aligned to 4
* @param addr Address of the slave shared buffer
* @param len Length to read
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: on success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_rdbuf_polling(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags);
/**
* @brief Write the shared buffer of the slave in ISR way
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
* overwritten, even the ``len`` is shorter than a word.
*
* @param spi SPI device handle representing the slave
* @param data Buffer for data to send, strongly suggested to be in the DRAM
* @param addr Address of the slave shared buffer,
* @param len Length to write
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags);
/**
* @brief Write the shared buffer of the slave in polling way
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
* overwritten, even the ``len`` is shorter than a word.
*
* @param spi SPI device handle representing the slave
* @param data Buffer for data to send, strongly suggested to be in the DRAM
* @param addr Address of the slave shared buffer,
* @param len Length to write
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_polling_transmit`.
*/
esp_err_t essl_spi_wrbuf_polling(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags);
/**
* @brief Receive long buffer in segments from the slave through its DMA.
*
* @note This function combines several :cpp:func:`essl_spi_rddma_seg` and one
* :cpp:func:`essl_spi_rddma_done` at the end. Used when the slave is working in segment mode.
*
* @param spi SPI device handle representing the slave
* @param[out] out_data Buffer to hold the received data, strongly suggested to be in the DRAM and aligned to 4
* @param len Total length of data to receive.
* @param seg_len Length of each segment, which is not larger than the maximum transaction length
* allowed for the spi device. Suggested to be multiples of 4. When set < 0, means send
* all data in one segment (the ``rddma_done`` will still be sent.)
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_rddma(spi_device_handle_t spi, uint8_t *out_data, int len, int seg_len, uint32_t flags);
/**
* @brief Read one data segment from the slave through its DMA.
*
* @note To read long buffer, call :cpp:func:`essl_spi_rddma` instead.
*
* @param spi SPI device handle representing the slave
* @param[out] out_data Buffer to hold the received data. strongly suggested to be in the DRAM and aligned to 4
* @param seg_len Length of this segment
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg_len, uint32_t flags);
/**
* @brief Send the ``rddma_done`` command to the slave. Upon receiving this command, the slave will
* stop sending the current buffer even there are data unsent, and maybe prepare the next buffer to
* send.
*
* @note This is required only when the slave is working in segment mode.
*
* @param spi SPI device handle representing the slave
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags);
/**
* @brief Send long buffer in segments to the slave through its DMA.
*
* @note This function combines several :cpp:func:`essl_spi_wrdma_seg` and one
* :cpp:func:`essl_spi_wrdma_done` at the end. Used when the slave is working in segment mode.
*
* @param spi SPI device handle representing the slave
* @param data Buffer for data to send, strongly suggested to be in the DRAM
* @param len Total length of data to send.
* @param seg_len Length of each segment, which is not larger than the maximum transaction length
* allowed for the spi device. Suggested to be multiples of 4. When set < 0, means send
* all data in one segment (the ``wrdma_done`` will still be sent.)
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len, int seg_len, uint32_t flags);
/**
* @brief Send one data segment to the slave through its DMA.
*
* @note To send long buffer, call :cpp:func:`essl_spi_wrdma` instead.
*
* @param spi SPI device handle representing the slave
* @param data Buffer for data to send, strongly suggested to be in the DRAM
* @param seg_len Length of this segment
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int seg_len, uint32_t flags);
/**
* @brief Send the ``wrdma_done`` command to the slave. Upon receiving this command, the slave will
* stop receiving, process the received data, and maybe prepare the next buffer to receive.
*
* @note This is required only when the slave is working in segment mode.
*
* @param spi SPI device handle representing the slave
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags);
#ifdef __cplusplus
}
#endif

29
components/driver/test_apps/components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
#define CMD_HD_QIO_MODE 0xA0
#define CMD_HD_SEG_END_REG 0x05
#define CMD_HD_EN_QPI_REG 0x06
#define CMD_HD_WR_END_REG 0x07
#define CMD_HD_INT0_REG 0x08
#define CMD_HD_INT1_REG 0x09
#define CMD_HD_INT2_REG 0x0A
#define CMD_HD_EX_QPI_REG 0xDD
#define SPI_SLAVE_HD_BUFFER_SIZE 64

29
components/driver/test_apps/components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h
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@@ -1,29 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
#define CMD_HD_QIO_MODE 0xA0
#define CMD_HD_SEG_END_REG 0x05
#define CMD_HD_EN_QPI_REG 0x06
#define CMD_HD_WR_END_REG 0x07
#define CMD_HD_INT0_REG 0x08
#define CMD_HD_INT1_REG 0x09
#define CMD_HD_INT2_REG 0x0A
#define CMD_HD_EX_QPI_REG 0xDD
#define SPI_SLAVE_HD_BUFFER_SIZE 64

29
components/driver/test_apps/components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h
View File

@@ -1,29 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
#define CMD_HD_QIO_MODE 0xA0
#define CMD_HD_SEG_END_REG 0x05
#define CMD_HD_EN_QPI_REG 0x06
#define CMD_HD_WR_END_REG 0x07
#define CMD_HD_INT0_REG 0x08
#define CMD_HD_INT1_REG 0x09
#define CMD_HD_INT2_REG 0x0A
#define CMD_HD_EX_QPI_REG 0xDD
#define SPI_SLAVE_HD_BUFFER_SIZE 72

29
components/driver/test_apps/components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h
View File

@@ -1,29 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// NOTE: From the view of master
#define CMD_HD_WRBUF_REG 0x01
#define CMD_HD_RDBUF_REG 0x02
#define CMD_HD_WRDMA_REG 0x03
#define CMD_HD_RDDMA_REG 0x04
#define CMD_HD_ONEBIT_MODE 0x00
#define CMD_HD_DOUT_MODE 0x10
#define CMD_HD_QOUT_MODE 0x20
#define CMD_HD_DIO_MODE 0x50
#define CMD_HD_QIO_MODE 0xA0
#define CMD_HD_SEG_END_REG 0x05
#define CMD_HD_EN_QPI_REG 0x06
#define CMD_HD_WR_END_REG 0x07
#define CMD_HD_INT0_REG 0x08
#define CMD_HD_INT1_REG 0x09
#define CMD_HD_INT2_REG 0x0A
#define CMD_HD_EX_QPI_REG 0xDD
#define SPI_SLAVE_HD_BUFFER_SIZE 64

1
components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/idf_component.yml
View File

@@ -1,2 +1,3 @@
dependencies: dependencies:
ccomp_timer: "^1.0.0" ccomp_timer: "^1.0.0"
espressif/esp_serial_slave_link: "^1.1.0"

3
components/esp_driver_spi/test_apps/param/main/idf_component.yml
View File

@@ -5,5 +5,4 @@ dependencies:
path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils
spi_bench_mark: spi_bench_mark:
path: ${IDF_PATH}/components/esp_driver_spi/test_apps/components/spi_bench_mark path: ${IDF_PATH}/components/esp_driver_spi/test_apps/components/spi_bench_mark
esp_serial_slave_link: espressif/esp_serial_slave_link: "^1.1.0"
path: ${IDF_PATH}/components/driver/test_apps/components/esp_serial_slave_link

3
components/esp_driver_spi/test_apps/slave_hd/main/idf_component.yml
View File

@@ -3,5 +3,4 @@ dependencies:
path: ${IDF_PATH}/tools/unit-test-app/components/test_utils path: ${IDF_PATH}/tools/unit-test-app/components/test_utils
test_driver_utils: test_driver_utils:
path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils
esp_serial_slave_link: espressif/esp_serial_slave_link: "^1.1.0"
path: ${IDF_PATH}/components/driver/test_apps/components/esp_serial_slave_link

4
docs/component_info_ignore_file.txt
View File

@@ -8,10 +8,6 @@ components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h
components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h
components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h
components/ulp/lp_core/lp_core/include/ulp_lp_core_spi.h components/ulp/lp_core/lp_core/include/ulp_lp_core_spi.h
# ESSL headers do not belong to any IDF component, in a user project it will come from a managed component
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h
components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h
# ESP-TEE header files # ESP-TEE header files
components/esp_tee/subproject/components/tee_sec_storage/include/esp_tee_sec_storage.h components/esp_tee/subproject/components/tee_sec_storage/include/esp_tee_sec_storage.h
components/esp_tee/subproject/components/tee_attestation/esp_tee_attestation.h components/esp_tee/subproject/components/tee_attestation/esp_tee_attestation.h

1
docs/docs_not_updated/esp32c5.txt
View File

@@ -33,5 +33,4 @@ api-reference/system/sleep_modes.rst
api-reference/system/power_management.rst api-reference/system/power_management.rst
api-reference/system/inc/power_management_esp32c5.rst api-reference/system/inc/power_management_esp32c5.rst
api-reference/index.rst api-reference/index.rst
api-reference/protocols/esp_serial_slave_link.rst
api-reference/protocols/esp_crt_bundle.rst api-reference/protocols/esp_crt_bundle.rst

2
docs/docs_not_updated/esp32c61.txt
View File

@@ -77,9 +77,7 @@ api-reference/system/mm.rst
api-reference/error-codes.rst api-reference/error-codes.rst
api-reference/index.rst api-reference/index.rst
api-reference/protocols/icmp_echo.rst api-reference/protocols/icmp_echo.rst
api-reference/protocols/esp_serial_slave_link.rst
api-reference/protocols/mqtt.rst api-reference/protocols/mqtt.rst
api-reference/protocols/esp_sdio_slave_protocol.rst
api-reference/protocols/modbus.rst api-reference/protocols/modbus.rst
api-reference/protocols/mdns.rst api-reference/protocols/mdns.rst
api-reference/protocols/index.rst api-reference/protocols/index.rst

2
docs/docs_not_updated/esp32h21.txt
View File

@@ -86,8 +86,6 @@ api-reference/protocols/asio.rst
api-reference/protocols/mbedtls.rst api-reference/protocols/mbedtls.rst
api-reference/protocols/modbus.rst api-reference/protocols/modbus.rst
api-reference/protocols/icmp_echo.rst api-reference/protocols/icmp_echo.rst
api-reference/protocols/esp_serial_slave_link.rst
api-reference/protocols/esp_sdio_slave_protocol.rst
api-reference/protocols/esp_https_server.rst api-reference/protocols/esp_https_server.rst
api-reference/protocols/esp_local_ctrl.rst api-reference/protocols/esp_local_ctrl.rst
api-reference/protocols/esp_tls.rst api-reference/protocols/esp_tls.rst

3
docs/docs_not_updated/esp32h4.txt
View File

@@ -86,12 +86,9 @@ api-reference/protocols/asio.rst
api-reference/protocols/mbedtls.rst api-reference/protocols/mbedtls.rst
api-reference/protocols/modbus.rst api-reference/protocols/modbus.rst
api-reference/protocols/icmp_echo.rst api-reference/protocols/icmp_echo.rst
api-reference/protocols/esp_serial_slave_link.rst
api-reference/protocols/esp_sdio_slave_protocol.rst
api-reference/protocols/esp_https_server.rst api-reference/protocols/esp_https_server.rst
api-reference/protocols/esp_local_ctrl.rst api-reference/protocols/esp_local_ctrl.rst
api-reference/protocols/esp_tls.rst api-reference/protocols/esp_tls.rst
api-reference/protocols/esp_spi_slave_protocol.rst
api-reference/protocols/esp_http_client.rst api-reference/protocols/esp_http_client.rst
api-reference/protocols/mqtt.rst api-reference/protocols/mqtt.rst
api-reference/protocols/esp_http_server.rst api-reference/protocols/esp_http_server.rst

3
docs/doxygen/Doxyfile
View File

@@ -74,9 +74,6 @@ INPUT = \
$(PROJECT_PATH)/components/bt/host/bluedroid/api/include/api/esp_spp_api.h \ $(PROJECT_PATH)/components/bt/host/bluedroid/api/include/api/esp_spp_api.h \
$(PROJECT_PATH)/components/bt/host/nimble/esp-hci/include/esp_nimble_hci.h \ $(PROJECT_PATH)/components/bt/host/nimble/esp-hci/include/esp_nimble_hci.h \
$(PROJECT_PATH)/components/console/esp_console.h \ $(PROJECT_PATH)/components/console/esp_console.h \
$(PROJECT_PATH)/components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h \
$(PROJECT_PATH)/components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h \
$(PROJECT_PATH)/components/driver/test_apps/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h \
$(PROJECT_PATH)/components/efuse/$(IDF_TARGET)/include/esp_efuse_chip.h \ $(PROJECT_PATH)/components/efuse/$(IDF_TARGET)/include/esp_efuse_chip.h \
$(PROJECT_PATH)/components/efuse/include/esp_efuse.h \ $(PROJECT_PATH)/components/efuse/include/esp_efuse.h \
$(PROJECT_PATH)/components/esp_adc/include/esp_adc/adc_cali_scheme.h \ $(PROJECT_PATH)/components/esp_adc/include/esp_adc/adc_cali_scheme.h \

6
docs/en/api-reference/peripherals/sdio_slave.rst
View File

@@ -149,11 +149,11 @@ The SDIO slave driver uses the following terms:
Communication with ESP SDIO Slave Communication with ESP SDIO Slave
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The host should initialize the {IDF_TARGET_NAME} SDIO slave according to the standard SDIO initialization process (Sector 3.1.2 of `SDIO Simplified Specification <https://www.sdcard.org/downloads/pls/pdf/?p=PartE1_SDIO_Simplified_Specification_Ver3.00.jpg&f=PartE1_SDIO_Simplified_Specification_Ver3.00.pdf&e=EN_SSE1>`_), which is described briefly in :ref:`esp_slave_init`. The host should initialize the {IDF_TARGET_NAME} SDIO slave according to the standard SDIO initialization process (Sector 3.1.2 of `SDIO Simplified Specification <https://www.sdcard.org/downloads/pls/pdf/?p=PartE1_SDIO_Simplified_Specification_Ver3.00.jpg&f=PartE1_SDIO_Simplified_Specification_Ver3.00.pdf&e=EN_SSE1>`_), which is described briefly in `ESP SDIO Slave Initialization <https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/sdio_slave_protocol.html#esp-sdio-slave-initialization>`_.
Furthermore, there is an {IDF_TARGET_NAME}-specific upper-level communication protocol built upon the foundation of CMD52/CMD53 to Function 1. Within this particular communication protocol, the master and slave engage in data exchange and communication through the utilization of CMD52/CMD53 commands. For more detailed information, please consult the :ref:`esp_slave_protocol_layer` section. Furthermore, there is an {IDF_TARGET_NAME}-specific upper-level communication protocol built upon the foundation of CMD52/CMD53 to Function 1. Within this particular communication protocol, the master and slave engage in data exchange and communication through the utilization of CMD52/CMD53 commands. For more detailed information, please consult the `ESP SDIO Slave Protocol <https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/sdio_slave_protocol.html#esp-sdio-slave-protocol>`_ section.
There is also a component :doc:`/api-reference/protocols/esp_serial_slave_link` designed for {IDF_TARGET_NAME} master to communicate with {IDF_TARGET_NAME} SDIO slave. See example :example:`peripherals/sdio` when programming your host. There is also a component `ESSL <https://components.espressif.com/components/espressif/esp_serial_slave_link>`_ designed for {IDF_TARGET_NAME} master to communicate with {IDF_TARGET_NAME} SDIO slave. See example :example:`peripherals/sdio` when programming your host.
.. _interrupts: .. _interrupts:

2
docs/en/api-reference/peripherals/spi_slave_hd.rst
View File

@@ -13,7 +13,7 @@ When conducting an SPI transaction, transactions can be classified into several
Protocol Protocol
^^^^^^^^ ^^^^^^^^
About the details of how master should communicate with the SPI Slave, see :doc:`/api-reference/protocols/esp_spi_slave_protocol`. About the details of how master should communicate with the SPI Slave, see `ESP SPI Slave HD Protocol <https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/spi_slave_hd_protocol.html#spi-slave-hd-half-duplex-protocol>`_.
Through these different transactions, the slave provides these services to the master: Through these different transactions, the slave provides these services to the master:

217
docs/en/api-reference/protocols/esp_sdio_slave_protocol.rst
View File

@@ -1,217 +0,0 @@
Communication with ESP SDIO Slave
=================================
:link_to_translation:`zh_CN:[中文]`
This document describes the process of initialization of an ESP SDIO Slave device and then provides details on the ESP SDIO Slave protocol - a non-standard protocol that allows an SDIO Host to communicate with an ESP SDIO slave.
The ESP SDIO Slave protocol was created to implement the communication between SDIO host and slave, because the SDIO specification only shows how to access the custom region of a card (by sending CMD52 and CMD53 to functions 1-7) without any details regarding the underlying hardware implementation.
.. _esp_sdio_slave_caps:
SDIO Slave Capabilities of Espressif Chips
------------------------------------------
The services provided by the SDIO Slave peripheral of the {IDF_TARGET_NAME} chip are listed in the table below:
.. list-table::
:widths: 70 30
:header-rows: 1
* - Services
- {IDF_TARGET_NAME}
* - SDIO slave
- Y
* - :ref:`Tohost intr <esp_sdio_slave_interrupts>`
- 8
* - :ref:`Frhost intr <esp_sdio_slave_interrupts>`
- 8
* - :ref:`TX DMA <esp_sdio_slave_send_fifo>`
- Y
* - :ref:`RX DMA <esp_sdio_slave_rcv_fifo>`
- Y
* - :ref:`Shared registers <esp_sdio_slave_shared_registers>`
- 56\*
\* Not including the interrupt registers
.. _esp_slave_init:
ESP SDIO Slave Initialization
-----------------------------
The host should initialize the {IDF_TARGET_NAME} SDIO slave according to the standard SDIO initialization process (Section 3.1.2 of `SDIO Simplified Specification <https://www.sdcard.org/downloads/pls/>`_). In this specification as well as below, the SDIO slave is called an SDIO/IO card. Here is a brief example of an ESP SDIO Slave initialization process:
1. SDIO reset
CMD52 (Write 0x6 = 0x8)
2. SD reset
CMD0
3. Check whether IO card (optional)
CMD8
4. Send SDIO op cond and wait for card ready
CMD5 arg = 0x00000000
CMD5 arg = 0x00ff8000 (according to the response above, poll until ready)
**Example:**
Arg of R4 after first CMD5 (arg = 0x00000000) is 0xXXFFFF00.
Keep sending CMD5 with arg = 0x00FFFF00 until the R4 shows card ready (arg bit 31 = 1).
5. Set address
CMD3
6. Select card
CMD7 (arg address according to CMD3 response)
**Example:**
Arg of R6 after CMD3 is 0x0001xxxx.
Arg of CMD7 should be 0x00010000.
7. Select 4-bit mode (optional)
CMD52 (Write 0x07 = 0x02)
8. Enable func1
CMD52 (Write 0x02 = 0x02)
9. Enable SDIO interrupt (required if interrupt line (DAT1) is used)
CMD52 (Write 0x04 = 0x03)
10. Set Func0 blocksize (optional, default value is 512 (0x200))
CMD52/53 (Read 0x10 ~ 0x11)
CMD52/53 (Write 0x10 = 0x00)
CMD52/53 (Write 0x11 = 0x02)
CMD52/53 (Read 0x10 ~ 0x11, read to check the final value)
11. Set Func1 blocksize (optional, default value is 512 (0x200))
CMD52/53 (Read 0x110 ~ 0x111)
CMD52/53 (Write 0x110 = 0x00)
CMD52/53 (Write 0x111 = 0x02)
CMD52/53 (Read 0x110 ~ 0x111, read to check the final value)
.. _esp_slave_protocol_layer:
ESP SDIO Slave Protocol
-----------------------
The ESP SDIO Slave protocol is based on the SDIO Specification's I/O Read/Write commands, i.e., CMD52 and CMD53. The protocol offers the following services:
- Sending FIFO and receiving FIFO
- 52 8-bit R/W registers shared by host and slave (For details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *SDIO Slave Controller* > *Register Summary* > SDIO SLC Host registers [`PDF <{IDF_TARGET_TRM_EN_URL}#sdioslave-reg-summ>`__])
- 16 general purpose interrupt sources, 8 from host to slave and 8 from slave to host
To begin communication, the host needs to enable the I/O Function 1 in the slave and access its registers as described below.
Check the code example: :example:`peripherals/sdio`
The :doc:`ESP Serial Slave Link </api-reference/protocols/esp_serial_slave_link>` component implements the logic of this protocol for ESP32 SDIO Host when communicating with an ESP32 SDIO slave.
.. _esp_sdio_slave_shared_registers:
Slave Register Table
^^^^^^^^^^^^^^^^^^^^
32-bit
""""""
- 0x044 (TOKEN_RDATA): in which bit 27-16 holds the number of the receiving buffer.
- 0x058 (INT_ST): holds the interrupt source bits from slave to host.
- 0x060 (PKT_LEN): holds the accumulated data length (in bytes) already read by host plus the data copied to the buffer but yet to be read.
- 0x0D4 (INT_CLR): write 1 to clear interrupt bits corresponding to INT_ST.
- 0x0DC (INT_ENA): mask bits for interrupts from slave to host.
8-bit
"""""
Shared general purpose registers:
- 0x06C-0x077: R/W registers 0-11 shared by slave and host.
- 0x07A-0x07B: R/W registers 14-15 shared by slave and host.
- 0x07E-0x07F: R/W registers 18-19 shared by slave and host.
- 0x088-0x08B: R/W registers 24-27 shared by slave and host.
- 0x09C-0x0BB: R/W registers 32-63 shared by slave and host.
Interrupt Registers:
- 0x08D (SLAVE_INT): bits for host to interrupt slave. auto clear.
FIFO (Sending and Receiving)
""""""""""""""""""""""""""""
0x090 - 0x1F7FF are reserved for FIFOs.
The address of CMD53 is related to the length requested to read from or write to the slave in a single transfer, as demonstrated by the equation below:
*requested length = 0x1F800 - address*
The slave responds to data that has a length equal to the length field of CMD53. In cases where the data is longer than the **requested length**, the data will be zero filled (when sending) or discarded (when receiving). This includes both the block and the byte mode of CMD53.
.. note::
The function number should be set to 1, and OP Code should be set to 1 (for CMD53).
In order to achieve higher efficiency when accessing the FIFO by an arbitrary length, the block and byte modes of CMD53 can be used in combination. For example, given that the block size is set to 512 by default, you can write or get 1031 bytes of data from the FIFO by doing the following:
1. Send CMD53 in block mode, block count = 2 (1024 bytes) to address 0x1F3F9 = 0x1F800 - **1031**.
2. Then send CMD53 in byte mode, byte count = 8 (or 7 if your controller supports that) to address 0x1F7F9 = 0x1F800 - **7**.
.. _esp_sdio_slave_interrupts:
Interrupts
^^^^^^^^^^
SDIO interrupts are "level sensitive". For host interrupts, the slave sends an interrupt by pulling the DAT1 line down at a proper time. The host detects when the interrupt line is pulled down and reads the INT_ST register to determine the source of the interrupt. After that, the host can clear the interrupt bits by writing the ``INT_CLR`` register and process the interrupt. The host can also mask unneeded sources by clearing the bits in the INT_ENA register corresponding to the sources. If all the sources are cleared (or masked), the DAT1 line goes inactive.
On {IDF_TARGET_NAME}, the corresponding ``host_int`` bits are: bit 0 to bit 7.
For slave interrupts, the host sends a transfer to write the ``SLAVE_INT`` register. Once a bit is set to 1, the slave hardware and the driver will detect it and inform the application.
.. _esp_sdio_slave_rcv_fifo:
Receiving FIFO
^^^^^^^^^^^^^^
To write to the slave's receiving FIFO, the host should complete the following steps:
1. **Read the TOKEN1 field (bits 27-16) of the register TOKEN_RDATA (0x044)**. The buffer number remaining is TOKEN1 minus the number of buffers used by host.
2. **Make sure the buffer number is sufficient** (*buffer_size* x *buffer_num* is greater than the data to write, *buffer_size* is pre-defined between the host and the slave before the communication starts). Otherwise, keep returning to step 1 until the buffer size is sufficient.
3. **Write to the FIFO address with CMD53**. Note that the *requested length* should not exceed the length calculated at step 2, and the FIFO address is related to *requested length*.
4. **Calculate used buffers**. Note that a partially-used buffer at the tail is counted as used.
.. _esp_sdio_slave_send_fifo:
Sending FIFO
^^^^^^^^^^^^
To read the slave's sending FIFO, the host should complete the following steps:
1. **Wait for the interrupt line to become active** (optional, low by default).
2. **Read (poll) the interrupt bits in the INT_ST register** to monitor if new packets exist.
3. **If new packets are ready, read the PKT_LEN register**. Before reading the packets, determine the length of data to be read. As the host keeps the length of data already read from the slave, subtract this value from ``PKT_LEN``, the result will be the maximum length of data available for reading. If no data has been added to the sending FIFO yet, wait and poll until the slave is ready and update ``PKT_LEN``.
4. **Read from the FIFO using CMD53**. Note that the **requested length** should not be greater than calculated at Step 3, and the FIFO address is related to **requested length**.
5. **Update the read length**.

168
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@@ -1,168 +0,0 @@
ESP Serial Slave Link
=====================
:link_to_translation:`zh_CN:[中文]`
Overview
--------
Espressif provides several chips that can work as slaves. These slave devices rely on some common buses, and have their own communication protocols over those buses. The ``esp_serial_slave_link`` component is designed for the master to communicate with ESP slave devices through those protocols over the bus drivers.
After an ``esp_serial_slave_link`` device is initialized properly, the application can use it to communicate with the ESP slave devices conveniently.
.. note::
The ESP-IDF component ``esp_serial_slave_link`` has been moved from ESP-IDF since version v5.0 to a separate repository:
* `ESSL component on GitHub <https://github.com/espressif/idf-extra-components/tree/master/esp_serial_slave_link>`__
To add ESSL component in your project, please run ``idf.py add-dependency espressif/esp_serial_slave_link``.
Espressif Device Protocols
--------------------------
For more details about Espressif device protocols, see the following documents.
.. toctree::
:maxdepth: 1
:SOC_SDIO_SLAVE_SUPPORTED: esp_sdio_slave_protocol
esp_spi_slave_protocol
Terminology
-----------
- ESSL: Abbreviation for ESP Serial Slave Link, the component described by this document.
- Master: The device running the ``esp_serial_slave_link`` component.
- ESSL device: a virtual device on the master associated with an ESP slave device. The device context has the knowledge of the slave protocol above the bus, relying on some bus drivers to communicate with the slave.
- ESSL device handle: a handle to ESSL device context containing the configuration, status and data required by the ESSL component. The context stores the driver configurations, communication state, data shared by master and slave, etc.
- The context should be initialized before it is used, and get deinitialized if not used any more. The master application operates on the ESSL device through this handle.
- ESP slave: the slave device connected to the bus, which ESSL component is designed to communicate with.
- Bus: The bus over which the master and the slave communicate with each other.
- Slave protocol: The special communication protocol specified by Espressif HW/SW over the bus.
- TX buffer num: a counter, which is on the slave and can be read by the master, indicates the accumulated buffer numbers that the slave has loaded to the hardware to receive data from the master.
- RX data size: a counter, which is on the slave and can be read by the master, indicates the accumulated data size that the slave has loaded to the hardware to send to the master.
Services Provided by ESP Slave
------------------------------
There are some common services provided by the Espressif slaves:
1. Tohost Interrupts: The slave can inform the master about certain events by the interrupt line. (optional)
2. Frhost Interrupts: The master can inform the slave about certain events.
3. TX FIFO (master to slave): The slave can receive data from the master in units of receiving buffers.
The slave updates the TX buffer num to inform the master how much data it can receive, and the master then read the TX buffer num, and take off the used buffer number to know how many buffers are remaining.
4. RX FIFO (slave to master): The slave can send data in stream to the master. The SDIO slave can also indicate it has new data to send to master by the interrupt line.
The slave updates the RX data size to inform the master how much data it has prepared to send, and then the master read the data size, and take off the data length it has already received to know how many data is remaining.
5. Shared registers: The master can read some part of the registers on the slave, and also write these registers to let the slave read.
.. only:: SOC_SDIO_SLAVE_SUPPORTED
The services provided by the slave depends on the slave's model. See :ref:`esp_sdio_slave_caps` and :ref:`esp_spi_slave_caps` for more details.
.. only:: not SOC_SDIO_SLAVE_SUPPORTED
The services provided by the slave depends on the slave's model. See :ref:`esp_spi_slave_caps` for more details.
Initialization of ESP Serial Slave Link
---------------------------------------
.. _essl_sdio_slave_init:
ESP SDIO Slave
^^^^^^^^^^^^^^
The ESP SDIO slave link (ESSL SDIO) devices relies on the SDMMC component. It includes the usage of communicating with ESP SDIO Slave device via the SDMMC Host or SDSPI Host feature. The ESSL device should be initialized as below:
1. Initialize a SDMMC card (see :doc:`Document of SDMMC driver </api-reference/storage/sdmmc>`) structure.
2. Call :cpp:func:`sdmmc_card_init` to initialize the card.
3. Initialize the ESSL device with :cpp:type:`essl_sdio_config_t`. The ``card`` member should be the :cpp:type:`sdmmc_card_t` got in step 2, and the ``recv_buffer_size`` member should be filled correctly according to pre-negotiated value.
4. Call :cpp:func:`essl_init` to do initialization of the SDIO part.
5. Call :cpp:func:`essl_wait_for_ready` to wait for the slave to be ready.
ESP SPI Slave
^^^^^^^^^^^^^
.. note::
If you are communicating with the ESP SDIO Slave device through SPI interface, you should use the :ref:`SDIO interface <essl_sdio_slave_init>` instead.
Has not been supported yet.
APIs
----
After the initialization process above is performed, you can call the APIs below to make use of the services provided by the slave:
Tohost Interrupts (Optional)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1. Call :cpp:func:`essl_get_intr_ena` to know which events trigger the interrupts to the master.
2. Call :cpp:func:`essl_set_intr_ena` to set the events that trigger interrupts to the master.
3. Call :cpp:func:`essl_wait_int` to wait until interrupt from the slave, or timeout.
4. When interrupt is triggered, call :cpp:func:`essl_get_intr` to know which events are active, and call :cpp:func:`essl_clear_intr` to clear them.
Frhost Interrupts
^^^^^^^^^^^^^^^^^
1. Call :cpp:func:`essl_send_slave_intr` to trigger general purpose interrupt of the slave.
TX FIFO
^^^^^^^
1. Call :cpp:func:`essl_get_tx_buffer_num` to know how many buffers the slave has prepared to receive data from the master. This is optional. The master will poll ``tx_buffer_num`` when it tries to send packets to the slave, until the slave has enough buffer or timeout.
2. Call :cpp:func:`essl_send_packet` to send data to the slave.
RX FIFO
^^^^^^^
1. Call :cpp:func:`essl_get_rx_data_size` to know how many data the slave has prepared to send to the master. This is optional. When the master tries to receive data from the slave, it updates the ``rx_data_size`` for once, if the current ``rx_data_size`` is shorter than the buffer size the master prepared to receive. And it may poll the ``rx_data_size`` if the ``rx_data_size`` keeps 0, until timeout.
2. Call :cpp:func:`essl_get_packet` to receive data from the slave.
Reset Counters (Optional)
^^^^^^^^^^^^^^^^^^^^^^^^^
Call :cpp:func:`essl_reset_cnt` to reset the internal counter if you find the slave has reset its counter.
Application Example
-------------------
The example below shows how {IDF_TARGET_NAME} SDIO host and slave communicate with each other. The host uses the ESSL SDIO:
:example:`peripherals/sdio`
Please refer to the specific example README.md for details.
API Reference
-------------
.. include-build-file:: inc/essl.inc
.. include-build-file:: inc/essl_sdio.inc
.. include-build-file:: inc/essl_spi.inc

168
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@@ -1,168 +0,0 @@
ESP SPI Slave HD (Half Duplex) Mode Protocol
============================================
:link_to_translation:`zh_CN:[中文]`
.. only:: esp32
.. warning::
ESP32 does not support this feature.
.. _esp_spi_slave_caps:
SPI Slave Capabilities of Espressif Chips
-----------------------------------------
+---------+------------+-----------+-----------+------+------+----------------+
| |SPI Slave HD|Tohost intr|Frhost intr|TX DMA|RX DMA|Shared registers|
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32 | N | | | | | |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-S2 | Y(v2) | N | 2 \* | Y | Y | 72 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C3 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-S3 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C2 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C6 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-H2 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-P4 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C5 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C61| Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-H21| Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
Introduction
------------
In the half duplex mode, the master has to use the protocol defined by the slave to communicate with the slave. Each transaction may consist of the following phases (listed by the order they should exist):
- Command: 8-bit, master to slave
This phase determines the rest phases of the transactions. See :ref:`spi_slave_hd_supported_cmds`.
- Address: 8-bit, master to slave, optional
For some commands (WRBUF, RDBUF), this phase specifies the address of the shared register to write to/read from. For other commands with this phase, they are meaningless but still have to exist in the transaction.
.. only:: esp32s2
- Dummy: 8-bit (for 1-bit mode) or 4-bit (for 2/4-bit mode), floating, optional
This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
.. only:: not esp32s2
- Dummy: 8-bit, floating, optional
This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master.
- Data: variable length, the direction is also determined by the command.
This may be a data OUT phase, in which the direction is slave to master, or a data IN phase, in which the direction is master to slave.
The **direction** means which side (master or slave) controls the MOSI, MISO, WP, and HD pins.
Data IO Modes
-------------
In some IO modes, more data wires can be used to send the data. As a result, the SPI clock cycles required for the same amount of data will be less than in the 1-bit mode. For example, in QIO mode, address and data (IN and OUT) should be sent on all 4 data wires (MOSI, MISO, WP, and HD). Here are the modes supported by the ESP32-S2 SPI slave and the wire number (WN) used in corresponding modes.
+-------+------------+------------+--------------+---------+
| Mode | Command WN | Address WN | Dummy cycles | Data WN |
+=======+============+============+==============+=========+
| 1-bit | 1 | 1 | 1 | 1 |
+-------+------------+------------+--------------+---------+
| DOUT | 1 | 1 | 4 | 2 |
+-------+------------+------------+--------------+---------+
| DIO | 1 | 2 | 4 | 2 |
+-------+------------+------------+--------------+---------+
| QOUT | 1 | 1 | 4 | 4 |
+-------+------------+------------+--------------+---------+
| QIO | 1 | 4 | 4 | 4 |
+-------+------------+------------+--------------+---------+
| QPI | 4 | 4 | 4 | 4 |
+-------+------------+------------+--------------+---------+
Normally, which mode is used is determined by the command sent by the master (See :ref:`spi_slave_hd_supported_cmds`), except the QPI mode.
QPI Mode
^^^^^^^^
The QPI mode is a special state of the SPI Slave. The master can send the ENQPI command to put the slave into the QPI mode state. In the QPI mode, the command is also sent in 4-bit, thus it is not compatible with the normal modes. The master should only send QPI commands when the slave is in QPI mode. To exit from the QPI mode, master can send the EXQPI command.
.. _spi_slave_hd_supported_cmds:
Supported Commands
------------------
.. note::
The command name is in a master-oriented direction. For example, WRBUF means master writes the buffer of slave.
+----------+---------------------+---------+----------+----------------------------------------------------------+
| Name | Description | Command | Address | Data |
+==========+=====================+=========+==========+==========================================================+
| WRBUF | Write buffer | 0x01 | Buf addr | master to slave, no longer than buffer size |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| RDBUF | Read buffer | 0x02 | Buf addr | slave to master, no longer than buffer size |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| WRDMA | Write DMA | 0x03 | 8 bits | master to slave, no longer than length provided by slave |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| RDDMA | Read DMA | 0x04 | 8 bits | slave to master, no longer than length provided by slave |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| SEG_DONE | Segments done | 0x05 | - | - |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| ENQPI | Enter QPI mode | 0x06 | - | - |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| WR_DONE | Write segments done | 0x07 | - | - |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| CMD8 | Interrupt | 0x08 | - | - |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| CMD9 | Interrupt | 0x09 | - | - |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| CMDA | Interrupt | 0x0A | - | - |
+----------+---------------------+---------+----------+----------------------------------------------------------+
| EXQPI | Exit QPI mode | 0xDD | - | - |
+----------+---------------------+---------+----------+----------------------------------------------------------+
Moreover, WRBUF, RDBUF, WRDMA, and RDDMA commands have their 2-bit and 4-bit version. To do transactions in 2-bit or 4-bit mode, send the original command ORed by the corresponding command mask below. For example, command 0xA1 means WRBUF in QIO mode.
+-------+------+
| Mode | Mask |
+=======+======+
| 1-bit | 0x00 |
+-------+------+
| DOUT | 0x10 |
+-------+------+
| DIO | 0x50 |
+-------+------+
| QOUT | 0x20 |
+-------+------+
| QIO | 0xA0 |
+-------+------+
| QPI | 0xA0 |
+-------+------+
Segment Transaction Mode
------------------------
Segment transaction mode is the only mode supported by the SPI Slave HD driver for now. In this mode, for a transaction the slave loads onto the DMA, the master is allowed to read or write in segments. In this way, the master does not have to prepare a large buffer as the size of data provided by the slave. After the master finishes reading/writing a buffer, it has to send the corresponding termination command to the slave as a synchronization signal. The slave driver will update new data (if exist) onto the DMA upon seeing the termination command.
The termination command is WR_DONE (0x07) for WRDMA and CMD8 (0x08) for RDDMA.
Here is an example for the flow the master read data from the slave DMA:
1. The slave loads 4092 bytes of data onto the RDDMA.
2. The master do seven RDDMA transactions, each of them is 512 bytes long, and reads the first 3584 bytes from the slave.
3. The master do the last RDDMA transaction of 512 bytes (equal, longer, or shorter than the total length loaded by the slave are all allowed). The first 508 bytes are valid data from the slave, while the last 4 bytes are meaningless bytes.
4. The master sends CMD8 to the slave.
5. The slave loads another 4092 bytes of data onto the RDDMA.
6. The master can start new reading transactions after it sends the CMD8.

1
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View File

@@ -12,7 +12,6 @@ Application Protocols
esp_tls esp_tls
esp_http_client esp_http_client
esp_local_ctrl esp_local_ctrl
esp_serial_slave_link
esp_crt_bundle esp_crt_bundle
esp_http_server esp_http_server
esp_https_server esp_https_server

4
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View File

@@ -109,9 +109,9 @@ Using API with SD Memory Cards
If you want the application to wait until the SDIO interrupt occurs, use :cpp:func:`sdmmc_io_wait_int`. If you want the application to wait until the SDIO interrupt occurs, use :cpp:func:`sdmmc_io_wait_int`.
.. only:: esp32 .. only:: SOC_SDMMC_HOST_SUPPORTED and SOC_SDIO_SLAVE_SUPPORTED
There is a component ESSL (ESP Serial Slave Link) to use if you are communicating with an ESP32 SDIO slave. See :doc:`/api-reference/protocols/esp_serial_slave_link` and example :example:`peripherals/sdio/host`. There is a component `ESSL <https://components.espressif.com/components/espressif/esp_serial_slave_link>`_ (ESP Serial Slave Link) to use if you are communicating with an ESP32 SDIO slave. See example :example:`peripherals/sdio/host`.
Combo (Memory + IO) Cards Combo (Memory + IO) Cards
^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^

3
docs/page_redirects.txt
View File

@@ -73,6 +73,9 @@ api-guides/event-handling api-reference/system/esp_event
api-reference/network/tcpip_adapter migration-guides/tcpip-adapter api-reference/network/tcpip_adapter migration-guides/tcpip-adapter
api-reference/system/system api-reference/system/misc_system_api api-reference/system/system api-reference/system/misc_system_api
api-reference/protocols/esp_spi_slave_protocol "https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/spi_slave_hd_protocol.html"
api-reference/protocols/esp_sdio_slave_protocol "https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/sdio_slave_protocol.html"
api-reference/protocols/esp_serial_slave_link "https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/index.html"
# Driver-NG refactor # Driver-NG refactor
api-reference/peripherals/timer api-reference/peripherals/gptimer api-reference/peripherals/timer api-reference/peripherals/gptimer

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@@ -149,11 +149,11 @@ SDIO 从机驱动程序的相关术语如下：
与 ESP SDIO 从机通信 与 ESP SDIO 从机通信
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
在使用主机初始化 SDIO 从机时，应遵循标准 SDIO 初始化流程（请参阅 `SDIO 简化规范 <https://www.sdcard.org/downloads/pls/pdf/?p=PartE1_SDIO_Simplified_Specification_Ver3.00.jpg&f=PartE1_SDIO_Simplified_Specification_Ver3.00.pdf&e=EN_SSE1>`_ 的第 3.1.2 节），简化版流程可参考 :ref:`esp_slave_init`。 在使用主机初始化 SDIO 从机时，应遵循标准 SDIO 初始化流程（请参阅 `SDIO 简化规范 <https://www.sdcard.org/downloads/pls/pdf/?p=PartE1_SDIO_Simplified_Specification_Ver3.00.jpg&f=PartE1_SDIO_Simplified_Specification_Ver3.00.pdf&e=EN_SSE1>`_ 的第 3.1.2 节），简化版流程可参考 `ESP SDIO Slave 初始化 <https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/sdio_slave_protocol.html#esp-sdio-slave-initialization>`_ 。
此外，在通过 CMD52/CMD53 访问到 Function 1 这一机制的基础上，还存在一个仅适用于 {IDF_TARGET_NAME} 的上层通信协议。该特定通信协议中，主机和从机通过 CMD52/CMD53 命令进行数据交换和通信。更多详情，请参阅 :ref:`esp_slave_protocol_layer`。 此外，在通过 CMD52/CMD53 访问到 Function 1 这一机制的基础上，还存在一个仅适用于 {IDF_TARGET_NAME} 的上层通信协议。该特定通信协议中，主机和从机通过 CMD52/CMD53 命令进行数据交换和通信。更多详情，请参阅 `ESP SDIO 从机协议 <https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/sdio_slave_protocol.html#esp-sdio-slave-protocol>`_ 。
组件 :doc:`/api-reference/protocols/esp_serial_slave_link` 也支持 {IDF_TARGET_NAME} 主机与 {IDF_TARGET_NAME} SDIO 从机通信。在开发主机应用程序时，请参阅 :example:`peripherals/sdio` 中的示例。 组件 `ESSL <https://components.espressif.com/components/espressif/esp_serial_slave_link>`_ 也支持 {IDF_TARGET_NAME} 主机与 {IDF_TARGET_NAME} SDIO 从机通信。在开发主机应用程序时，请参阅 :example:`peripherals/sdio` 中的示例。
.. _interrupts: .. _interrupts:

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@@ -13,7 +13,7 @@ SPI 从机半双工模式
协议 协议
^^^^^^^^ ^^^^^^^^
有关主设备与 SPI 从机通信的详细信息，请参阅 :doc:`/api-reference/protocols/esp_spi_slave_protocol`。 有关主设备与 SPI 从机通信的详细信息，请参阅 `ESP SPI 从机半双工协议 <https://espressif.github.io/idf-extra-components/latest/esp_serial_slave_link/spi_slave_hd_protocol.html#spi-slave-hd-half-duplex-protocol>`_ 。
通过不同类型的事务，从设备为主设备提供以下服务： 通过不同类型的事务，从设备为主设备提供以下服务：

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@@ -1,217 +0,0 @@
ESP SDIO 主从机通信
========================
:link_to_translation:`en:[English]`
本文档介绍了 ESP 数字输入输出 (Secure Digital Input and Output，SDIO) 从机设备的初始化过程，并提供 ESP SDIO 从机协议的详细信息。该协议为非标准协议，允许 SDIO 主机与 ESP SDIO 从机进行通信。
创建 ESP SDIO 从机协议是为了实现 SDIO 主机和从机之间的通信。这是因为 SDIO 规范只说明了如何访问卡的自定义区（向功能 1-7 发送 CMD52 和 CMD53），却没有说明底层的硬件实现过程。
.. _esp_sdio_slave_caps:
乐鑫芯片的 SDIO 从机功能
-----------------------------------
{IDF_TARGET_NAME} 芯片的 SDIO 从机提供以下服务：
.. list-table::
:widths: 70 30
:header-rows: 1
* - 服务
- {IDF_TARGET_NAME}
* - SDIO 从机
- Y
* - :ref:`Tohost intr <esp_sdio_slave_interrupts>`
- 8
* - :ref:`Frhost intr <esp_sdio_slave_interrupts>`
- 8
* - :ref:`TX DMA <esp_sdio_slave_send_fifo>`
- Y
* - :ref:`RX DMA <esp_sdio_slave_rcv_fifo>`
- Y
* - :ref:`共享寄存器 <esp_sdio_slave_shared_registers>`
- 56\*
\* 未包括中断寄存器
.. _esp_slave_init:
初始化 ESP SDIO 从机
-------------------------
主机需按照标准的 SDIO 初始化流程，对 {IDF_TARGET_NAME} SDIO 从机进行初始化（参考 `SDIO Simplified Specification <https://www.sdcard.org/downloads/pls/>`_ 3.1.2 章节）。下文将 SDIO 从机简称为 SD/SDIO 卡。以下是 ESP SDIO 从机初始化流程的一个简单示例：
1. SDIO 复位
CMD52（写入 0x6 = 0x8）
2. SD 复位
CMD0
3. 检查 IO 卡（可选）
CMD8
4. 发送 SDIO op cond 指令，等待 IO 卡就绪
CMD5 arg = 0x00000000
CMD5 arg = 0x00ff8000（根据以上响应进行轮询，直到 IO 卡就绪）
**示例：**
首次 CMD5 (arg = 0x00000000) 后 R4 的 arg 为 0xXXFFFF00。
不断发送 CMD5 arg = 0x00FFFF00，直到 R4 显示卡已就绪 (arg 31 = 1) 为止。
5. 设置地址
CMD3
6. 选择卡
CMD7（根据 CMD3 响应设置 arg）
**示例：**
CMD3 后 R6 的 arg 为 0x0001xxxx。
CMD7 的 arg 应为 0x00010000。
7. 选择 4-bit 模式（可选）
CMD52（写入 0x07 = 0x02）
8. 启用 Func1
CMD52（写入 0x02 = 0x02）
9. 启用 SDIO 中断（使用中断线 (DAT1) 时必要）
CMD52（写入 0x04 = 0x03）
10. 设置 Func0 块大小（可选，默认为 512 (0x200) 字节）
CMD52/53（读取 0x10 ~ 0x11）
CMD52/53（写入 0x10 = 0x00）
CMD52/53（写入 0x11 = 0x02）
CMD52/53（再次读取 0x10 ~ 0x11, 检查最终写入的值）
11. 设置 Func1 块大小（可选，默认为 512 (0x200) 字节）
CMD52/53（读取 0x110 ~ 0x111）
CMD52/53（写入 0x110 = 0x00）
CMD52/53（写入 0x111 = 0x02）
CMD52/53（再次读取 0x110 ~ 0x111, 检查最终写入的值）
.. _esp_slave_protocol_layer:
ESP SDIO 从机协议
--------------------------
ESP SDIO 从机协议基于 SDIO 规范的 I/O 读/写命令（即 CMD52 和 CMD53）创建。该协议提供以下服务：
- 发送 FIFO 和接收 FIFO
- 52 个主从机共享的 8 位读写寄存器（要了解详细信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *SDIO 从机控制器* > *寄存器列表* > SDIO SLC Host 寄存器 [`PDF <{IDF_TARGET_TRM_CN_URL}#sdioslave-reg-summ>`__]）
- 16 个通用中断源，其中 8 个从主机到从机的中断源，8 个自从机到主机的中断源。
开始通信前，主机需启用从机的 I/O Function 1，访问从机的寄存器，如下所示。
代码示例：:example:`peripherals/sdio`
ESP32 SDIO 用作主机与 ESP32 SDIO 从机通信时，协议中涉及的逻辑由 :doc:`/api-reference/protocols/esp_serial_slave_link` 组件实现。
.. _esp_sdio_slave_shared_registers:
从机寄存器列表
^^^^^^^^^^^^^^^^^^^^^^
32 位
""""""
- 0x044 (TOKEN_RDATA): 第 27-16 位为接收 buffer 的数量。
- 0x058 (INT_ST): 保存自从机到主机的中断源位。
- 0x060 (PKT_LEN): 保存主机已读取的累计数据长度（以字节为单位），和已复制到缓冲区但尚未读取的数据。
- 0x0D4 (INT_CLR): 写 1 清除 与 INT_ST 对应的中断位。
- 0x0DC (INT_ENA): 从机到主机的中断屏蔽位。
8 位
"""""
共享通用寄存器：
- 0x06C-0x077: 读/写寄存器 0-11，主机和从机都可读写。
- 0x07A-0x07B: 读/写寄存器 14-15，主机和从机都可读写。
- 0x07E-0x07F: 读/写寄存器 18-19，主机和从机都可读写。
- 0x088-0x08B: 读/写寄存器 24-27，主机和从机都可读写。
- 0x09C-0x0BB: 读/写寄存器 32-63，主机和从机都可读写。
中断寄存器：
- 0x08D (SLAVE_INT)：主机对从机的中断位，会自动清空。
FIFO（发送和接收）
""""""""""""""""""""""""""""
0x090 - 0x1F7FF 用作 FIFO。
CMD53 的地址与单次传输中从从机读取或写入从机的要求长度 (requested length) 有关。如下式所示：
*要求长度 = 0x1F800 - 地址*
从机返回的数据长度等于 CMD53 中定义的长度。如果数据长度大于 *requested length*，多余的数据会在发送时自动补零，或在接收时被丢弃，这一情况同时适用于 CMD53 的块模式和字节模式。
.. note::
将功能编号设置为 1，将 OP 也设置为 1（适用于 CMD53）。
为了提高以任意长度访问 FIFO 时的效率，可以将 CMD53 的块模式和字节模式结合使用。例如，如果块大小默认设置为 512 字节，则可以通过以下操作从 FIFO 中写入或获取 1031 字节的数据：
1. 在块模式下发送 CMD53，block count = 2（1024 字节）到 0x1F3F9 = 0x1F800 - **1031**。
2. 然后在字节模式下发送 CMD53，byte count = 8（如果控制器支持也可为 7）到 0x1F7F9 = 0x1F800 - **7**。
.. _esp_sdio_slave_interrupts:
中断
^^^^
SDIO 中断属于电平敏感中断。对于主机中断，从机通过在适当时间拉低 DAT1 线的方式发送中断。当该中断线被拉低后，主机会检测到变化并读取 INT_ST 寄存器，确定中断源。然后，主机写入 INT_CLR 寄存器清除中断位，并处理中断。主机也可以清除 INT_ENA 寄存器中相应位以屏蔽不需要的源。如果所有源都已清除或已屏蔽，DAT1 线状态无效。
{IDF_TARGET_NAME} 上对应的 host_int 位：0 至 7。
对于从机中断，主机发起一次传输，将数据写入 SLAVE_INT 寄存器。一旦某位被写入 1，从机硬件和驱动程序就会检测到变化，通知应用程序。
.. _esp_sdio_slave_rcv_fifo:
接收 FIFO
^^^^^^^^^^^
要写入从机的接收 FIFO，主机应完成以下步骤：
1. **读取 TOKEN_RDATA (0x044) 寄存器的 TOKEN1 字段（27-16 位）。** 剩余的缓冲数量为 TOKEN1 减去主机使用的缓冲数量。
2. **确保有足够的 buffer**，（*buffer_size* x *buffer_num* 应大于要写入数据的长度，*buffer_size* 是主机和从机在开始通信前预定义的值）。如果 buffer 不够，重复步骤 1，直至满足要求为止。
3. **用 CMD53 写入 FIFO 地址**。注意， *requested length* 不应超过步骤 2 中计算出的长度，FIFO 地址与 *requested length* 有关。
4. **计算已使用的缓冲**。 注意，尾部的缓冲即使仅部分使用，也属于已使用的范围。
.. _esp_sdio_slave_send_fifo:
发送 FIFO
^^^^^^^^^^^
要读取从机的发送 FIFO，主机应完成以下步骤：
1. **等待中断线有效**。（可选，默认为低电平）
2. **读取（轮询）INT_ST 寄存器中的中断位**，以监控是否存在新数据包。
3. **如果新数据包已准备就绪，读取 PKT_LEN 寄存器**。在读取数据包之前，确定要读取数据的长度。由于主机会保留已从从机中读取的数据的长度，因此，要从 PKT_LEN 中减去该值，得到可读取的最大数据长度。如果发送 FIFO 中尚未写入过数据，则继续等待并轮询，直到从机准备就绪，然后更新 PKT_LEN。
4. **用 CMD53 从 FIFO 中读取数据**。注意， *要求长度* 应不大于步骤 3 中计算出的长度，FIFO 地址与 *要求长度* 相关。
5. **更新读取长度**。

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ESP 串行从机链路
=================
:link_to_translation:`en:[English]`
概述
----
乐鑫有多款芯片可用作从机。这些从机依赖于一些通用总线，并在总线上实现了各自的通信协议。 ``esp_serial_slave_link`` 组件能让主机通过总线驱动和相应的协议与 ESP 从机进行通信。
``esp_serial_slave_link`` 设备初始化完成后，应用程序就能通过它与 ESP 从机方便地通信。
.. note::
``esp_serial_slave_link`` 组件自 ESP-IDF 版本 v5.0 起移到了单独的仓库：
* `ESSL component on GitHub <https://github.com/espressif/idf-extra-components/tree/master/esp_serial_slave_link>`__
运行 ``idf.py add-dependency espressif/esp_serial_slave_link`` 将 ESSL 组件添加到你的项目中。
乐鑫设备协议
--------------------
如需了解关于乐鑫设备协议详情，请参考以下文档：
.. toctree::
:maxdepth: 1
:SOC_SDIO_SLAVE_SUPPORTED: esp_sdio_slave_protocol
esp_spi_slave_protocol
术语解释
--------
- ESSL：ESP 串行从机链路 (ESP Serial Slave Link)，即本文档描述的组件。
- 主机：运行 ``esp_serial_slave_link`` 组件的设备。
- ESSL 设备：主机上的虚拟设备，关联到一个 ESP 从机，其设备上下文中具有如何通过总线驱动和从机的总线协议与其通信的信息。
- ESSL 设备句柄：ESSL 设备上下文的一个句柄，包含配置信息、状态信息和 ESSL 组件所需的数据。设备上下文中储存了驱动配置、通信状态和主从机共享的数据等。
- 在使用前，应将上下文初始化；如不再使用，应该反初始化。主机应用程序通过这一句柄操作 ESSL 设备。
- ESP 从机：连接到总线的从机，ESSL 组件的通信对象。
- 总线：特指用于主机和从机相互通信的总线。
- 从机协议：Espressif 硬件和软件在总线上使用的特殊通信协议。
- TX buffer num：计数器，位于从机，可由主机读取。指示由从机加载到硬件上、用于接收主机数据的累计 buffer 总数。
- RX data size：计数器，位于从机，可由主机读取。指示由从机加载到硬件上、需发送给主机的累计数据大小。
ESP 从机提供的服务
---------------------------
Espressif 从机提供下列服务：
1. Tohost 中断：从机可通过中断线向主机通知某些事件。（可选）
2. Frhost 中断：主机可向从机通知某些事件。
3. TX FIFO（主机到从机）：从机能够以接收 buffer 为单位，接收主机发送的数据。
从机通过更新 TX buffer num 的方式，将可以接收多少数据的信息通知主机。主机读取 TX buffer num，减去已使用的 buffer 数，得到剩余 buffer 数量。
4. RX FIFO（从机到主机）：从机可向主机发送数据流。SDIO 从机也可通过中断线通知主机，从机有待发送的新数据。
从机通过更新 RX data size，将准备发送的数据大小通知主机。主机读取该数据大小，减去已接收的数据长度，得到剩余数据大小。
5. 共享寄存器：主机可以读取从机寄存器上的部分内容，也可写入从机寄存器供从机读取。
.. only:: SOC_SDIO_SLAVE_SUPPORTED
从机提供的服务取决于从机的模型。如需了解详情，请参考 :ref:`esp_sdio_slave_caps` 和 :ref:`esp_spi_slave_caps`。
.. only:: not SOC_SDIO_SLAVE_SUPPORTED
从机提供的服务取决于从机的模型。如需了解详情，请参考 :ref:`esp_spi_slave_caps`。
初始化 ESP 串行从机链路
--------------------------------
.. _essl_sdio_slave_init:
ESP SDIO 从机
^^^^^^^^^^^^^^^^^
ESP SDIO 从机链路 (ESSL SDIO) 设备依赖于 SDMMC 组件。它可通过 SDMMC Host 或 SDSPI Host 功能均可与 ESP SDIO 从机通信。ESSL 设备初始化步骤如下：
1. 初始化 SDMMC 卡（参考 :doc:`SDMMC 驱动相关文档 </api-reference/storage/sdmmc>` ）结构体。
2. 调用 :cpp:func:`sdmmc_card_init` 初始化该卡。
3. 用 :cpp:type:`essl_sdio_config_t` 初始化 ESSL 设备。其中， ``card`` 成员应为第二步中的 :cpp:type:`sdmmc_card_t`， ``recv_buffer_size`` 成员应填写为预先协商的值。
4. 调用 :cpp:func:`essl_init` 对 SDIO 部分进行初始化。
5. 调用 :cpp:func:`essl_wait_for_ready` 等待从机就绪。
ESP SPI 从机
^^^^^^^^^^^^^^^^^^
.. note::
如果你正在用 SPI 接口与 ESP SDIO 从机进行通信，则应该用 :ref:`SDIO 接口 <essl_sdio_slave_init>` 代替。
暂不支持。
API
--------
初始化完成后，你可调用以下 API 使用从机提供的服务：
Tohost 中断（可选）
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1. 调用 :cpp:func:`essl_get_intr_ena` 了解哪些事件触发了对主机的中断。
2. 调用 :cpp:func:`essl_set_intr_ena` 设置能够触发主机中断的事件。
3. 调用 :cpp:func:`essl_wait_int` 等待从机中断或超时。
4. 中断触发后，调用 :cpp:func:`essl_get_intr` 了解哪些事件处于活跃状态，并调用 :cpp:func:`essl_clear_intr` 将其清空。
Frhost 中断
^^^^^^^^^^^^^^^^^
1. 调用 :cpp:func:`essl_send_slave_intr` 触发从机的通用中断。
TX FIFO
^^^^^^^
1. 调用 :cpp:func:`essl_get_tx_buffer_num` 了解从机准备用于接收主机数据的 buffer 数。你可选择是否调用该函数。主机向从机发送数据包前，也会轮询 ``tx_buffer_num``，直到从机的 buffer 数量足够或超时。
2. 调用 :cpp:func:`essl_send_packet` 向从机发送数据。
RX FIFO
^^^^^^^
1. 调用 :cpp:func:`essl_get_rx_data_size` 了解从机需发送给主机的数据大小。你可选择是否调用该函数。当主机尝试接收数据时，如果目前的 ``rx_data_size`` 小于主机准备接收数据的 buffer 大小，就会对 ``rx_data_size`` 进行一次更新。如果 ``rx_data_size`` 一直为 0，主机可能会轮询 ``rx_data_size`` 直到超时。
2. 调用 :cpp:func:`essl_get_packet` 接收来自从机的数据。
重置计数器（可选）
^^^^^^^^^^^^^^^^^^^^^^^^^
如果从机计数器已重置，调用 :cpp:func:`essl_reset_cnt` 重置内部计数器。
应用示例
--------------
以下示例展示了 {IDF_TARGET_NAME} SDIO 主机如何与从机互相通信，其中主机使用了 ESSL SDIO：
:example:`peripherals/sdio`
如需了解详情，请参考 README.md 中的示例。
API 参考
----------
.. include-build-file:: inc/essl.inc
.. include-build-file:: inc/essl_sdio.inc
.. include-build-file:: inc/essl_spi.inc

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ESP SPI 从机 HD（半双工）模式协议
==========================================
:link_to_translation:`en:[English]`
.. only:: esp32
.. warning::
ESP32 不支持此功能。
.. _esp_spi_slave_caps:
乐鑫芯片的 SPI 从机功能支持概况
---------------------------------
+---------+------------+-----------+-----------+------+------+----------------+
| |SPI Slave HD|Tohost intr|Frhost intr|TX DMA|RX DMA|Shared registers|
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32 | N | | | | | |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-S2 | Y(v2) | N | 2 \* | Y | Y | 72 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C3 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-S3 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C2 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C6 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-H2 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-P4 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C5 | Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-C61| Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
|ESP32-H21| Y(v2) | N | 2 \* | Y | Y | 64 |
+---------+------------+-----------+-----------+------+------+----------------+
概述
----
在半双工模式下，主机须使用从机定义的协议与从机通信。每个传输事务按顺序可能包括以下阶段：
- 命令阶段：8 位，主机到从机
此阶段决定事务的其它阶段。参见 :ref:`spi_slave_hd_supported_cmds`。
- 地址阶段：8 位，主机到从机，可选
对于某些命令（如 WRBUF、RDBUF），此阶段指定要写入/读取的共享寄存器地址。对于其他包括此阶段的命令，这没有实际意义，但仍必须存在于事务中。
.. only:: esp32s2
- Dummy 阶段：8 位 (1线模式) 或 4 位 (2/4线模式)，浮动，可选
此阶段是主机和从机在总线上的周转时间，并为从机向主机发送数据提供了充分的准备时间。
.. only:: not esp32s2
- Dummy 阶段：8 位，浮动，可选
此阶段是主机和从机在总线上的周转时间，并为从机向主机发送数据提供了充分的准备时间。
- 数据阶段：长度可变，方向由命令确定。
这一阶段可以输出数据（OUT，方向为由从机向主机），或者输入数据（IN，方向为由主机向从机）。
**方向** 是指哪一方（主机或从机）控制 MOSI、MISO、WP 和 HD 管脚。
数据 IO 模式
-------------
在某些 IO 模式下，可以使用更多数据线来发送数据。因此，与 1 位模式相比，发送相同数据量所需的 SPI 时钟周期更少。例如，在 QIO 模式下，地址和数据（IN 和 OUT）应发送到全部 4 条数据线上（MOSI、MISO、WP 和 HD）。下表展示了 ESP32-S2 SPI 从机支持的模式，以及相应模式下使用的数据线数量。
+-------+----------+----------+------------+----------+
| Mode | 命令线数 | 地址线数 | dummy 线数 | 数据线数 |
+-------+----------+----------+------------+----------+
| 1-bit | 1 | 1 | 1 | 1 |
+-------+----------+----------+------------+----------+
| DOUT | 1 | 1 | 4 | 2 |
+-------+----------+----------+------------+----------+
| DIO | 1 | 2 | 4 | 2 |
+-------+----------+----------+------------+----------+
| QOUT | 1 | 1 | 4 | 4 |
+-------+----------+----------+------------+----------+
| QIO | 1 | 4 | 4 | 4 |
+-------+----------+----------+------------+----------+
| QPI | 4 | 4 | 4 | 4 |
+-------+----------+----------+------------+----------+
除 QPI 模式外，使用哪种模式通常取决于主机发送的命令（请参考 :ref:`spi_slave_hd_supported_cmds`）。
QPI 模式
^^^^^^^^
QPI 模式是 SPI 从机的一种特殊状态。主机可发送 ENQPI 命令，使从机进入 QPI 模式。在 QPI 模式下，命令以 4 位形式发送，因此与其他正常模式不兼容。只有在从机处于 QPI 模式时，主机才能发送 QPI 命令。主机可发送 EXQPI 命令退出 QPI 模式。
.. _spi_slave_hd_supported_cmds:
支持的命令
----------
.. note::
命令名称是从主机视角确定的。例如，WRBUF 表示由主机向从机的缓冲区写入。
+----------+---------------+------+----------+------------------------------+
| 名称 | 描述 | 命令 | 地址 | 数据 |
+----------+---------------+------+----------+------------------------------+
| WRBUF | 写入缓冲区 | 0x01 | Buf addr | 主到从，不超过缓冲区大小 |
+----------+---------------+------+----------+------------------------------+
| RDBUF | 读取缓冲区 | 0x02 | Buf addr | 从到主，不超过缓冲区大小 |
+----------+---------------+------+----------+------------------------------+
| WRDMA | 写入 DMA | 0x03 | 8 位 | 主到从，不超过从机提供的长度 |
+----------+---------------+------+----------+------------------------------+
| RDDMA | 读取 DMA | 0x04 | 8 位 | 从到主，不超过从机提供的长度 |
+----------+---------------+------+----------+------------------------------+
| SEG_DONE | 段完成 | 0x05 | - | - |
+----------+---------------+------+----------+------------------------------+
| ENQPI | 进入 QPI 模式 | 0x06 | - | - |
+----------+---------------+------+----------+------------------------------+
| WR_DONE | 写入段完成 | 0x07 | - | - |
+----------+---------------+------+----------+------------------------------+
| CMD8 | 中断 | 0x08 | - | - |
+----------+---------------+------+----------+------------------------------+
| CMD9 | 中断 | 0x09 | - | - |
+----------+---------------+------+----------+------------------------------+
| CMDA | 中断 | 0x0A | - | - |
+----------+---------------+------+----------+------------------------------+
| EXQPI | 退出 QPI 模式 | 0xDD | - | - |
+----------+---------------+------+----------+------------------------------+
此外，WRBUF、RDBUF、WRDMA 和 RDDMA 命令都有 2 位和 4 位版本。要在 2 位或 4 位模式下操作，请用下表中的对应命令掩码与原始命令按位或 (bit OR) 后发送。例如，命令 0xA1 表示 QIO 模式下的 WRBUF。
+-------+------+
| 模式 | 掩码 |
+-------+------+
| 1-bit | 0x00 |
+-------+------+
| DOUT | 0x10 |
+-------+------+
| DIO | 0x50 |
+-------+------+
| QOUT | 0x20 |
+-------+------+
| QIO | 0xA0 |
+-------+------+
| QPI | 0xA0 |
+-------+------+
段事务模式
------------------
目前，SPI 从机 HD 驱动程序仅支持段事务模式。在此模式下，对于从机加载到 DMA 的事务，主机可以分段读取或写入。这样，主机就无需准备与从机数据大小相同的大缓冲区。主机在一个缓冲区的读取/写入完成后，须向从机发送相应的终止命令作为同步信号。在从机收到终止命令后，从机驱动程序会将新数据（如有）更新到 DMA 上。
WRDMA 的终止命令是 WR_DONE (0x07)，RDDMA 的终止命令是 CMD8 (0x08)。
以下是主机自从机 DMA 读取数据的流程示例：
1. 从机将 4092 字节数据加载到 RDDMA。
2. 主机进行七次 RDDMA 事务，每个事务长 512 字节，并自从机读取前 3584 字节。
3. 主机进行最后一次 RDDMA 事务，长度为 512 字节（长度可以与从机相同、更长或更短）。前 508 字节是从机发送的有效数据，最后 4 字节无意义。
4. 主机向从机发送 CMD8。
5. 从机将其他的 4092 字节数据加载到 RDDMA。
6. 主机发送 CMD8 后，可以开始新的读取事务。

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@@ -12,7 +12,6 @@
esp_tls esp_tls
esp_http_client esp_http_client
esp_local_ctrl esp_local_ctrl
esp_serial_slave_link
esp_crt_bundle esp_crt_bundle
esp_http_server esp_http_server
esp_https_server esp_https_server

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@@ -109,9 +109,9 @@ SD/SDIO/MMC 驱动支持 SD 存储器、SDIO 卡和 eMMC 芯片。这是一个
如果需要应用程序保持等待直至发生 SDIO 中断，请使用 :cpp:func:`sdmmc_io_wait_int` 函数。 如果需要应用程序保持等待直至发生 SDIO 中断，请使用 :cpp:func:`sdmmc_io_wait_int` 函数。
.. only:: esp32 .. only:: SOC_SDMMC_HOST_SUPPORTED and SOC_SDIO_SLAVE_SUPPORTED
如果需要与 ESP32 的 SDIO 从设备通信，请使用 ESSL 组件（ESP 串行从设备链接）。请参阅 :doc:`/api-reference/protocols/esp_serial_slave_link` 和示例 :example:`peripherals/sdio/host`。 如果需要与 ESP32 的 SDIO 从设备通信，请使用 `ESSL <https://components.espressif.com/components/espressif/esp_serial_slave_link>`_ 组件（ESP 串行从设备链接）。请参阅示例 :example:`peripherals/sdio/host`。
复合卡（存储 + IO） 复合卡（存储 + IO）
^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^