Merge branch 'refactor/hal_function_set_exception_vector_table' into 'master'

soc: add hal api to set exception vector table base address

See merge request espressif/esp-idf!7905

components/esp32/cpu_start.c

@@ -130,10 +130,8 @@ void IRAM_ATTR call_start_cpu0(void)
 
     bootloader_init_mem();
 
-    //Move exception vectors to IRAM
+    // Move exception vectors to IRAM
-    asm volatile (\
+    cpu_hal_set_vecbase(&_init_start);
-                  "wsr    %0, vecbase\n" \
-                  ::"r"(&_init_start));
 
     rst_reas[0] = rtc_get_reset_reason(0);
 
@@ -273,9 +271,8 @@ static void wdt_reset_cpu1_info_enable(void)
 
 void IRAM_ATTR call_start_cpu1(void)
 {
-    asm volatile (\
+    // Move exception vectors to IRAM
-                  "wsr    %0, vecbase\n" \
+    cpu_hal_set_vecbase(&_init_start);
-                  ::"r"(&_init_start));
 
     ets_set_appcpu_boot_addr(0);
 

components/esp32s2/cpu_start.c

@@ -114,10 +114,8 @@ void IRAM_ATTR call_start_cpu0(void)
 
     bootloader_init_mem();
 
-    //Move exception vectors to IRAM
+    // Move exception vectors to IRAM
-    asm volatile (\
+    cpu_hal_set_vecbase(&_init_start);
-                  "wsr    %0, vecbase\n" \
-                  ::"r"(&_init_start));
 
     rst_reas = rtc_get_reset_reason(0);
 

components/soc/include/hal/cpu_hal.h

@@ -109,6 +109,13 @@ void cpu_hal_clear_watchpoint(int id);
 
 #endif // SOC_CPU_WATCHPOINTS_NUM > 0
 
+/**
+ * Set exception vector table base address.
+ *
+ * @param base address to move the exception vector table to
+ */
+void cpu_hal_set_vecbase(const void* base);
+
 #ifdef __cplusplus
 }
 #endif

components/soc/src/esp32/include/hal/cpu_ll.h

@@ -166,6 +166,11 @@ static inline void cpu_ll_break(void)
     __asm__ ("break 0,0");
 }
 
+static inline void cpu_ll_set_vecbase(const void* vecbase)
+{
+    asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
+}
+
 #ifdef __cplusplus
 }
 #endif

components/soc/src/esp32s2/include/hal/cpu_ll.h

@@ -162,6 +162,11 @@ static inline void cpu_ll_break(void)
     __asm__ ("break 0,0");
 }
 
+static inline void cpu_ll_set_vecbase(const void* vecbase)
+{
+    asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
+}
+
 #ifdef __cplusplus
 }
 #endif

components/soc/src/hal/cpu_hal.c

@@ -54,4 +54,9 @@ void cpu_hal_clear_watchpoint(int id)
 {
     cpu_ll_clear_watchpoint(id);
 }
-#endif // SOC_CPU_WATCHPOINTS_NUM > 0
+#endif // SOC_CPU_WATCHPOINTS_NUM > 0
+
+void cpu_hal_set_vecbase(const void* base)
+{
+    cpu_ll_set_vecbase(base);
+}