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https://github.com/espressif/esp-idf.git
synced 2026-05-03 19:41:55 +02:00
fix(bootloader): Fix compilation issue in bootloader build during verbose+sb+fe
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@@ -24,7 +24,7 @@
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x4ff3abd0;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x4000;
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x2000;
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@@ -47,7 +47,7 @@ MEMORY
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* 2. Update the value in this assert.
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* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32p4/memory.ld.in to the same value.
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*/
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ASSERT(bootloader_iram_loader_seg_start == 0x4FF2DBD0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
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ASSERT(bootloader_iram_loader_seg_start == 0x4FF2CBD0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
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/* Default entry point: */
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ENTRY(call_start_cpu0);
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -10,9 +10,9 @@
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MEMORY
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{
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iram_seg (RWX) : org = 0x4004B000, len = 0x4000 /* SRAM part of block 12 and 13 */
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iram_loader_seg (RWX) : org = 0x4004F000, len = 0x7000 /* SRAM part of block 13, Block 14 & part of 15 */
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dram_seg (RW) : org = 0x3FFE6000, len = 0x4B00 /* Part SRAM Blocks 15 & 16, ROM static buffer starts at end of this region (reclaimed after app runs) */
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iram_seg (RWX) : org = 0x4004A000, len = 0x4000 /* SRAM part of block 12 and 13 */
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iram_loader_seg (RWX) : org = 0x4004E000, len = 0x7000 /* SRAM part of block 13, Block 14 & part of 15 */
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dram_seg (RW) : org = 0x3FFE5000, len = 0x5B00 /* Part SRAM Blocks 15 & 16, ROM static buffer starts at end of this region (reclaimed after app runs) */
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}
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/* Default entry point: */
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@@ -26,7 +26,7 @@ iram_dram_offset = 0x6f0000;
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x3fce9700;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x4000;
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x3000;
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@@ -49,7 +49,7 @@ MEMORY
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* 2. Update the value in this assert.
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* 3. Update SRAM_IRAM_END in components/esp_system/ld/esp32s3/memory.ld.in to the same value.
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*/
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ASSERT(bootloader_iram_loader_seg_start == 0x403cc700, "bootloader_iram_loader_seg_start inconsistent with SRAM_IRAM_END");
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ASSERT(bootloader_iram_loader_seg_start == 0x403CB700, "bootloader_iram_loader_seg_start inconsistent with SRAM_IRAM_END");
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/* Default entry point: */
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ENTRY(call_start_cpu0);
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