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change(riscv): Remove redundant definition of MEMPROT_ISR

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harshal.patil
2025-07-29 14:50:14 +05:30
parent d70b5000cc
commit 5c6c73ece4
1 changed files with 2 additions and 6 deletions
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8
components/riscv/vectors_clic.S
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -8,11 +8,7 @@
/* If memory protection interrupts are meant to trigger a panic, attach them to panic handler, /* If memory protection interrupts are meant to trigger a panic, attach them to panic handler,
* else, attach them to the interrupt handler. */ * else, attach them to the interrupt handler. */
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define MEMPROT_ISR _interrupt_handler
#define MEMPROT_ISR _panic_handler
#else
#define MEMPROT_ISR _interrupt_handler
#endif // CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD #if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
#define ASTDBG_ISR _panic_handler #define ASTDBG_ISR _panic_handler