espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-11-01 23:51:49 +01:00
Code Issues Packages Projects Releases Wiki Activity

freertos: Added experimental, optional FPU usage on level 1 ISR

Browse Source
This commit is contained in:
Felipe Neves
2020-01-16 01:11:07 -03:00
parent 670ea56df2
commit 5cbb3f05c0
5 changed files with 61 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
docs/en/api-guides/freertos-smp.rst
View File

@@ -409,8 +409,9 @@ the state of a core's FPU registers are not immediately saved when a context
switch occurs. Therefore, tasks that utilize ``float`` must be pinned to a
particular core upon creation. If not, ESP-IDF FreeRTOS will automatically pin
the task in question to whichever core the task was running on upon the task's
first use of ``float``. Likewise due to Lazy Context Switching, interrupt service
routines must also not use ``float``.
first use of ``float``. Likewise due to Lazy Context Switching, only interrupt
service routines of lowest priority (that is it the Level 1) can use ``float``,
higher priority interrupts do not support FPU usage.
ESP32 does not support hardware acceleration for double precision floating point
arithmetic (``double``). Instead ``double`` is implemented via software hence the