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interrupt: added INTC FLEXIBLE capabillity to esp32c3 CPU caps

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This commit is contained in:
Felipe Neves
2020-12-16 14:20:38 -03:00
committed by morris
parent 544a3f7df5
commit 5d316ac142
8 changed files with 59 additions and 145 deletions
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20
components/esp_system/intr_alloc.c
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@@ -237,18 +237,20 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
ALCHLOG("....Unusable: special-purpose int"); ALCHLOG("....Unusable: special-purpose int");
return false; return false;
} }
#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
//Check if the interrupt level is acceptable //Check if the interrupt level is acceptable
if (!(flags&(1<<interrupt_controller_hal_get_level(x))) && if (!(flags&(1<<interrupt_controller_hal_get_level(x)))) {
(interrupt_controller_hal_get_type(x)!=INTTP_ANY)) {
ALCHLOG("....Unusable: incompatible level"); ALCHLOG("....Unusable: incompatible level");
return false;
}
//check if edge/level type matches what we want
if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL) && (interrupt_controller_hal_get_type(x)!= INTTP_ANY)) ||
(((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)&& (interrupt_controller_hal_get_type(x)!= INTTP_ANY)))) {
ALCHLOG("....Unusable: incompatible trigger type");
return false; return false;
} }
//check if edge/level type matches what we want
if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL)) ||
(((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) { ALCHLOG("....Unusable: incompatible trigger type");
return false;
}
#endif
//check if interrupt is reserved at runtime //check if interrupt is reserved at runtime
if (vd->flags&VECDESC_FL_RESERVED) { if (vd->flags&VECDESC_FL_RESERVED) {
ALCHLOG("....Unusable: reserved at runtime."); ALCHLOG("....Unusable: reserved at runtime.");
@@ -583,6 +585,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
esp_intr_disable(ret); esp_intr_disable(ret);
} }
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
//Extract the level from the interrupt passed flags //Extract the level from the interrupt passed flags
int level = (__builtin_ffs((flags >> 1) & ESP_INTR_FLAG_LEVELMASK)) + 1; int level = (__builtin_ffs((flags >> 1) & ESP_INTR_FLAG_LEVELMASK)) + 1;
@@ -593,6 +596,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
} else { } else {
interrupt_controller_hal_set_int_type(intr,INTTP_LEVEL); interrupt_controller_hal_set_int_type(intr,INTTP_LEVEL);
} }
#endif
portEXIT_CRITICAL(&spinlock); portEXIT_CRITICAL(&spinlock);

30
components/hal/esp32/include/hal/interrupt_controller_ll.h
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@@ -110,36 +110,6 @@ static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
xthal_set_intclear(1 << intr); xthal_set_intclear(1 << intr);
} }
/**
* @brief Sets the interrupt level int the interrupt controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param level priority between 1 (lowest) to 7 (highest)
*/
static inline void intr_cntrl_ll_set_int_level(int intr, int level)
{
/* Not needed currently for xtensa platforms since the level is already set
* in interrupt table
*/
(void)intr;
(void)level;
}
/**
* @brief Set the type of an interrupt in the controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param type interrupt type as edge or level triggered
*/
static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
{
/* Not needed currently for xtensa platforms since the type is already set
* in interrupt table
*/
(void)intr;
(void)type;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

64
components/hal/esp32c3/interrupt_descriptor_table.c
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@@ -18,38 +18,38 @@
//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h //This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
const int_desc_t interrupt_descriptor_table[32] = { const int_desc_t interrupt_descriptor_table[32] = {
{ 1, INTTP_ANY, {INTDESC_RESVD } }, //0 { 1, INTTP_NA, {INTDESC_RESVD } }, //0
{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //1 { 1, INTTP_NA, {INTDESC_SPECIAL } }, //1
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //2 { 1, INTTP_NA, {INTDESC_NORMAL } }, //2
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //3 { 1, INTTP_NA, {INTDESC_NORMAL } }, //3
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //4 { 1, INTTP_NA, {INTDESC_NORMAL } }, //4
{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //5 { 1, INTTP_NA, {INTDESC_SPECIAL } }, //5
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //6 { 1, INTTP_NA, {INTDESC_NORMAL } }, //6
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //7 { 1, INTTP_NA, {INTDESC_NORMAL } }, //7
{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //8 { 1, INTTP_NA, {INTDESC_SPECIAL } }, //8
{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //9 { 1, INTTP_NA, {INTDESC_SPECIAL } }, //9
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //10 { 1, INTTP_NA, {INTDESC_NORMAL } }, //10
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //11 { 1, INTTP_NA, {INTDESC_NORMAL } }, //11
{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //12 { 1, INTTP_NA, {INTDESC_SPECIAL } }, //12
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //13 { 1, INTTP_NA, {INTDESC_NORMAL } }, //13
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //14 { 1, INTTP_NA, {INTDESC_NORMAL } }, //14
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //15 { 1, INTTP_NA, {INTDESC_NORMAL } }, //15
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //16 { 1, INTTP_NA, {INTDESC_NORMAL } }, //16
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //17 { 1, INTTP_NA, {INTDESC_NORMAL } }, //17
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //18 { 1, INTTP_NA, {INTDESC_NORMAL } }, //18
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //19 { 1, INTTP_NA, {INTDESC_NORMAL } }, //19
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //20 { 1, INTTP_NA, {INTDESC_NORMAL } }, //20
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //21 { 1, INTTP_NA, {INTDESC_NORMAL } }, //21
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //22 { 1, INTTP_NA, {INTDESC_NORMAL } }, //22
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //23 { 1, INTTP_NA, {INTDESC_NORMAL } }, //23
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //24 { 1, INTTP_NA, {INTDESC_NORMAL } }, //24
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //25 { 1, INTTP_NA, {INTDESC_NORMAL } }, //25
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //26 { 1, INTTP_NA, {INTDESC_NORMAL } }, //26
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //27 { 1, INTTP_NA, {INTDESC_NORMAL } }, //27
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //28 { 1, INTTP_NA, {INTDESC_NORMAL } }, //28
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //29 { 1, INTTP_NA, {INTDESC_NORMAL } }, //29
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //30 { 1, INTTP_NA, {INTDESC_NORMAL } }, //30
{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //31 { 1, INTTP_NA, {INTDESC_NORMAL } }, //31
}; };
const int_desc_t *interrupt_controller_hal_desc_table(void) const int_desc_t *interrupt_controller_hal_desc_table(void)

32
components/hal/esp32s2/include/hal/interrupt_controller_ll.h
View File

@@ -109,38 +109,6 @@ static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
{ {
xthal_set_intclear(1 << intr); xthal_set_intclear(1 << intr);
} }
/**
* @brief Sets the interrupt level int the interrupt controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param level priority between 1 (lowest) to 7 (highest)
*/
static inline void intr_cntrl_ll_set_int_level(int intr, int level)
{
/* Not needed currently for xtensa platforms since the level is already set
* in interrupt table
*/
(void)intr;
(void)level;
}
/**
* @brief Set the type of an interrupt in the controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param type interrupt type as edge or level triggered
*/
static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
{
/* Not needed currently for xtensa platforms since the type is already set
* in interrupt table
*/
(void)intr;
(void)type;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

31
components/hal/esp32s3/include/hal/interrupt_controller_ll.h
View File

@@ -109,37 +109,6 @@ static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
{ {
xthal_set_intclear(1 << intr); xthal_set_intclear(1 << intr);
} }
/**
* @brief Sets the interrupt level int the interrupt controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param level priority between 1 (lowest) to 7 (highest)
*/
static inline void intr_cntrl_ll_set_int_level(int intr, int level)
{
/* Not needed currently for xtensa platforms since the level is already set
* in interrupt table
*/
(void)intr;
(void)level;
}
/**
* @brief Set the type of an interrupt in the controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param type interrupt type as edge or level triggered
*/
static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
{
/* Not needed currently for xtensa platforms since the type is already set
* in interrupt table
*/
(void)intr;
(void)type;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

24
components/hal/include/hal/interrupt_controller_hal.h
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@@ -84,17 +84,6 @@ static inline int_type_t interrupt_controller_hal_get_type(int interrupt_number)
return interrupt_controller_hal_desc_type(interrupt_number); return interrupt_controller_hal_desc_type(interrupt_number);
} }
/**
* @brief Set the type of an interrupt in the controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param type interrupt type as edge or level triggered
*/
static inline void interrupt_controller_hal_set_int_type(int intr, int_type_t type)
{
intr_cntrl_ll_set_int_type(intr, type);
}
/** /**
* @brief Gets the interrupt level given an interrupt number. * @brief Gets the interrupt level given an interrupt number.
* *
@@ -106,6 +95,18 @@ static inline int interrupt_controller_hal_get_level(int interrupt_number)
return interrupt_controller_hal_desc_level(interrupt_number); return interrupt_controller_hal_desc_level(interrupt_number);
} }
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
/**
* @brief Set the type of an interrupt in the controller.
*
* @param interrupt_number Interrupt number 0 to 31
* @param type interrupt type as edge or level triggered
*/
static inline void interrupt_controller_hal_set_int_type(int intr, int_type_t type)
{
intr_cntrl_ll_set_int_type(intr, type);
}
/** /**
* @brief Sets the interrupt level int the interrupt controller. * @brief Sets the interrupt level int the interrupt controller.
* *
@@ -116,6 +117,7 @@ static inline void interrupt_controller_hal_set_int_level(int intr, int level)
{ {
intr_cntrl_ll_set_int_level(intr, level); intr_cntrl_ll_set_int_level(intr, level);
} }
#endif
/** /**
* @brief Gets the cpu flags given the interrupt number and target cpu. * @brief Gets the cpu flags given the interrupt number and target cpu.

2
components/hal/include/hal/interrupt_controller_types.h
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@@ -30,7 +30,7 @@ typedef enum {
typedef enum { typedef enum {
INTTP_LEVEL=0, INTTP_LEVEL=0,
INTTP_EDGE, INTTP_EDGE,
INTTP_ANY, INTTP_NA,
} int_type_t; } int_type_t;
typedef struct { typedef struct {

1
components/soc/esp32c3/include/soc/cpu_caps.h
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@@ -16,5 +16,6 @@
#define SOC_CPU_BREAKPOINTS_NUM 8 #define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8 #define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes #define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes