Merge branch 'feat/support_esp32h4_modem_clock' into 'master'

feat(esp_hw_support): add esp32h4 modem clock initial support

Closes PM-445

See merge request espressif/esp-idf!39948

components/hal/esp32c5/include/hal/modem_lpcon_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -146,7 +146,7 @@ static inline void modem_lpcon_ll_set_clk_modem_aon_force(modem_lpcon_dev_t *hw,
 }
 
 __attribute__((always_inline))
-static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
+static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, modem_clock_32k_clk_src_t src)
 {
     hw->modem_32k_clk_conf.clk_modem_32k_sel = src;
 }
@@ -269,12 +269,6 @@ static inline void modem_lpcon_ll_set_pwr_tick_target(modem_lpcon_dev_t *hw, uin
     hw->tick_conf.modem_pwr_tick_target = val;
 }
 
-__attribute__((always_inline))
-static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
-{
-    return hw->date.val;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_chan_freq_mem(modem_lpcon_dev_t *hw, bool en)
 {

components/hal/esp32c5/include/hal/modem_syscon_ll.h

@@ -108,13 +108,13 @@ static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw
 }
 
 __attribute__((always_inline))
-static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw)
+static inline void modem_syscon_ll_enable_ieee802154_apb_force_clock(modem_syscon_dev_t *hw)
 {
     hw->clk_conf_force_on.clk_zbmac_apb_fo = 1;
 }
 
 __attribute__((always_inline))
-static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw)
+static inline void modem_syscon_ll_enable_ieee802154_mac_force_clock(modem_syscon_dev_t *hw)
 {
     hw->clk_conf_force_on.clk_zbmac_fo = 1;
 }

components/hal/esp32c5/modem_clock_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,12 +13,6 @@
 #include "hal/efuse_hal.h"
 #include "hal/assert.h"
 
-typedef enum {
-    MODEM_CLOCK_XTAL32K_CODE = 0,
-    MODEM_CLOCK_RC32K_CODE   = 1,
-    MODEM_CLOCK_EXT32K_CODE  = 2
-} modem_clock_32k_clk_src_code_t;
-
 void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
 {
     HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
@@ -154,15 +148,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -194,15 +188,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -234,15 +228,15 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);

components/hal/esp32c6/include/hal/modem_lpcon_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -134,7 +134,7 @@ static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_d
 }
 
 __attribute__((always_inline))
-static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
+static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, modem_clock_32k_clk_src_t src)
 {
     hw->modem_32k_clk_conf.clk_modem_32k_sel = src;
 }
@@ -251,12 +251,6 @@ static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
     hw->rst_conf.val = 0;
 }
 
-__attribute__((always_inline))
-static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
-{
-    return hw->date.val;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c6/include/hal/modem_syscon_ll.h

@@ -78,13 +78,13 @@ static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw
 }
 
 __attribute__((always_inline))
-static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw)
+static inline void modem_syscon_ll_enable_ieee802154_apb_force_clock(modem_syscon_dev_t *hw)
 {
     hw->clk_conf_force_on.clk_zb_apb_fo = 1;
 }
 
 __attribute__((always_inline))
-static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw)
+static inline void modem_syscon_ll_enable_ieee802154_mac_force_clock(modem_syscon_dev_t *hw)
 {
     hw->clk_conf_force_on.clk_zb_mac_fo = 1;
 }

components/hal/esp32c6/modem_clock_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,12 +13,6 @@
 #include "hal/efuse_hal.h"
 #include "hal/assert.h"
 
-typedef enum {
-    MODEM_CLOCK_XTAL32K_CODE = 0,
-    MODEM_CLOCK_RC32K_CODE   = 1,
-    MODEM_CLOCK_EXT32K_CODE  = 2
-} modem_clock_32k_clk_src_code_t;
-
 void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
 {
     HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
@@ -152,15 +146,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -192,15 +186,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -232,15 +226,15 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);

components/hal/esp32c61/include/hal/modem_lpcon_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -146,7 +146,7 @@ static inline void modem_lpcon_ll_set_clk_modem_aon_force(modem_lpcon_dev_t *hw,
 }
 
 __attribute__((always_inline))
-static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
+static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, modem_clock_32k_clk_src_t src)
 {
     hw->modem_32k_clk_conf.clk_modem_32k_sel = src;
 }
@@ -269,12 +269,6 @@ static inline void modem_lpcon_ll_set_pwr_tick_target(modem_lpcon_dev_t *hw, uin
     hw->tick_conf.modem_pwr_tick_target = val;
 }
 
-__attribute__((always_inline))
-static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
-{
-    return hw->date.val;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_chan_freq_mem(modem_lpcon_dev_t *hw, bool en)
 {

components/hal/esp32c61/include/hal/modem_syscon_ll.h

@@ -108,13 +108,13 @@ static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw
 }
 
 __attribute__((always_inline))
-static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw)
+static inline void modem_syscon_ll_enable_ieee802154_apb_force_clock(modem_syscon_dev_t *hw)
 {
     hw->clk_conf_force_on.clk_zbmac_apb_fo = 1;
 }
 
 __attribute__((always_inline))
-static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw)
+static inline void modem_syscon_ll_enable_ieee802154_mac_force_clock(modem_syscon_dev_t *hw)
 {
     hw->clk_conf_force_on.clk_zbmac_fo = 1;
 }

components/hal/esp32c61/modem_clock_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,12 +13,6 @@
 #include "hal/efuse_hal.h"
 #include "hal/assert.h"
 
-typedef enum {
-    MODEM_CLOCK_XTAL32K_CODE = 0,
-    MODEM_CLOCK_RC32K_CODE   = 1,
-    MODEM_CLOCK_EXT32K_CODE  = 2
-} modem_clock_32k_clk_src_code_t;
-
 void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
 {
     HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
@@ -154,15 +148,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -194,15 +188,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -234,15 +228,15 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
-        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
+        modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);

components/hal/esp32h2/include/hal/lp_clkrst_ll.h

@@ -13,6 +13,7 @@
 #include "soc/soc.h"
 #include "soc/lp_clkrst_struct.h"
 #include "soc/lpperi_struct.h"
+#include "hal/modem_clock_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -55,7 +56,7 @@ static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_de
 }
 
 __attribute__((always_inline))
-static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
+static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, modem_clock_32k_clk_src_t src)
 {
     hw->lpperi.lp_bletimer_32k_sel = src;
 }

components/hal/esp32h2/include/hal/modem_lpcon_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -99,12 +99,6 @@ static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
     hw->rst_conf.val = 0;
 }
 
-__attribute__((always_inline))
-static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
-{
-    return hw->date.val;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h2/modem_clock_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,12 +13,6 @@
 #include "hal/modem_clock_types.h"
 #include "hal/assert.h"
 
-typedef enum {
-    MODEM_CLOCK_XTAL32K_CODE = 0,
-    MODEM_CLOCK_RC32K_CODE   = 1,
-    MODEM_CLOCK_EXT32K_CODE  = 2
-} modem_clock_32k_clk_src_code_t;
-
 void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
 {
     modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
@@ -68,15 +62,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -108,15 +102,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);

components/hal/esp32h21/include/hal/lp_clkrst_ll.h

@@ -13,6 +13,7 @@
 #include "soc/soc.h"
 #include "soc/lp_clkrst_struct.h"
 #include "soc/lpperi_struct.h"
+#include "hal/modem_clock_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -55,7 +56,7 @@ static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_de
 }
 
 __attribute__((always_inline))
-static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
+static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, modem_clock_32k_clk_src_t src)
 {
     hw->lpperi.clkrst_lp_bletimer_32k_sel = src;
 }

components/hal/esp32h21/include/hal/modem_lpcon_ll.h

@@ -99,12 +99,6 @@ static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
     hw->rst_conf.val = 0;
 }
 
-__attribute__((always_inline))
-static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
-{
-    return hw->date.val;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h21/modem_clock_hal.c

@@ -13,12 +13,6 @@
 #include "hal/modem_clock_types.h"
 #include "hal/assert.h"
 
-typedef enum {
-    MODEM_CLOCK_XTAL32K_CODE = 0,
-    MODEM_CLOCK_RC32K_CODE   = 1,
-    MODEM_CLOCK_EXT32K_CODE  = 2
-} modem_clock_32k_clk_src_code_t;
-
 void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
 {
     modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
@@ -69,15 +63,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);
@@ -109,15 +103,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
         break;
     case MODEM_CLOCK_LPCLK_SRC_RC32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
         break;
     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
         modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
-        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
         break;
     default:
         HAL_ASSERT(0);

components/hal/esp32h4/include/hal/lp_clkrst_ll.h

@@ -0,0 +1,66 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H4 LP CLKRST & LP PERI register operations
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include "soc/soc.h"
+#include "soc/lp_clkrst_struct.h"
+#include "soc/lpperi_struct.h"
+#include "hal/modem_clock_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.lp_sel_osc_slow = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.lp_sel_osc_fast = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.lp_sel_xtal = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.lp_sel_xtal32k = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_set_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw, uint32_t value)
+{
+    hw->lpperi.lp_bletimer_div_num = value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw)
+{
+    return hw->lpperi.lp_bletimer_div_num;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, modem_clock_32k_clk_src_t src)
+{
+    hw->lpperi.lp_bletimer_32k_sel = src;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h4/include/hal/modem_lpcon_ll.h

@@ -0,0 +1,97 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H4 MODEM LPCON register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "hal/assert.h"
+#include "modem/modem_lpcon_struct.h"
+#include "hal/modem_clock_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->test_conf.clk_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_div_num = value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw)
+{
+    return hw->coex_lp_clk_conf.clk_coex_lp_div_num;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_coex_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en)
+{
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf_force_on.clk_coex_fo = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
+{
+    hw->rst_conf.rst_coex = 1;
+    hw->rst_conf.rst_coex = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
+{
+    hw->rst_conf.val = 0xf;
+    hw->rst_conf.val = 0;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h4/include/hal/modem_syscon_ll.h

@@ -0,0 +1,372 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H4 MODEM SYSCON register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "hal/assert.h"
+#include "modem/modem_syscon_struct.h"
+#include "hal/modem_clock_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en)
+{
+    hw->test_conf.clk_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_pwdet_sar_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.pwdet_sar_clock_ena = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_set_pwdet_clk_div_num(modem_syscon_dev_t *hw, uint32_t div)
+{
+    hw->clk_conf.pwdet_clk_div_num = div;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_clk_tx_dac_inv(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_tx_dac_inv_ena = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_clk_rx_dac_inv(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_rx_adc_inv_ena = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_clk_pwdet_adc_inv(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_pwdet_adc_inv_ena = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_data_dump_mux = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_etm_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_zb_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_zbmac_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_modem_sec_en = en;
+    hw->clk_conf.clk_modem_sec_ecb_en = en;
+    hw->clk_conf.clk_modem_sec_ccm_en = en;
+    hw->clk_conf.clk_modem_sec_bah_en = en;
+    hw->clk_conf.clk_modem_sec_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_ble_timer_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_data_dump_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_etm_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_apb_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on_2.clk_zbmac_apb_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_mac_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on_2.clk_zbmac_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_modem_sec_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_ble_timer_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_data_dump_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_ieee802154_icg_bitmap(modem_syscon_dev_t *hw)
+{
+    return hw->clk_conf_power_st.clk_zb_st_map;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_set_ieee802154_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
+{
+    hw->clk_conf_power_st.clk_zb_st_map = bitmap;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_fe_icg_bitmap(modem_syscon_dev_t *hw)
+{
+    return hw->clk_conf_power_st.clk_fe_st_map;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_set_fe_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
+{
+    hw->clk_conf_power_st.clk_fe_st_map = bitmap;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_bt_icg_bitmap(modem_syscon_dev_t *hw)
+{
+    return hw->clk_conf_power_st.clk_bt_st_map;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_set_bt_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
+{
+    hw->clk_conf_power_st.clk_bt_st_map = bitmap;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_modem_periph_icg_bitmap(modem_syscon_dev_t *hw)
+{
+    return hw->clk_conf_power_st.clk_modem_peri_st_map;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_set_modem_periph_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
+{
+    hw->clk_conf_power_st.clk_modem_peri_st_map = bitmap;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_modem_apb_icg_bitmap(modem_syscon_dev_t *hw)
+{
+    return hw->clk_conf_power_st.clk_modem_apb_st_map;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_set_modem_apb_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
+{
+    hw->clk_conf_power_st.clk_modem_apb_st_map = bitmap;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_fe = 1;
+    hw->modem_rst_conf.rst_fe = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btmac_apb = 1;
+    hw->modem_rst_conf.rst_btmac_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btmac = 1;
+    hw->modem_rst_conf.rst_btmac = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btbb_apb = 1;
+    hw->modem_rst_conf.rst_btbb_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btbb = 1;
+    hw->modem_rst_conf.rst_btbb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_etm = 1;
+    hw->modem_rst_conf.rst_etm = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_zbmac_apb = 1;
+    hw->modem_rst_conf.rst_zbmac_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_zbmac = 1;
+    hw->modem_rst_conf.rst_zbmac = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_modem_ecb = 1;
+    hw->modem_rst_conf.rst_modem_ccm = 1;
+    hw->modem_rst_conf.rst_modem_bah = 1;
+    hw->modem_rst_conf.rst_modem_sec = 1;
+    hw->modem_rst_conf.rst_modem_ecb = 0;
+    hw->modem_rst_conf.rst_modem_ccm = 0;
+    hw->modem_rst_conf.rst_modem_bah = 0;
+    hw->modem_rst_conf.rst_modem_sec = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_ble_timer = 1;
+    hw->modem_rst_conf.rst_ble_timer = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_data_dump = 1;
+    hw->modem_rst_conf.rst_data_dump = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.val = 0xffffffff;
+    hw->modem_rst_conf.val = 0;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
+{
+    if(en){
+        hw->clk_conf1.val = hw->clk_conf1.val | mask;
+    } else {
+        hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
+    }
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_txlogain_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_txlogain_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_16m_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_32m_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_32m_en = en;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_sdm_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_adc_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_bt_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_bb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_btbb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_btmac_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_bt_apb_en = en;
+    hw->clk_conf1.clk_btbb_en = en;
+    hw->clk_conf1.clk_btmac_en = en;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw)
+{
+    return hw->date.val;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h4/modem_clock_hal.c

@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The HAL layer for MODEM CLOCK (ESP32-H4 specific part)
+#include <stdbool.h>
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "hal/modem_clock_hal.h"
+#include "hal/lp_clkrst_ll.h"
+#include "hal/modem_clock_types.h"
+#include "hal/assert.h"
+
+void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable);
+}
+
+void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable);
+    modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable);
+}
+
+void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider)
+{
+    lp_clkrst_ll_set_ble_rtc_timer_divisor_value(&LP_CLKRST, divider);
+}
+
+void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    // No clock gate on ESP32-H4
+}
+
+void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal)
+{
+    lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, false);
+}
+
+void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
+{
+    HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
+
+    switch (src)
+    {
+    case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
+        lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
+        lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
+        lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_EXT32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
+        break;
+    default:
+        HAL_ASSERT(0);
+    }
+}
+
+void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal)
+{
+    modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false);
+}
+
+void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
+{
+    HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
+
+    switch (src)
+    {
+    case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
+        modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
+        modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
+        modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_EXT32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
+        break;
+    default:
+        HAL_ASSERT(0);
+    }
+}

components/hal/include/hal/modem_clock_types.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,6 +35,12 @@ typedef enum {
     MODEM_CLOCK_LPCLK_SRC_MAX
 } modem_clock_lpclk_src_t;
 
+typedef enum {
+    MODEM_CLOCK_32K_SRC_XTAL32K = 0,
+    MODEM_CLOCK_32K_SRC_RC32K   = 1,
+    MODEM_CLOCK_32K_SRC_EXT32K  = 2
+} modem_clock_32k_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h4/include/modem/modem_lpcon_reg.h

@@ -0,0 +1,431 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "modem/reg_base.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MODEM_LPCON_TEST_CONF_REG register*/
+#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
+/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_CLK_EN    (BIT(0))
+#define MODEM_LPCON_CLK_EN_M  (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
+#define MODEM_LPCON_CLK_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_EN_S  0
+
+/* MODEM_LPCON_LP_TIMER_CONF_REG register*/
+#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW    (BIT(0))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S  0
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST    (BIT(1))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S  1
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL    (BIT(2))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S  2
+/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K    (BIT(3))
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M  (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S)
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S  3
+/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM    0x00000FFFU
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M  (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V  0x00000FFFU
+#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S  4
+
+/* MODEM_LPCON_COEX_LP_CLK_CONF_REG register*/
+#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
+/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW    (BIT(0))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S  0
+/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST    (BIT(1))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S  1
+/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL    (BIT(2))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M  (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S  2
+/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K    (BIT(3))
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M  (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S  3
+/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM    0x00000FFFU
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M  (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V  0x00000FFFU
+#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S  4
+
+/* MODEM_LPCON_WIFI_LP_CLK_CONF_REG register*/
+#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW    (BIT(0))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S  0
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST    (BIT(1))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S  1
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL    (BIT(2))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S  2
+/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K    (BIT(3))
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M  (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S  3
+/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM    0x00000FFFU
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M  (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V  0x00000FFFU
+#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S  4
+
+/* MODEM_LPCON_MODEM_SRC_CLK_CONF_REG register*/
+#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
+/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W; bitpos: [1:0]; default: 0;*/
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE    0x00000003U
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M  (MODEM_LPCON_CLK_MODEM_AON_FORCE_V << MODEM_LPCON_CLK_MODEM_AON_FORCE_S)
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V  0x00000003U
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S  0
+/* MODEM_LPCON_MODEM_PWR_32K_FO : R/W; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_MODEM_PWR_32K_FO    (BIT(2))
+#define MODEM_LPCON_MODEM_PWR_32K_FO_M  (MODEM_LPCON_MODEM_PWR_32K_FO_V << MODEM_LPCON_MODEM_PWR_32K_FO_S)
+#define MODEM_LPCON_MODEM_PWR_32K_FO_V  0x00000001U
+#define MODEM_LPCON_MODEM_PWR_32K_FO_S  2
+/* MODEM_LPCON_MODEM_PWR_FOSC_FO : R/W; bitpos: [3]; default: 0;*/
+#define MODEM_LPCON_MODEM_PWR_FOSC_FO    (BIT(3))
+#define MODEM_LPCON_MODEM_PWR_FOSC_FO_M  (MODEM_LPCON_MODEM_PWR_FOSC_FO_V << MODEM_LPCON_MODEM_PWR_FOSC_FO_S)
+#define MODEM_LPCON_MODEM_PWR_FOSC_FO_V  0x00000001U
+#define MODEM_LPCON_MODEM_PWR_FOSC_FO_S  3
+/* MODEM_LPCON_MODEM_PWR_SOSC_FO : R/W; bitpos: [4]; default: 0;*/
+#define MODEM_LPCON_MODEM_PWR_SOSC_FO    (BIT(4))
+#define MODEM_LPCON_MODEM_PWR_SOSC_FO_M  (MODEM_LPCON_MODEM_PWR_SOSC_FO_V << MODEM_LPCON_MODEM_PWR_SOSC_FO_S)
+#define MODEM_LPCON_MODEM_PWR_SOSC_FO_V  0x00000001U
+#define MODEM_LPCON_MODEM_PWR_SOSC_FO_S  4
+/* MODEM_LPCON_MODEM_PWR_XTAL_FO : R/W; bitpos: [5]; default: 0;*/
+#define MODEM_LPCON_MODEM_PWR_XTAL_FO    (BIT(5))
+#define MODEM_LPCON_MODEM_PWR_XTAL_FO_M  (MODEM_LPCON_MODEM_PWR_XTAL_FO_V << MODEM_LPCON_MODEM_PWR_XTAL_FO_S)
+#define MODEM_LPCON_MODEM_PWR_XTAL_FO_V  0x00000001U
+#define MODEM_LPCON_MODEM_PWR_XTAL_FO_S  5
+
+/* MODEM_LPCON_MODEM_32K_CLK_CONF_REG register*/
+#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
+/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0;*/
+#define MODEM_LPCON_CLK_MODEM_32K_SEL    0x00000003U
+#define MODEM_LPCON_CLK_MODEM_32K_SEL_M  (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S)
+#define MODEM_LPCON_CLK_MODEM_32K_SEL_V  0x00000003U
+#define MODEM_LPCON_CLK_MODEM_32K_SEL_S  0
+
+/* MODEM_LPCON_CLK_CONF_REG register*/
+#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
+/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_EN    (BIT(0))
+#define MODEM_LPCON_CLK_WIFIPWR_EN_M  (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S)
+#define MODEM_LPCON_CLK_WIFIPWR_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_EN_S  0
+/* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_EN    (BIT(1))
+#define MODEM_LPCON_CLK_COEX_EN_M  (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
+#define MODEM_LPCON_CLK_COEX_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_EN_S  1
+/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_CLK_I2C_MST_EN    (BIT(2))
+#define MODEM_LPCON_CLK_I2C_MST_EN_M  (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
+#define MODEM_LPCON_CLK_I2C_MST_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_I2C_MST_EN_S  2
+/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_TIMER_EN    (BIT(3))
+#define MODEM_LPCON_CLK_LP_TIMER_EN_M  (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S)
+#define MODEM_LPCON_CLK_LP_TIMER_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_EN_S  3
+/* MODEM_LPCON_CLK_ANA_XTAL_EN : R/W; bitpos: [4]; default: 1;*/
+#define MODEM_LPCON_CLK_ANA_XTAL_EN    (BIT(4))
+#define MODEM_LPCON_CLK_ANA_XTAL_EN_M  (MODEM_LPCON_CLK_ANA_XTAL_EN_V << MODEM_LPCON_CLK_ANA_XTAL_EN_S)
+#define MODEM_LPCON_CLK_ANA_XTAL_EN_V  0x00000001U
+#define MODEM_LPCON_CLK_ANA_XTAL_EN_S  4
+
+/* MODEM_LPCON_CLK_CONF_FORCE_ON_REG register*/
+#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
+/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_FO    (BIT(0))
+#define MODEM_LPCON_CLK_WIFIPWR_FO_M  (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S)
+#define MODEM_LPCON_CLK_WIFIPWR_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_WIFIPWR_FO_S  0
+/* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_FO    (BIT(1))
+#define MODEM_LPCON_CLK_COEX_FO_M  (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
+#define MODEM_LPCON_CLK_COEX_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_COEX_FO_S  1
+/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_CLK_I2C_MST_FO    (BIT(2))
+#define MODEM_LPCON_CLK_I2C_MST_FO_M  (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
+#define MODEM_LPCON_CLK_I2C_MST_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_I2C_MST_FO_S  2
+/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_TIMER_FO    (BIT(3))
+#define MODEM_LPCON_CLK_LP_TIMER_FO_M  (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S)
+#define MODEM_LPCON_CLK_LP_TIMER_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_LP_TIMER_FO_S  3
+/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W; bitpos: [4]; default: 0;*/
+#define MODEM_LPCON_CLK_AGC_MEM_FO    (BIT(4))
+#define MODEM_LPCON_CLK_AGC_MEM_FO_M  (MODEM_LPCON_CLK_AGC_MEM_FO_V << MODEM_LPCON_CLK_AGC_MEM_FO_S)
+#define MODEM_LPCON_CLK_AGC_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_AGC_MEM_FO_S  4
+/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W; bitpos: [5]; default: 0;*/
+#define MODEM_LPCON_CLK_PBUS_MEM_FO    (BIT(5))
+#define MODEM_LPCON_CLK_PBUS_MEM_FO_M  (MODEM_LPCON_CLK_PBUS_MEM_FO_V << MODEM_LPCON_CLK_PBUS_MEM_FO_S)
+#define MODEM_LPCON_CLK_PBUS_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_PBUS_MEM_FO_S  5
+/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W; bitpos: [6]; default: 0;*/
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO    (BIT(6))
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M  (MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V << MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S)
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S  6
+/* MODEM_LPCON_CLK_AGC_DCMEM_FO : R/W; bitpos: [7]; default: 0;*/
+#define MODEM_LPCON_CLK_AGC_DCMEM_FO    (BIT(7))
+#define MODEM_LPCON_CLK_AGC_DCMEM_FO_M  (MODEM_LPCON_CLK_AGC_DCMEM_FO_V << MODEM_LPCON_CLK_AGC_DCMEM_FO_S)
+#define MODEM_LPCON_CLK_AGC_DCMEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_AGC_DCMEM_FO_S  7
+/* MODEM_LPCON_CLK_BCMEM_FO : R/W; bitpos: [8]; default: 0;*/
+#define MODEM_LPCON_CLK_BCMEM_FO    (BIT(8))
+#define MODEM_LPCON_CLK_BCMEM_FO_M  (MODEM_LPCON_CLK_BCMEM_FO_V << MODEM_LPCON_CLK_BCMEM_FO_S)
+#define MODEM_LPCON_CLK_BCMEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_BCMEM_FO_S  8
+/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W; bitpos: [9]; default: 0;*/
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO    (BIT(9))
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M  (MODEM_LPCON_CLK_I2C_MST_MEM_FO_V << MODEM_LPCON_CLK_I2C_MST_MEM_FO_S)
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V  0x00000001U
+#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S  9
+
+/* MODEM_LPCON_CLK_CONF_POWER_ST_REG register*/
+#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
+/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0;*/
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M  (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S  16
+/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0;*/
+#define MODEM_LPCON_CLK_COEX_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_COEX_ST_MAP_M  (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S)
+#define MODEM_LPCON_CLK_COEX_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_COEX_ST_MAP_S  20
+/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0;*/
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M  (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S  24
+/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0;*/
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP    0x0000000FU
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M  (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S)
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V  0x0000000FU
+#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S  28
+
+/* MODEM_LPCON_RST_CONF_REG register*/
+#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
+/* MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_RST_WIFIPWR    (BIT(0))
+#define MODEM_LPCON_RST_WIFIPWR_M  (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S)
+#define MODEM_LPCON_RST_WIFIPWR_V  0x00000001U
+#define MODEM_LPCON_RST_WIFIPWR_S  0
+/* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0;*/
+#define MODEM_LPCON_RST_COEX    (BIT(1))
+#define MODEM_LPCON_RST_COEX_M  (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
+#define MODEM_LPCON_RST_COEX_V  0x00000001U
+#define MODEM_LPCON_RST_COEX_S  1
+/* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_RST_I2C_MST    (BIT(2))
+#define MODEM_LPCON_RST_I2C_MST_M  (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
+#define MODEM_LPCON_RST_I2C_MST_V  0x00000001U
+#define MODEM_LPCON_RST_I2C_MST_S  2
+/* MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0;*/
+#define MODEM_LPCON_RST_LP_TIMER    (BIT(3))
+#define MODEM_LPCON_RST_LP_TIMER_M  (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S)
+#define MODEM_LPCON_RST_LP_TIMER_V  0x00000001U
+#define MODEM_LPCON_RST_LP_TIMER_S  3
+/* MODEM_LPCON_RST_DCMEM : WO; bitpos: [4]; default: 0;*/
+#define MODEM_LPCON_RST_DCMEM    (BIT(4))
+#define MODEM_LPCON_RST_DCMEM_M  (MODEM_LPCON_RST_DCMEM_V << MODEM_LPCON_RST_DCMEM_S)
+#define MODEM_LPCON_RST_DCMEM_V  0x00000001U
+#define MODEM_LPCON_RST_DCMEM_S  4
+/* MODEM_LPCON_RST_MODEM_POWER_CTRL : WO; bitpos: [5]; default: 0;*/
+#define MODEM_LPCON_RST_MODEM_POWER_CTRL    (BIT(5))
+#define MODEM_LPCON_RST_MODEM_POWER_CTRL_M  (MODEM_LPCON_RST_MODEM_POWER_CTRL_V << MODEM_LPCON_RST_MODEM_POWER_CTRL_S)
+#define MODEM_LPCON_RST_MODEM_POWER_CTRL_V  0x00000001U
+#define MODEM_LPCON_RST_MODEM_POWER_CTRL_S  5
+
+/* MODEM_LPCON_TICK_CONF_REG register*/
+#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
+/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W; bitpos: [5:0]; default: 39;*/
+#define MODEM_LPCON_MODEM_PWR_TICK_TARGET    0x0000003FU
+#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M  (MODEM_LPCON_MODEM_PWR_TICK_TARGET_V << MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)
+#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V  0x0000003FU
+#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S  0
+
+/* MODEM_LPCON_MEM_CONF_REG register*/
+#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2c)
+/* MODEM_LPCON_DC_MEM_MODE : R/W; bitpos: [2:0]; default: 0;*/
+#define MODEM_LPCON_DC_MEM_MODE    0x00000007U
+#define MODEM_LPCON_DC_MEM_MODE_M  (MODEM_LPCON_DC_MEM_MODE_V << MODEM_LPCON_DC_MEM_MODE_S)
+#define MODEM_LPCON_DC_MEM_MODE_V  0x00000007U
+#define MODEM_LPCON_DC_MEM_MODE_S  0
+/* MODEM_LPCON_DC_MEM_FORCE : R/W; bitpos: [3]; default: 1;*/
+#define MODEM_LPCON_DC_MEM_FORCE    (BIT(3))
+#define MODEM_LPCON_DC_MEM_FORCE_M  (MODEM_LPCON_DC_MEM_FORCE_V << MODEM_LPCON_DC_MEM_FORCE_S)
+#define MODEM_LPCON_DC_MEM_FORCE_V  0x00000001U
+#define MODEM_LPCON_DC_MEM_FORCE_S  3
+/* MODEM_LPCON_AGC_MEM_MODE : R/W; bitpos: [6:4]; default: 0;*/
+#define MODEM_LPCON_AGC_MEM_MODE    0x00000007U
+#define MODEM_LPCON_AGC_MEM_MODE_M  (MODEM_LPCON_AGC_MEM_MODE_V << MODEM_LPCON_AGC_MEM_MODE_S)
+#define MODEM_LPCON_AGC_MEM_MODE_V  0x00000007U
+#define MODEM_LPCON_AGC_MEM_MODE_S  4
+/* MODEM_LPCON_AGC_MEM_FORCE : R/W; bitpos: [7]; default: 1;*/
+#define MODEM_LPCON_AGC_MEM_FORCE    (BIT(7))
+#define MODEM_LPCON_AGC_MEM_FORCE_M  (MODEM_LPCON_AGC_MEM_FORCE_V << MODEM_LPCON_AGC_MEM_FORCE_S)
+#define MODEM_LPCON_AGC_MEM_FORCE_V  0x00000001U
+#define MODEM_LPCON_AGC_MEM_FORCE_S  7
+/* MODEM_LPCON_PBUS_MEM_MODE : R/W; bitpos: [10:8]; default: 0;*/
+#define MODEM_LPCON_PBUS_MEM_MODE    0x00000007U
+#define MODEM_LPCON_PBUS_MEM_MODE_M  (MODEM_LPCON_PBUS_MEM_MODE_V << MODEM_LPCON_PBUS_MEM_MODE_S)
+#define MODEM_LPCON_PBUS_MEM_MODE_V  0x00000007U
+#define MODEM_LPCON_PBUS_MEM_MODE_S  8
+/* MODEM_LPCON_PBUS_MEM_FORCE : R/W; bitpos: [11]; default: 1;*/
+#define MODEM_LPCON_PBUS_MEM_FORCE    (BIT(11))
+#define MODEM_LPCON_PBUS_MEM_FORCE_M  (MODEM_LPCON_PBUS_MEM_FORCE_V << MODEM_LPCON_PBUS_MEM_FORCE_S)
+#define MODEM_LPCON_PBUS_MEM_FORCE_V  0x00000001U
+#define MODEM_LPCON_PBUS_MEM_FORCE_S  11
+/* MODEM_LPCON_BC_MEM_MODE : R/W; bitpos: [14:12]; default: 0;*/
+#define MODEM_LPCON_BC_MEM_MODE    0x00000007U
+#define MODEM_LPCON_BC_MEM_MODE_M  (MODEM_LPCON_BC_MEM_MODE_V << MODEM_LPCON_BC_MEM_MODE_S)
+#define MODEM_LPCON_BC_MEM_MODE_V  0x00000007U
+#define MODEM_LPCON_BC_MEM_MODE_S  12
+/* MODEM_LPCON_BC_MEM_FORCE : R/W; bitpos: [15]; default: 1;*/
+#define MODEM_LPCON_BC_MEM_FORCE    (BIT(15))
+#define MODEM_LPCON_BC_MEM_FORCE_M  (MODEM_LPCON_BC_MEM_FORCE_V << MODEM_LPCON_BC_MEM_FORCE_S)
+#define MODEM_LPCON_BC_MEM_FORCE_V  0x00000001U
+#define MODEM_LPCON_BC_MEM_FORCE_S  15
+/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W; bitpos: [18:16]; default: 0;*/
+#define MODEM_LPCON_I2C_MST_MEM_MODE    0x00000007U
+#define MODEM_LPCON_I2C_MST_MEM_MODE_M  (MODEM_LPCON_I2C_MST_MEM_MODE_V << MODEM_LPCON_I2C_MST_MEM_MODE_S)
+#define MODEM_LPCON_I2C_MST_MEM_MODE_V  0x00000007U
+#define MODEM_LPCON_I2C_MST_MEM_MODE_S  16
+/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W; bitpos: [19]; default: 1;*/
+#define MODEM_LPCON_I2C_MST_MEM_FORCE    (BIT(19))
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_M  (MODEM_LPCON_I2C_MST_MEM_FORCE_V << MODEM_LPCON_I2C_MST_MEM_FORCE_S)
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_V  0x00000001U
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_S  19
+/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W; bitpos: [22:20]; default: 0;*/
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE    0x00000007U
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M  (MODEM_LPCON_CHAN_FREQ_MEM_MODE_V << MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V  0x00000007U
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S  20
+/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W; bitpos: [23]; default: 1;*/
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE    (BIT(23))
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M  (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S)
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V  0x00000001U
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S  23
+
+/* MODEM_LPCON_MEM_RF1_AUX_CTRL_REG register*/
+#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30)
+/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W; bitpos: [31:0]; default: 10320;*/
+#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL    0xFFFFFFFFU
+#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M  (MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)
+#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V  0xFFFFFFFFU
+#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S  0
+
+/* MODEM_LPCON_MEM_RF2_AUX_CTRL_REG register*/
+#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34)
+/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;*/
+#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL    0xFFFFFFFFU
+#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M  (MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)
+#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V  0xFFFFFFFFU
+#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S  0
+
+/* MODEM_LPCON_APB_MEM_SEL_REG register*/
+#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38)
+/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W; bitpos: [0]; default: 0;*/
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN    (BIT(0))
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M  (MODEM_LPCON_CHAN_FREQ_MEM_EN_V << MODEM_LPCON_CHAN_FREQ_MEM_EN_S)
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V  0x00000001U
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S  0
+/* MODEM_LPCON_PBUS_MEM_EN : R/W; bitpos: [1]; default: 0;*/
+#define MODEM_LPCON_PBUS_MEM_EN    (BIT(1))
+#define MODEM_LPCON_PBUS_MEM_EN_M  (MODEM_LPCON_PBUS_MEM_EN_V << MODEM_LPCON_PBUS_MEM_EN_S)
+#define MODEM_LPCON_PBUS_MEM_EN_V  0x00000001U
+#define MODEM_LPCON_PBUS_MEM_EN_S  1
+/* MODEM_LPCON_AGC_MEM_EN : R/W; bitpos: [2]; default: 0;*/
+#define MODEM_LPCON_AGC_MEM_EN    (BIT(2))
+#define MODEM_LPCON_AGC_MEM_EN_M  (MODEM_LPCON_AGC_MEM_EN_V << MODEM_LPCON_AGC_MEM_EN_S)
+#define MODEM_LPCON_AGC_MEM_EN_V  0x00000001U
+#define MODEM_LPCON_AGC_MEM_EN_S  2
+/* MODEM_LPCON_PWR_MEM_BASE : R/W; bitpos: [18:3]; default: 0;*/
+#define MODEM_LPCON_PWR_MEM_BASE    0x0000FFFFU
+#define MODEM_LPCON_PWR_MEM_BASE_M  (MODEM_LPCON_PWR_MEM_BASE_V << MODEM_LPCON_PWR_MEM_BASE_S)
+#define MODEM_LPCON_PWR_MEM_BASE_V  0x0000FFFFU
+#define MODEM_LPCON_PWR_MEM_BASE_S  3
+
+/* MODEM_LPCON_DCMEM_VALID_0_REG register*/
+#define MODEM_LPCON_DCMEM_VALID_0_REG (DR_REG_MODEM_LPCON_BASE + 0x3c)
+/* MODEM_LPCON_DCMEM_VALID_0 : RO; bitpos: [31:0]; default: 0;*/
+#define MODEM_LPCON_DCMEM_VALID_0    0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_0_M  (MODEM_LPCON_DCMEM_VALID_0_V << MODEM_LPCON_DCMEM_VALID_0_S)
+#define MODEM_LPCON_DCMEM_VALID_0_V  0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_0_S  0
+
+/* MODEM_LPCON_DCMEM_VALID_1_REG register*/
+#define MODEM_LPCON_DCMEM_VALID_1_REG (DR_REG_MODEM_LPCON_BASE + 0x40)
+/* MODEM_LPCON_DCMEM_VALID_1 : RO; bitpos: [31:0]; default: 0;*/
+#define MODEM_LPCON_DCMEM_VALID_1    0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_1_M  (MODEM_LPCON_DCMEM_VALID_1_V << MODEM_LPCON_DCMEM_VALID_1_S)
+#define MODEM_LPCON_DCMEM_VALID_1_V  0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_1_S  0
+
+/* MODEM_LPCON_DCMEM_VALID_2_REG register*/
+#define MODEM_LPCON_DCMEM_VALID_2_REG (DR_REG_MODEM_LPCON_BASE + 0x44)
+/* MODEM_LPCON_DCMEM_VALID_2 : RO; bitpos: [31:0]; default: 0;*/
+#define MODEM_LPCON_DCMEM_VALID_2    0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_2_M  (MODEM_LPCON_DCMEM_VALID_2_V << MODEM_LPCON_DCMEM_VALID_2_S)
+#define MODEM_LPCON_DCMEM_VALID_2_V  0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_2_S  0
+
+/* MODEM_LPCON_DCMEM_VALID_3_REG register*/
+#define MODEM_LPCON_DCMEM_VALID_3_REG (DR_REG_MODEM_LPCON_BASE + 0x48)
+/* MODEM_LPCON_DCMEM_VALID_3 : RO; bitpos: [31:0]; default: 0;*/
+#define MODEM_LPCON_DCMEM_VALID_3    0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_3_M  (MODEM_LPCON_DCMEM_VALID_3_V << MODEM_LPCON_DCMEM_VALID_3_S)
+#define MODEM_LPCON_DCMEM_VALID_3_V  0xFFFFFFFFU
+#define MODEM_LPCON_DCMEM_VALID_3_S  0
+
+/* MODEM_LPCON_DATE_REG register*/
+#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x4c)
+/* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 37823024;*/
+#define MODEM_LPCON_DATE    0x0FFFFFFFU
+#define MODEM_LPCON_DATE_M  (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
+#define MODEM_LPCON_DATE_V  0x0FFFFFFFU
+#define MODEM_LPCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h4/include/modem/modem_lpcon_struct.h

@@ -0,0 +1,341 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/* Type of test_conf register*/
+typedef union {
+    struct {
+        /* clk_en : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_en: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} modem_lpcon_test_conf_reg_t;
+
+/* Type of lp_timer_conf register*/
+typedef union {
+    struct {
+        /* clk_lp_timer_sel_osc_slow : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_lp_timer_sel_osc_slow: 1;
+        /* clk_lp_timer_sel_osc_fast : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_lp_timer_sel_osc_fast: 1;
+        /* clk_lp_timer_sel_xtal : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_lp_timer_sel_xtal: 1;
+        /* clk_lp_timer_sel_xtal32k : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_lp_timer_sel_xtal32k: 1;
+        /* clk_lp_timer_div_num : R/W; bitpos: [15:4]; default: 0;*/
+        uint32_t clk_lp_timer_div_num: 12;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} modem_lpcon_lp_timer_conf_reg_t;
+
+/* Type of coex_lp_clk_conf register*/
+typedef union {
+    struct {
+        /* clk_coex_lp_sel_osc_slow : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_coex_lp_sel_osc_slow: 1;
+        /* clk_coex_lp_sel_osc_fast : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_coex_lp_sel_osc_fast: 1;
+        /* clk_coex_lp_sel_xtal : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_coex_lp_sel_xtal: 1;
+        /* clk_coex_lp_sel_xtal32k : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_coex_lp_sel_xtal32k: 1;
+        /* clk_coex_lp_div_num : R/W; bitpos: [15:4]; default: 0;*/
+        uint32_t clk_coex_lp_div_num: 12;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} modem_lpcon_coex_lp_clk_conf_reg_t;
+
+/* Type of wifi_lp_clk_conf register*/
+typedef union {
+    struct {
+        /* clk_wifipwr_lp_sel_osc_slow : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_wifipwr_lp_sel_osc_slow: 1;
+        /* clk_wifipwr_lp_sel_osc_fast : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_wifipwr_lp_sel_osc_fast: 1;
+        /* clk_wifipwr_lp_sel_xtal : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_wifipwr_lp_sel_xtal: 1;
+        /* clk_wifipwr_lp_sel_xtal32k : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_wifipwr_lp_sel_xtal32k: 1;
+        /* clk_wifipwr_lp_div_num : R/W; bitpos: [15:4]; default: 0;*/
+        uint32_t clk_wifipwr_lp_div_num: 12;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} modem_lpcon_wifi_lp_clk_conf_reg_t;
+
+/* Type of modem_src_clk_conf register*/
+typedef union {
+    struct {
+        /* clk_modem_aon_force : R/W; bitpos: [1:0]; default: 0;*/
+        uint32_t clk_modem_aon_force: 2;
+        /* modem_pwr_32k_fo : R/W; bitpos: [2]; default: 0;*/
+        uint32_t modem_pwr_32k_fo: 1;
+        /* modem_pwr_fosc_fo : R/W; bitpos: [3]; default: 0;*/
+        uint32_t modem_pwr_fosc_fo: 1;
+        /* modem_pwr_sosc_fo : R/W; bitpos: [4]; default: 0;*/
+        uint32_t modem_pwr_sosc_fo: 1;
+        /* modem_pwr_xtal_fo : R/W; bitpos: [5]; default: 0;*/
+        uint32_t modem_pwr_xtal_fo: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} modem_lpcon_modem_src_clk_conf_reg_t;
+
+/* Type of modem_32k_clk_conf register*/
+typedef union {
+    struct {
+        /* clk_modem_32k_sel : R/W; bitpos: [1:0]; default: 0;*/
+        uint32_t clk_modem_32k_sel: 2;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} modem_lpcon_modem_32k_clk_conf_reg_t;
+
+/* Type of clk_conf register*/
+typedef union {
+    struct {
+        /* clk_wifipwr_en : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_wifipwr_en: 1;
+        /* clk_coex_en : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_coex_en: 1;
+        /* clk_i2c_mst_en : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_i2c_mst_en: 1;
+        /* clk_lp_timer_en : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_lp_timer_en: 1;
+        /* clk_ana_xtal_en : R/W; bitpos: [4]; default: 1;*/
+        uint32_t clk_ana_xtal_en: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} modem_lpcon_clk_conf_reg_t;
+
+/* Type of clk_conf_force_on register*/
+typedef union {
+    struct {
+        /* clk_wifipwr_fo : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_wifipwr_fo: 1;
+        /* clk_coex_fo : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_coex_fo: 1;
+        /* clk_i2c_mst_fo : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_i2c_mst_fo: 1;
+        /* clk_lp_timer_fo : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_lp_timer_fo: 1;
+        /* clk_agc_mem_fo : R/W; bitpos: [4]; default: 0;*/
+        uint32_t clk_agc_mem_fo: 1;
+        /* clk_pbus_mem_fo : R/W; bitpos: [5]; default: 0;*/
+        uint32_t clk_pbus_mem_fo: 1;
+        /* clk_chan_freq_mem_fo : R/W; bitpos: [6]; default: 0;*/
+        uint32_t clk_chan_freq_mem_fo: 1;
+        /* clk_agc_dcmem_fo : R/W; bitpos: [7]; default: 0;*/
+        uint32_t clk_agc_dcmem_fo: 1;
+        /* clk_bcmem_fo : R/W; bitpos: [8]; default: 0;*/
+        uint32_t clk_bcmem_fo: 1;
+        /* clk_i2c_mst_mem_fo : R/W; bitpos: [9]; default: 0;*/
+        uint32_t clk_i2c_mst_mem_fo: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} modem_lpcon_clk_conf_force_on_reg_t;
+
+/* Type of clk_conf_power_st register*/
+typedef union {
+    struct {
+        uint32_t reserved_0: 16;
+        /* clk_wifipwr_st_map : R/W; bitpos: [19:16]; default: 0;*/
+        uint32_t clk_wifipwr_st_map: 4;
+        /* clk_coex_st_map : R/W; bitpos: [23:20]; default: 0;*/
+        uint32_t clk_coex_st_map: 4;
+        /* clk_i2c_mst_st_map : R/W; bitpos: [27:24]; default: 0;*/
+        uint32_t clk_i2c_mst_st_map: 4;
+        /* clk_lp_apb_st_map : R/W; bitpos: [31:28]; default: 0;*/
+        uint32_t clk_lp_apb_st_map: 4;
+    };
+    uint32_t val;
+} modem_lpcon_clk_conf_power_st_reg_t;
+
+/* Type of rst_conf register*/
+typedef union {
+    struct {
+        /* rst_wifipwr : WO; bitpos: [0]; default: 0;*/
+        uint32_t rst_wifipwr: 1;
+        /* rst_coex : WO; bitpos: [1]; default: 0;*/
+        uint32_t rst_coex: 1;
+        /* rst_i2c_mst : WO; bitpos: [2]; default: 0;*/
+        uint32_t rst_i2c_mst: 1;
+        /* rst_lp_timer : WO; bitpos: [3]; default: 0;*/
+        uint32_t rst_lp_timer: 1;
+        /* rst_dcmem : WO; bitpos: [4]; default: 0;*/
+        uint32_t rst_dcmem: 1;
+        /* rst_modem_power_ctrl : WO; bitpos: [5]; default: 0;*/
+        uint32_t rst_modem_power_ctrl: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} modem_lpcon_rst_conf_reg_t;
+
+/* Type of tick_conf register*/
+typedef union {
+    struct {
+        /* modem_pwr_tick_target : R/W; bitpos: [5:0]; default: 39;*/
+        uint32_t modem_pwr_tick_target: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} modem_lpcon_tick_conf_reg_t;
+
+/* Type of mem_conf register*/
+typedef union {
+    struct {
+        /* dc_mem_mode : R/W; bitpos: [2:0]; default: 0;*/
+        uint32_t dc_mem_mode: 3;
+        /* dc_mem_force : R/W; bitpos: [3]; default: 1;*/
+        uint32_t dc_mem_force: 1;
+        /* agc_mem_mode : R/W; bitpos: [6:4]; default: 0;*/
+        uint32_t agc_mem_mode: 3;
+        /* agc_mem_force : R/W; bitpos: [7]; default: 1;*/
+        uint32_t agc_mem_force: 1;
+        /* pbus_mem_mode : R/W; bitpos: [10:8]; default: 0;*/
+        uint32_t pbus_mem_mode: 3;
+        /* pbus_mem_force : R/W; bitpos: [11]; default: 1;*/
+        uint32_t pbus_mem_force: 1;
+        /* bc_mem_mode : R/W; bitpos: [14:12]; default: 0;*/
+        uint32_t bc_mem_mode: 3;
+        /* bc_mem_force : R/W; bitpos: [15]; default: 1;*/
+        uint32_t bc_mem_force: 1;
+        /* i2c_mst_mem_mode : R/W; bitpos: [18:16]; default: 0;*/
+        uint32_t i2c_mst_mem_mode: 3;
+        /* i2c_mst_mem_force : R/W; bitpos: [19]; default: 1;*/
+        uint32_t i2c_mst_mem_force: 1;
+        /* chan_freq_mem_mode : R/W; bitpos: [22:20]; default: 0;*/
+        uint32_t chan_freq_mem_mode: 3;
+        /* chan_freq_mem_force : R/W; bitpos: [23]; default: 1;*/
+        uint32_t chan_freq_mem_force: 1;
+        uint32_t reserved_24: 8;
+    };
+    uint32_t val;
+} modem_lpcon_mem_conf_reg_t;
+
+/* Type of mem_rf1_aux_ctrl register*/
+typedef union {
+    struct {
+        /* modem_pwr_rf1_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;*/
+        uint32_t modem_pwr_rf1_aux_ctrl: 32;
+    };
+    uint32_t val;
+} modem_lpcon_mem_rf1_aux_ctrl_reg_t;
+
+/* Type of mem_rf2_aux_ctrl register*/
+typedef union {
+    struct {
+        /* modem_pwr_rf2_aux_ctrl : R/W; bitpos: [31:0]; default: 0;*/
+        uint32_t modem_pwr_rf2_aux_ctrl: 32;
+    };
+    uint32_t val;
+} modem_lpcon_mem_rf2_aux_ctrl_reg_t;
+
+/* Type of apb_mem_sel register*/
+typedef union {
+    struct {
+        /* chan_freq_mem_en : R/W; bitpos: [0]; default: 0;*/
+        uint32_t chan_freq_mem_en: 1;
+        /* pbus_mem_en : R/W; bitpos: [1]; default: 0;*/
+        uint32_t pbus_mem_en: 1;
+        /* agc_mem_en : R/W; bitpos: [2]; default: 0;*/
+        uint32_t agc_mem_en: 1;
+        /* pwr_mem_base : R/W; bitpos: [18:3]; default: 0;*/
+        uint32_t pwr_mem_base: 16;
+        uint32_t reserved_19: 13;
+    };
+    uint32_t val;
+} modem_lpcon_apb_mem_sel_reg_t;
+
+/* Type of dcmem_valid_0 register*/
+typedef union {
+    struct {
+        /* dcmem_valid_0 : RO; bitpos: [31:0]; default: 0;*/
+        uint32_t dcmem_valid_0: 32;
+    };
+    uint32_t val;
+} modem_lpcon_dcmem_valid_0_reg_t;
+
+/* Type of dcmem_valid_1 register*/
+typedef union {
+    struct {
+        /* dcmem_valid_1 : RO; bitpos: [31:0]; default: 0;*/
+        uint32_t dcmem_valid_1: 32;
+    };
+    uint32_t val;
+} modem_lpcon_dcmem_valid_1_reg_t;
+
+/* Type of dcmem_valid_2 register*/
+typedef union {
+    struct {
+        /* dcmem_valid_2 : RO; bitpos: [31:0]; default: 0;*/
+        uint32_t dcmem_valid_2: 32;
+    };
+    uint32_t val;
+} modem_lpcon_dcmem_valid_2_reg_t;
+
+/* Type of dcmem_valid_3 register*/
+typedef union {
+    struct {
+        /* dcmem_valid_3 : RO; bitpos: [31:0]; default: 0;*/
+        uint32_t dcmem_valid_3: 32;
+    };
+    uint32_t val;
+} modem_lpcon_dcmem_valid_3_reg_t;
+
+/* Type of date register*/
+typedef union {
+    struct {
+        /* date : R/W; bitpos: [27:0]; default: 37823024;*/
+        uint32_t date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} modem_lpcon_date_reg_t;
+
+typedef struct {
+    volatile modem_lpcon_test_conf_reg_t test_conf;
+    volatile modem_lpcon_lp_timer_conf_reg_t lp_timer_conf;
+    volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf;
+    volatile modem_lpcon_wifi_lp_clk_conf_reg_t wifi_lp_clk_conf;
+    volatile modem_lpcon_modem_src_clk_conf_reg_t modem_src_clk_conf;
+    volatile modem_lpcon_modem_32k_clk_conf_reg_t modem_32k_clk_conf;
+    volatile modem_lpcon_clk_conf_reg_t clk_conf;
+    volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on;
+    volatile modem_lpcon_clk_conf_power_st_reg_t clk_conf_power_st;
+    volatile modem_lpcon_rst_conf_reg_t rst_conf;
+    volatile modem_lpcon_tick_conf_reg_t tick_conf;
+    volatile modem_lpcon_mem_conf_reg_t mem_conf;
+    volatile modem_lpcon_mem_rf1_aux_ctrl_reg_t mem_rf1_aux_ctrl;
+    volatile modem_lpcon_mem_rf2_aux_ctrl_reg_t mem_rf2_aux_ctrl;
+    volatile modem_lpcon_apb_mem_sel_reg_t apb_mem_sel;
+    volatile modem_lpcon_dcmem_valid_0_reg_t dcmem_valid_0;
+    volatile modem_lpcon_dcmem_valid_1_reg_t dcmem_valid_1;
+    volatile modem_lpcon_dcmem_valid_2_reg_t dcmem_valid_2;
+    volatile modem_lpcon_dcmem_valid_3_reg_t dcmem_valid_3;
+    volatile modem_lpcon_date_reg_t date;
+} modem_lpcon_dev_t;
+
+extern modem_lpcon_dev_t MODEM_LPCON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(modem_lpcon_dev_t) == 0x50, "Invalid size of modem_lpcon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h4/include/modem/modem_syscon_reg.h

@@ -0,0 +1,826 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "modem/reg_base.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MODEM_SYSCON_TEST_CONF_REG register */
+#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
+/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
+#define MODEM_SYSCON_CLK_EN    (BIT(0))
+#define MODEM_SYSCON_CLK_EN_M  (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S)
+#define MODEM_SYSCON_CLK_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_EN_S  0
+/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W; bitpos: [1]; default: 0; */
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT    (BIT(1))
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M  (MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V << MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S)
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V  0x00000001U
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S  1
+/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W; bitpos: [2]; default: 0; */
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI    (BIT(2))
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M  (MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V << MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S)
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V  0x00000001U
+#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S  2
+/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W; bitpos: [3]; default: 0; */
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH    (BIT(3))
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M  (MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V << MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S)
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V  0x00000001U
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S  3
+/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W; bitpos: [4]; default: 0; */
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80    (BIT(4))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M  (MODEM_SYSCON_FPGA_DEBUG_CLK80_V << MODEM_SYSCON_FPGA_DEBUG_CLK80_S)
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V  0x00000001U
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S  4
+/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W; bitpos: [5]; default: 0; */
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40    (BIT(5))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M  (MODEM_SYSCON_FPGA_DEBUG_CLK40_V << MODEM_SYSCON_FPGA_DEBUG_CLK40_S)
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V  0x00000001U
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S  5
+/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W; bitpos: [6]; default: 0; */
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20    (BIT(6))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M  (MODEM_SYSCON_FPGA_DEBUG_CLK20_V << MODEM_SYSCON_FPGA_DEBUG_CLK20_S)
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V  0x00000001U
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S  6
+/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W; bitpos: [7]; default: 0; */
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10    (BIT(7))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M  (MODEM_SYSCON_FPGA_DEBUG_CLK10_V << MODEM_SYSCON_FPGA_DEBUG_CLK10_S)
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V  0x00000001U
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S  7
+/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W; bitpos: [8]; default: 1; */
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE    (BIT(8))
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M  (MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V << MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S)
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V  0x00000001U
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S  8
+
+/* MODEM_SYSCON_CLK_CONF_REG register */
+#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
+/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W; bitpos: [0]; default: 0; */
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA    (BIT(0))
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M  (MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V << MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S)
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V  0x00000001U
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S  0
+/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W; bitpos: [8:1]; default: 1; */
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM    0x000000FFU
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M  (MODEM_SYSCON_PWDET_CLK_DIV_NUM_V << MODEM_SYSCON_PWDET_CLK_DIV_NUM_S)
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V  0x000000FFU
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S  1
+/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W; bitpos: [9]; default: 0; */
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA    (BIT(9))
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M  (MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V << MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S)
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V  0x00000001U
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S  9
+/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W; bitpos: [10]; default: 0; */
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA    (BIT(10))
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M  (MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V << MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S)
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V  0x00000001U
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S  10
+/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W; bitpos: [11]; default: 0; */
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA    (BIT(11))
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M  (MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V << MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S)
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V  0x00000001U
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S  11
+/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [12]; default: 0; */
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M    (BIT(12))
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M  (MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V << MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S)
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V  0x00000001U
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S  12
+/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 0; */
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX    (BIT(21))
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M  (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S)
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V  0x00000001U
+#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S  21
+/* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; */
+#define MODEM_SYSCON_CLK_ETM_EN    (BIT(22))
+#define MODEM_SYSCON_CLK_ETM_EN_M  (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S)
+#define MODEM_SYSCON_CLK_ETM_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_ETM_EN_S  22
+/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; */
+#define MODEM_SYSCON_CLK_ZB_APB_EN    (BIT(23))
+#define MODEM_SYSCON_CLK_ZB_APB_EN_M  (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S)
+#define MODEM_SYSCON_CLK_ZB_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZB_APB_EN_S  23
+/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W; bitpos: [24]; default: 0; */
+#define MODEM_SYSCON_CLK_ZBMAC_EN    (BIT(24))
+#define MODEM_SYSCON_CLK_ZBMAC_EN_M  (MODEM_SYSCON_CLK_ZBMAC_EN_V << MODEM_SYSCON_CLK_ZBMAC_EN_S)
+#define MODEM_SYSCON_CLK_ZBMAC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZBMAC_EN_S  24
+/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN    (BIT(25))
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S  25
+/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN    (BIT(26))
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S  26
+/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN    (BIT(27))
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S  27
+/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN    (BIT(28))
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S  28
+/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN    (BIT(29))
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M  (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S  29
+/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN    (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M  (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S)
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S  30
+/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN    (BIT(31))
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M  (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S)
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S  31
+
+/* MODEM_SYSCON_CLK_CONF_FORCE_ON_REG register */
+#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8)
+/* MODEM_SYSCON_CLK_AON_FO : R/W; bitpos: [0]; default: 0; */
+#define MODEM_SYSCON_CLK_AON_FO    (BIT(0))
+#define MODEM_SYSCON_CLK_AON_FO_M  (MODEM_SYSCON_CLK_AON_FO_V << MODEM_SYSCON_CLK_AON_FO_S)
+#define MODEM_SYSCON_CLK_AON_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_AON_FO_S  0
+/* MODEM_SYSCON_CLK_PLL_FO : R/W; bitpos: [1]; default: 0; */
+#define MODEM_SYSCON_CLK_PLL_FO    (BIT(1))
+#define MODEM_SYSCON_CLK_PLL_FO_M  (MODEM_SYSCON_CLK_PLL_FO_V << MODEM_SYSCON_CLK_PLL_FO_S)
+#define MODEM_SYSCON_CLK_PLL_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_PLL_FO_S  1
+/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [2]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO    (BIT(2))
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S  2
+/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO : R/W; bitpos: [3]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO    (BIT(3))
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S  3
+/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO : R/W; bitpos: [4]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO    (BIT(4))
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S  4
+/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO : R/W; bitpos: [5]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO    (BIT(5))
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S  5
+/* MODEM_SYSCON_CLK_MODEM_SEC_APB_FO : R/W; bitpos: [6]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO    (BIT(6))
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S  6
+/* MODEM_SYSCON_CLK_MODEM_SEC_AHB_FO : R/W; bitpos: [7]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_SEC_AHB_FO    (BIT(7))
+#define MODEM_SYSCON_CLK_MODEM_SEC_AHB_FO_M  (MODEM_SYSCON_CLK_MODEM_SEC_AHB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_AHB_FO_S)
+#define MODEM_SYSCON_CLK_MODEM_SEC_AHB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_MODEM_SEC_AHB_FO_S  7
+/* MODEM_SYSCON_CLK_FE_PWDET_ADC_INF_FO : R/W; bitpos: [8]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_INF_FO    (BIT(8))
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_INF_FO_M  (MODEM_SYSCON_CLK_FE_PWDET_ADC_INF_FO_V << MODEM_SYSCON_CLK_FE_PWDET_ADC_INF_FO_S)
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_INF_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_INF_FO_S  8
+/* MODEM_SYSCON_CLK_FE_DAC_INF_FO : R/W; bitpos: [9]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_DAC_INF_FO    (BIT(9))
+#define MODEM_SYSCON_CLK_FE_DAC_INF_FO_M  (MODEM_SYSCON_CLK_FE_DAC_INF_FO_V << MODEM_SYSCON_CLK_FE_DAC_INF_FO_S)
+#define MODEM_SYSCON_CLK_FE_DAC_INF_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_DAC_INF_FO_S  9
+/* MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [10]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_APB_FO    (BIT(10))
+#define MODEM_SYSCON_CLK_FE_APB_FO_M  (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S)
+#define MODEM_SYSCON_CLK_FE_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_APB_FO_S  10
+/* MODEM_SYSCON_CLK_FE_ADC_INF_FO : R/W; bitpos: [11]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_ADC_INF_FO    (BIT(11))
+#define MODEM_SYSCON_CLK_FE_ADC_INF_FO_M  (MODEM_SYSCON_CLK_FE_ADC_INF_FO_V << MODEM_SYSCON_CLK_FE_ADC_INF_FO_S)
+#define MODEM_SYSCON_CLK_FE_ADC_INF_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ADC_INF_FO_S  11
+/* MODEM_SYSCON_CLK_FE_80M_FO : R/W; bitpos: [12]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_80M_FO    (BIT(12))
+#define MODEM_SYSCON_CLK_FE_80M_FO_M  (MODEM_SYSCON_CLK_FE_80M_FO_V << MODEM_SYSCON_CLK_FE_80M_FO_S)
+#define MODEM_SYSCON_CLK_FE_80M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_80M_FO_S  12
+/* MODEM_SYSCON_CLK_FE_40M_FO : R/W; bitpos: [13]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_40M_FO    (BIT(13))
+#define MODEM_SYSCON_CLK_FE_40M_FO_M  (MODEM_SYSCON_CLK_FE_40M_FO_V << MODEM_SYSCON_CLK_FE_40M_FO_S)
+#define MODEM_SYSCON_CLK_FE_40M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_40M_FO_S  13
+/* MODEM_SYSCON_CLK_FE_20M_FO : R/W; bitpos: [14]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_20M_FO    (BIT(14))
+#define MODEM_SYSCON_CLK_FE_20M_FO_M  (MODEM_SYSCON_CLK_FE_20M_FO_V << MODEM_SYSCON_CLK_FE_20M_FO_S)
+#define MODEM_SYSCON_CLK_FE_20M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_20M_FO_S  14
+/* MODEM_SYSCON_CLK_FE_160M_FO : R/W; bitpos: [15]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_160M_FO    (BIT(15))
+#define MODEM_SYSCON_CLK_FE_160M_FO_M  (MODEM_SYSCON_CLK_FE_160M_FO_V << MODEM_SYSCON_CLK_FE_160M_FO_S)
+#define MODEM_SYSCON_CLK_FE_160M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_160M_FO_S  15
+/* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [16]; default: 0; */
+#define MODEM_SYSCON_CLK_ETM_FO    (BIT(16))
+#define MODEM_SYSCON_CLK_ETM_FO_M  (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S)
+#define MODEM_SYSCON_CLK_ETM_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ETM_FO_S  16
+/* MODEM_SYSCON_CLK_ETM_APB_FO : R/W; bitpos: [17]; default: 0; */
+#define MODEM_SYSCON_CLK_ETM_APB_FO    (BIT(17))
+#define MODEM_SYSCON_CLK_ETM_APB_FO_M  (MODEM_SYSCON_CLK_ETM_APB_FO_V << MODEM_SYSCON_CLK_ETM_APB_FO_S)
+#define MODEM_SYSCON_CLK_ETM_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ETM_APB_FO_S  17
+/* MODEM_SYSCON_CLK_DATA_DUMP_MEM_FO : R/W; bitpos: [18]; default: 0; */
+#define MODEM_SYSCON_CLK_DATA_DUMP_MEM_FO    (BIT(18))
+#define MODEM_SYSCON_CLK_DATA_DUMP_MEM_FO_M  (MODEM_SYSCON_CLK_DATA_DUMP_MEM_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_MEM_FO_S)
+#define MODEM_SYSCON_CLK_DATA_DUMP_MEM_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_DATA_DUMP_MEM_FO_S  18
+/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [19]; default: 0; */
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO    (BIT(19))
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M  (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S)
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S  19
+/* MODEM_SYSCON_CLK_BTMAC_FO : R/W; bitpos: [20]; default: 0; */
+#define MODEM_SYSCON_CLK_BTMAC_FO    (BIT(20))
+#define MODEM_SYSCON_CLK_BTMAC_FO_M  (MODEM_SYSCON_CLK_BTMAC_FO_V << MODEM_SYSCON_CLK_BTMAC_FO_S)
+#define MODEM_SYSCON_CLK_BTMAC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BTMAC_FO_S  20
+/* MODEM_SYSCON_CLK_BTMAC_AHB_FO : R/W; bitpos: [21]; default: 0; */
+#define MODEM_SYSCON_CLK_BTMAC_AHB_FO    (BIT(21))
+#define MODEM_SYSCON_CLK_BTMAC_AHB_FO_M  (MODEM_SYSCON_CLK_BTMAC_AHB_FO_V << MODEM_SYSCON_CLK_BTMAC_AHB_FO_S)
+#define MODEM_SYSCON_CLK_BTMAC_AHB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BTMAC_AHB_FO_S  21
+/* MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [22]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_APB_FO    (BIT(22))
+#define MODEM_SYSCON_CLK_BT_APB_FO_M  (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S)
+#define MODEM_SYSCON_CLK_BT_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_APB_FO_S  22
+/* MODEM_SYSCON_CLK_BT_APB_32M_FO : R/W; bitpos: [23]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_APB_32M_FO    (BIT(23))
+#define MODEM_SYSCON_CLK_BT_APB_32M_FO_M  (MODEM_SYSCON_CLK_BT_APB_32M_FO_V << MODEM_SYSCON_CLK_BT_APB_32M_FO_S)
+#define MODEM_SYSCON_CLK_BT_APB_32M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_APB_32M_FO_S  23
+/* MODEM_SYSCON_CLK_BT_8M_FO : R/W; bitpos: [24]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_8M_FO    (BIT(24))
+#define MODEM_SYSCON_CLK_BT_8M_FO_M  (MODEM_SYSCON_CLK_BT_8M_FO_V << MODEM_SYSCON_CLK_BT_8M_FO_S)
+#define MODEM_SYSCON_CLK_BT_8M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_8M_FO_S  24
+/* MODEM_SYSCON_CLK_BT_80M_FO : R/W; bitpos: [25]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_80M_FO    (BIT(25))
+#define MODEM_SYSCON_CLK_BT_80M_FO_M  (MODEM_SYSCON_CLK_BT_80M_FO_V << MODEM_SYSCON_CLK_BT_80M_FO_S)
+#define MODEM_SYSCON_CLK_BT_80M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_80M_FO_S  25
+/* MODEM_SYSCON_CLK_BT_40M_FO : R/W; bitpos: [26]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_40M_FO    (BIT(26))
+#define MODEM_SYSCON_CLK_BT_40M_FO_M  (MODEM_SYSCON_CLK_BT_40M_FO_V << MODEM_SYSCON_CLK_BT_40M_FO_S)
+#define MODEM_SYSCON_CLK_BT_40M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_40M_FO_S  26
+/* MODEM_SYSCON_CLK_BT_32M_FO : R/W; bitpos: [27]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_32M_FO    (BIT(27))
+#define MODEM_SYSCON_CLK_BT_32M_FO_M  (MODEM_SYSCON_CLK_BT_32M_FO_V << MODEM_SYSCON_CLK_BT_32M_FO_S)
+#define MODEM_SYSCON_CLK_BT_32M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_32M_FO_S  27
+/* MODEM_SYSCON_CLK_BT_16M_FO : R/W; bitpos: [28]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_16M_FO    (BIT(28))
+#define MODEM_SYSCON_CLK_BT_16M_FO_M  (MODEM_SYSCON_CLK_BT_16M_FO_V << MODEM_SYSCON_CLK_BT_16M_FO_S)
+#define MODEM_SYSCON_CLK_BT_16M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_16M_FO_S  28
+/* MODEM_SYSCON_CLK_BT_160M_FO : R/W; bitpos: [29]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_160M_FO    (BIT(29))
+#define MODEM_SYSCON_CLK_BT_160M_FO_M  (MODEM_SYSCON_CLK_BT_160M_FO_V << MODEM_SYSCON_CLK_BT_160M_FO_S)
+#define MODEM_SYSCON_CLK_BT_160M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_160M_FO_S  29
+/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO    (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M  (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S)
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S  30
+/* MODEM_SYSCON_CLK_BLE_TIMER_APB_FO : R/W; bitpos: [31]; default: 0; */
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_FO    (BIT(31))
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_FO_M  (MODEM_SYSCON_CLK_BLE_TIMER_APB_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_APB_FO_S)
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_FO_S  31
+
+/* MODEM_SYSCON_CLK_CONF_POWER_ST_REG register */
+#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc)
+/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; */
+#define MODEM_SYSCON_CLK_ZB_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_ZB_ST_MAP_M  (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S)
+#define MODEM_SYSCON_CLK_ZB_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_ZB_ST_MAP_S  8
+/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_FE_ST_MAP_M  (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S)
+#define MODEM_SYSCON_CLK_FE_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_FE_ST_MAP_S  12
+/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_BT_ST_MAP_M  (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S)
+#define MODEM_SYSCON_CLK_BT_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_BT_ST_MAP_S  16
+/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M  (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S)
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S  20
+/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M  (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S  24
+/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP    0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M  (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V  0x0000000FU
+#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S  28
+
+/* MODEM_SYSCON_MODEM_RST_CONF_REG register */
+#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
+/* MODEM_SYSCON_RST_FE_TXLOGAIN : R/W; bitpos: [6]; default: 0; */
+#define MODEM_SYSCON_RST_FE_TXLOGAIN    (BIT(6))
+#define MODEM_SYSCON_RST_FE_TXLOGAIN_M  (MODEM_SYSCON_RST_FE_TXLOGAIN_V << MODEM_SYSCON_RST_FE_TXLOGAIN_S)
+#define MODEM_SYSCON_RST_FE_TXLOGAIN_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_TXLOGAIN_S  6
+/* MODEM_SYSCON_RST_FE_SDM : R/W; bitpos: [7]; default: 0; */
+#define MODEM_SYSCON_RST_FE_SDM    (BIT(7))
+#define MODEM_SYSCON_RST_FE_SDM_M  (MODEM_SYSCON_RST_FE_SDM_V << MODEM_SYSCON_RST_FE_SDM_S)
+#define MODEM_SYSCON_RST_FE_SDM_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_SDM_S  7
+/* MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; */
+#define MODEM_SYSCON_RST_WIFIBB    (BIT(8))
+#define MODEM_SYSCON_RST_WIFIBB_M  (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S)
+#define MODEM_SYSCON_RST_WIFIBB_V  0x00000001U
+#define MODEM_SYSCON_RST_WIFIBB_S  8
+/* MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [9]; default: 0; */
+#define MODEM_SYSCON_RST_WIFIMAC    (BIT(9))
+#define MODEM_SYSCON_RST_WIFIMAC_M  (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S)
+#define MODEM_SYSCON_RST_WIFIMAC_V  0x00000001U
+#define MODEM_SYSCON_RST_WIFIMAC_S  9
+/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W; bitpos: [10]; default: 0; */
+#define MODEM_SYSCON_RST_FE_PWDET_ADC    (BIT(10))
+#define MODEM_SYSCON_RST_FE_PWDET_ADC_M  (MODEM_SYSCON_RST_FE_PWDET_ADC_V << MODEM_SYSCON_RST_FE_PWDET_ADC_S)
+#define MODEM_SYSCON_RST_FE_PWDET_ADC_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_PWDET_ADC_S  10
+/* MODEM_SYSCON_RST_FE_DAC : R/W; bitpos: [11]; default: 0; */
+#define MODEM_SYSCON_RST_FE_DAC    (BIT(11))
+#define MODEM_SYSCON_RST_FE_DAC_M  (MODEM_SYSCON_RST_FE_DAC_V << MODEM_SYSCON_RST_FE_DAC_S)
+#define MODEM_SYSCON_RST_FE_DAC_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_DAC_S  11
+/* MODEM_SYSCON_RST_FE_ADC : R/W; bitpos: [12]; default: 0; */
+#define MODEM_SYSCON_RST_FE_ADC    (BIT(12))
+#define MODEM_SYSCON_RST_FE_ADC_M  (MODEM_SYSCON_RST_FE_ADC_V << MODEM_SYSCON_RST_FE_ADC_S)
+#define MODEM_SYSCON_RST_FE_ADC_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_ADC_S  12
+/* MODEM_SYSCON_RST_FE_AHB : R/W; bitpos: [13]; default: 0; */
+#define MODEM_SYSCON_RST_FE_AHB    (BIT(13))
+#define MODEM_SYSCON_RST_FE_AHB_M  (MODEM_SYSCON_RST_FE_AHB_V << MODEM_SYSCON_RST_FE_AHB_S)
+#define MODEM_SYSCON_RST_FE_AHB_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_AHB_S  13
+/* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */
+#define MODEM_SYSCON_RST_FE    (BIT(14))
+#define MODEM_SYSCON_RST_FE_M  (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S)
+#define MODEM_SYSCON_RST_FE_V  0x00000001U
+#define MODEM_SYSCON_RST_FE_S  14
+/* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */
+#define MODEM_SYSCON_RST_BTMAC_APB    (BIT(15))
+#define MODEM_SYSCON_RST_BTMAC_APB_M  (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S)
+#define MODEM_SYSCON_RST_BTMAC_APB_V  0x00000001U
+#define MODEM_SYSCON_RST_BTMAC_APB_S  15
+/* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */
+#define MODEM_SYSCON_RST_BTMAC    (BIT(16))
+#define MODEM_SYSCON_RST_BTMAC_M  (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S)
+#define MODEM_SYSCON_RST_BTMAC_V  0x00000001U
+#define MODEM_SYSCON_RST_BTMAC_S  16
+/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */
+#define MODEM_SYSCON_RST_BTBB_APB    (BIT(17))
+#define MODEM_SYSCON_RST_BTBB_APB_M  (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S)
+#define MODEM_SYSCON_RST_BTBB_APB_V  0x00000001U
+#define MODEM_SYSCON_RST_BTBB_APB_S  17
+/* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */
+#define MODEM_SYSCON_RST_BTBB    (BIT(18))
+#define MODEM_SYSCON_RST_BTBB_M  (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S)
+#define MODEM_SYSCON_RST_BTBB_V  0x00000001U
+#define MODEM_SYSCON_RST_BTBB_S  18
+/* MODEM_SYSCON_RST_COEX_BTMAC_APB : R/W; bitpos: [19]; default: 0; */
+#define MODEM_SYSCON_RST_COEX_BTMAC_APB    (BIT(19))
+#define MODEM_SYSCON_RST_COEX_BTMAC_APB_M  (MODEM_SYSCON_RST_COEX_BTMAC_APB_V << MODEM_SYSCON_RST_COEX_BTMAC_APB_S)
+#define MODEM_SYSCON_RST_COEX_BTMAC_APB_V  0x00000001U
+#define MODEM_SYSCON_RST_COEX_BTMAC_APB_S  19
+/* MODEM_SYSCON_RST_COEX_BTMAC : R/W; bitpos: [20]; default: 0; */
+#define MODEM_SYSCON_RST_COEX_BTMAC    (BIT(20))
+#define MODEM_SYSCON_RST_COEX_BTMAC_M  (MODEM_SYSCON_RST_COEX_BTMAC_V << MODEM_SYSCON_RST_COEX_BTMAC_S)
+#define MODEM_SYSCON_RST_COEX_BTMAC_V  0x00000001U
+#define MODEM_SYSCON_RST_COEX_BTMAC_S  20
+/* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */
+#define MODEM_SYSCON_RST_ETM    (BIT(22))
+#define MODEM_SYSCON_RST_ETM_M  (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S)
+#define MODEM_SYSCON_RST_ETM_V  0x00000001U
+#define MODEM_SYSCON_RST_ETM_S  22
+/* MODEM_SYSCON_RST_ZBMAC_APB : R/W; bitpos: [23]; default: 0; */
+#define MODEM_SYSCON_RST_ZBMAC_APB    (BIT(23))
+#define MODEM_SYSCON_RST_ZBMAC_APB_M  (MODEM_SYSCON_RST_ZBMAC_APB_V << MODEM_SYSCON_RST_ZBMAC_APB_S)
+#define MODEM_SYSCON_RST_ZBMAC_APB_V  0x00000001U
+#define MODEM_SYSCON_RST_ZBMAC_APB_S  23
+/* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */
+#define MODEM_SYSCON_RST_ZBMAC    (BIT(24))
+#define MODEM_SYSCON_RST_ZBMAC_M  (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S)
+#define MODEM_SYSCON_RST_ZBMAC_V  0x00000001U
+#define MODEM_SYSCON_RST_ZBMAC_S  24
+/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */
+#define MODEM_SYSCON_RST_MODEM_ECB    (BIT(25))
+#define MODEM_SYSCON_RST_MODEM_ECB_M  (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S)
+#define MODEM_SYSCON_RST_MODEM_ECB_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_ECB_S  25
+/* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */
+#define MODEM_SYSCON_RST_MODEM_CCM    (BIT(26))
+#define MODEM_SYSCON_RST_MODEM_CCM_M  (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S)
+#define MODEM_SYSCON_RST_MODEM_CCM_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_CCM_S  26
+/* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */
+#define MODEM_SYSCON_RST_MODEM_BAH    (BIT(27))
+#define MODEM_SYSCON_RST_MODEM_BAH_M  (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S)
+#define MODEM_SYSCON_RST_MODEM_BAH_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_BAH_S  27
+/* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */
+#define MODEM_SYSCON_RST_MODEM_SEC    (BIT(29))
+#define MODEM_SYSCON_RST_MODEM_SEC_M  (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S)
+#define MODEM_SYSCON_RST_MODEM_SEC_V  0x00000001U
+#define MODEM_SYSCON_RST_MODEM_SEC_S  29
+/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */
+#define MODEM_SYSCON_RST_BLE_TIMER    (BIT(30))
+#define MODEM_SYSCON_RST_BLE_TIMER_M  (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S)
+#define MODEM_SYSCON_RST_BLE_TIMER_V  0x00000001U
+#define MODEM_SYSCON_RST_BLE_TIMER_S  30
+/* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */
+#define MODEM_SYSCON_RST_DATA_DUMP    (BIT(31))
+#define MODEM_SYSCON_RST_DATA_DUMP_M  (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S)
+#define MODEM_SYSCON_RST_DATA_DUMP_V  0x00000001U
+#define MODEM_SYSCON_RST_DATA_DUMP_S  31
+
+/* MODEM_SYSCON_CLK_CONF1_REG register */
+#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14)
+/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN    (BIT(0))
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S  0
+/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN    (BIT(1))
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S  1
+/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN    (BIT(2))
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S  2
+/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN    (BIT(3))
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S  3
+/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN    (BIT(4))
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S  4
+/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN    (BIT(5))
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S  5
+/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN    (BIT(6))
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S  6
+/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN    (BIT(7))
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S  7
+/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN    (BIT(8))
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M  (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S)
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S  8
+/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIMAC_EN    (BIT(9))
+#define MODEM_SYSCON_CLK_WIFIMAC_EN_M  (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S)
+#define MODEM_SYSCON_CLK_WIFIMAC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIMAC_EN_S  9
+/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFI_APB_EN    (BIT(10))
+#define MODEM_SYSCON_CLK_WIFI_APB_EN_M  (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S)
+#define MODEM_SYSCON_CLK_WIFI_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFI_APB_EN_S  10
+/* MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_20M_EN    (BIT(11))
+#define MODEM_SYSCON_CLK_FE_20M_EN_M  (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S)
+#define MODEM_SYSCON_CLK_FE_20M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_20M_EN_S  11
+/* MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_40M_EN    (BIT(12))
+#define MODEM_SYSCON_CLK_FE_40M_EN_M  (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S)
+#define MODEM_SYSCON_CLK_FE_40M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_40M_EN_S  12
+/* MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_80M_EN    (BIT(13))
+#define MODEM_SYSCON_CLK_FE_80M_EN_M  (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S)
+#define MODEM_SYSCON_CLK_FE_80M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_80M_EN_S  13
+/* MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_160M_EN    (BIT(14))
+#define MODEM_SYSCON_CLK_FE_160M_EN_M  (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S)
+#define MODEM_SYSCON_CLK_FE_160M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_160M_EN_S  14
+/* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [15]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_APB_EN    (BIT(15))
+#define MODEM_SYSCON_CLK_FE_APB_EN_M  (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S)
+#define MODEM_SYSCON_CLK_FE_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_APB_EN_S  15
+/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [16]; default: 0; */
+#define MODEM_SYSCON_CLK_BT_APB_EN    (BIT(16))
+#define MODEM_SYSCON_CLK_BT_APB_EN_M  (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S)
+#define MODEM_SYSCON_CLK_BT_APB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_BT_APB_EN_S  16
+/* MODEM_SYSCON_CLK_BTBB_EN : R/W; bitpos: [17]; default: 0; */
+#define MODEM_SYSCON_CLK_BTBB_EN    (BIT(17))
+#define MODEM_SYSCON_CLK_BTBB_EN_M  (MODEM_SYSCON_CLK_BTBB_EN_V << MODEM_SYSCON_CLK_BTBB_EN_S)
+#define MODEM_SYSCON_CLK_BTBB_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_BTBB_EN_S  17
+/* MODEM_SYSCON_CLK_BTMAC_EN : R/W; bitpos: [18]; default: 0; */
+#define MODEM_SYSCON_CLK_BTMAC_EN    (BIT(18))
+#define MODEM_SYSCON_CLK_BTMAC_EN_M  (MODEM_SYSCON_CLK_BTMAC_EN_V << MODEM_SYSCON_CLK_BTMAC_EN_S)
+#define MODEM_SYSCON_CLK_BTMAC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_BTMAC_EN_S  18
+/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W; bitpos: [19]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN    (BIT(19))
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M  (MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V << MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S)
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S  19
+/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W; bitpos: [20]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_ADC_EN    (BIT(20))
+#define MODEM_SYSCON_CLK_FE_ADC_EN_M  (MODEM_SYSCON_CLK_FE_ADC_EN_V << MODEM_SYSCON_CLK_FE_ADC_EN_S)
+#define MODEM_SYSCON_CLK_FE_ADC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ADC_EN_S  20
+/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W; bitpos: [21]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_DAC_EN    (BIT(21))
+#define MODEM_SYSCON_CLK_FE_DAC_EN_M  (MODEM_SYSCON_CLK_FE_DAC_EN_V << MODEM_SYSCON_CLK_FE_DAC_EN_S)
+#define MODEM_SYSCON_CLK_FE_DAC_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_DAC_EN_S  21
+/* MODEM_SYSCON_CLK_FE_SDM_EN : R/W; bitpos: [22]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_SDM_EN    (BIT(22))
+#define MODEM_SYSCON_CLK_FE_SDM_EN_M  (MODEM_SYSCON_CLK_FE_SDM_EN_V << MODEM_SYSCON_CLK_FE_SDM_EN_S)
+#define MODEM_SYSCON_CLK_FE_SDM_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_SDM_EN_S  22
+/* MODEM_SYSCON_CLK_FE_TXLOGAIN_EN : R/W; bitpos: [23]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN    (BIT(23))
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_M  (MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_V << MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_S)
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_EN_S  23
+/* MODEM_SYSCON_CLK_FE_32M_EN : R/W; bitpos: [24]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_32M_EN    (BIT(24))
+#define MODEM_SYSCON_CLK_FE_32M_EN_M  (MODEM_SYSCON_CLK_FE_32M_EN_V << MODEM_SYSCON_CLK_FE_32M_EN_S)
+#define MODEM_SYSCON_CLK_FE_32M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_32M_EN_S  24
+/* MODEM_SYSCON_CLK_FE_16M_EN : R/W; bitpos: [25]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_16M_EN    (BIT(25))
+#define MODEM_SYSCON_CLK_FE_16M_EN_M  (MODEM_SYSCON_CLK_FE_16M_EN_V << MODEM_SYSCON_CLK_FE_16M_EN_S)
+#define MODEM_SYSCON_CLK_FE_16M_EN_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_16M_EN_S  25
+
+/* MODEM_SYSCON_WIFI_BB_CFG_REG register */
+#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18)
+/* MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; */
+#define MODEM_SYSCON_WIFI_BB_CFG    0xFFFFFFFFU
+#define MODEM_SYSCON_WIFI_BB_CFG_M  (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S)
+#define MODEM_SYSCON_WIFI_BB_CFG_V  0xFFFFFFFFU
+#define MODEM_SYSCON_WIFI_BB_CFG_S  0
+
+/* MODEM_SYSCON_FE_CFG_REG register */
+#define MODEM_SYSCON_FE_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c)
+/* MODEM_SYSCON_FE_CFG : R/W; bitpos: [31:0]; default: 0; */
+#define MODEM_SYSCON_FE_CFG    0xFFFFFFFFU
+#define MODEM_SYSCON_FE_CFG_M  (MODEM_SYSCON_FE_CFG_V << MODEM_SYSCON_FE_CFG_S)
+#define MODEM_SYSCON_FE_CFG_V  0xFFFFFFFFU
+#define MODEM_SYSCON_FE_CFG_S  0
+
+/* MODEM_SYSCON_MEM_RF1_CONF_REG register */
+#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20)
+/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 10320; */
+#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL    0xFFFFFFFFU
+#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M  (MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V << MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)
+#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S  0
+
+/* MODEM_SYSCON_MEM_RF2_CONF_REG register */
+#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x24)
+/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; */
+#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL    0xFFFFFFFFU
+#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M  (MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V << MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)
+#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S  0
+
+/* MODEM_SYSCON_BTMAC_CLK_CFG_REG register */
+#define MODEM_SYSCON_BTMAC_CLK_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x28)
+/* MODEM_SYSCON_CLK_BTMAC_LOW_RATE : R/W; bitpos: [0]; default: 0; */
+#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE    (BIT(0))
+#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE_M  (MODEM_SYSCON_CLK_BTMAC_LOW_RATE_V << MODEM_SYSCON_CLK_BTMAC_LOW_RATE_S)
+#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE_V  0x00000001U
+#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE_S  0
+
+/* MODEM_SYSCON_CLK_CONF_FORCE_ON_2_REG register */
+#define MODEM_SYSCON_CLK_CONF_FORCE_ON_2_REG (DR_REG_MODEM_SYSCON_BASE + 0x2c)
+/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [0]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFI_APB_FO    (BIT(0))
+#define MODEM_SYSCON_CLK_WIFI_APB_FO_M  (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S)
+#define MODEM_SYSCON_CLK_WIFI_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFI_APB_FO_S  0
+/* MODEM_SYSCON_CLK_WIFIBB_160M_X1_FO : R/W; bitpos: [1]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_160M_X1_FO    (BIT(1))
+#define MODEM_SYSCON_CLK_WIFIBB_160M_X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_160M_X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_160M_X1_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_160M_X1_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_160M_X1_FO_S  1
+/* MODEM_SYSCON_CLK_WIFIBB_22M_FO : R/W; bitpos: [2]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO    (BIT(2))
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_22M_FO_V << MODEM_SYSCON_CLK_WIFIBB_22M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_S  2
+/* MODEM_SYSCON_CLK_WIFIBB_40M_FO : R/W; bitpos: [3]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO    (BIT(3))
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40M_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_S  3
+/* MODEM_SYSCON_CLK_WIFIBB_40M_X1_FO : R/W; bitpos: [4]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X1_FO    (BIT(4))
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40M_X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_X1_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X1_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X1_FO_S  4
+/* MODEM_SYSCON_CLK_WIFIBB_40M_X_INT_FO : R/W; bitpos: [5]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_INT_FO    (BIT(5))
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_INT_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40M_X_INT_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_X_INT_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_INT_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_INT_FO_S  5
+/* MODEM_SYSCON_CLK_WIFIBB_44M_FO : R/W; bitpos: [6]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO    (BIT(6))
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_44M_FO_V << MODEM_SYSCON_CLK_WIFIBB_44M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_S  6
+/* MODEM_SYSCON_CLK_WIFIBB_80M_FO : R/W; bitpos: [7]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO    (BIT(7))
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80M_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_S  7
+/* MODEM_SYSCON_CLK_WIFIBB_80M_X1_FO : R/W; bitpos: [8]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X1_FO    (BIT(8))
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X1_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80M_X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_X1_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X1_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X1_FO_S  8
+/* MODEM_SYSCON_CLK_WIFIBB_80M_X_INT_FO : R/W; bitpos: [9]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_INT_FO    (BIT(9))
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_INT_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80M_X_INT_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_X_INT_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_INT_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_INT_FO_S  9
+/* MODEM_SYSCON_CLK_WIFIBB_APB_44M_FO : R/W; bitpos: [10]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_APB_44M_FO    (BIT(10))
+#define MODEM_SYSCON_CLK_WIFIBB_APB_44M_FO_M  (MODEM_SYSCON_CLK_WIFIBB_APB_44M_FO_V << MODEM_SYSCON_CLK_WIFIBB_APB_44M_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_APB_44M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_APB_44M_FO_S  10
+/* MODEM_SYSCON_CLK_WIFIMAC_AHB_FO : R/W; bitpos: [11]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIMAC_AHB_FO    (BIT(11))
+#define MODEM_SYSCON_CLK_WIFIMAC_AHB_FO_M  (MODEM_SYSCON_CLK_WIFIMAC_AHB_FO_V << MODEM_SYSCON_CLK_WIFIMAC_AHB_FO_S)
+#define MODEM_SYSCON_CLK_WIFIMAC_AHB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIMAC_AHB_FO_S  11
+/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [12]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIMAC_FO    (BIT(12))
+#define MODEM_SYSCON_CLK_WIFIMAC_FO_M  (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S)
+#define MODEM_SYSCON_CLK_WIFIMAC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIMAC_FO_S  12
+/* MODEM_SYSCON_CLK_ZBMAC_AHB_FO : R/W; bitpos: [13]; default: 0; */
+#define MODEM_SYSCON_CLK_ZBMAC_AHB_FO    (BIT(13))
+#define MODEM_SYSCON_CLK_ZBMAC_AHB_FO_M  (MODEM_SYSCON_CLK_ZBMAC_AHB_FO_V << MODEM_SYSCON_CLK_ZBMAC_AHB_FO_S)
+#define MODEM_SYSCON_CLK_ZBMAC_AHB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZBMAC_AHB_FO_S  13
+/* MODEM_SYSCON_CLK_ZBMAC_APB_16M_FO : R/W; bitpos: [14]; default: 0; */
+#define MODEM_SYSCON_CLK_ZBMAC_APB_16M_FO    (BIT(14))
+#define MODEM_SYSCON_CLK_ZBMAC_APB_16M_FO_M  (MODEM_SYSCON_CLK_ZBMAC_APB_16M_FO_V << MODEM_SYSCON_CLK_ZBMAC_APB_16M_FO_S)
+#define MODEM_SYSCON_CLK_ZBMAC_APB_16M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZBMAC_APB_16M_FO_S  14
+/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W; bitpos: [15]; default: 0; */
+#define MODEM_SYSCON_CLK_ZBMAC_APB_FO    (BIT(15))
+#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M  (MODEM_SYSCON_CLK_ZBMAC_APB_FO_V << MODEM_SYSCON_CLK_ZBMAC_APB_FO_S)
+#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S  15
+/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W; bitpos: [16]; default: 0; */
+#define MODEM_SYSCON_CLK_ZBMAC_FO    (BIT(16))
+#define MODEM_SYSCON_CLK_ZBMAC_FO_M  (MODEM_SYSCON_CLK_ZBMAC_FO_V << MODEM_SYSCON_CLK_ZBMAC_FO_S)
+#define MODEM_SYSCON_CLK_ZBMAC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_ZBMAC_FO_S  16
+/* MODEM_SYSCON_CLK_WIFIBB_80M_X_FO : R/W; bitpos: [17]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_FO    (BIT(17))
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_FO_M  (MODEM_SYSCON_CLK_WIFIBB_80M_X_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_X_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_80M_X_FO_S  17
+/* MODEM_SYSCON_CLK_WIFIBB_40M_X_FO : R/W; bitpos: [18]; default: 0; */
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_FO    (BIT(18))
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_FO_M  (MODEM_SYSCON_CLK_WIFIBB_40M_X_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_X_FO_S)
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_WIFIBB_40M_X_FO_S  18
+/* MODEM_SYSCON_CLK_FE_ADC_FO : R/W; bitpos: [19]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_ADC_FO    (BIT(19))
+#define MODEM_SYSCON_CLK_FE_ADC_FO_M  (MODEM_SYSCON_CLK_FE_ADC_FO_V << MODEM_SYSCON_CLK_FE_ADC_FO_S)
+#define MODEM_SYSCON_CLK_FE_ADC_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_ADC_FO_S  19
+/* MODEM_SYSCON_CLK_FE_TXLOGAIN_INF_FO : R/W; bitpos: [20]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_INF_FO    (BIT(20))
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_INF_FO_M  (MODEM_SYSCON_CLK_FE_TXLOGAIN_INF_FO_V << MODEM_SYSCON_CLK_FE_TXLOGAIN_INF_FO_S)
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_INF_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_TXLOGAIN_INF_FO_S  20
+/* MODEM_SYSCON_CLK_FE_SDM_INF_FO : R/W; bitpos: [21]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_SDM_INF_FO    (BIT(21))
+#define MODEM_SYSCON_CLK_FE_SDM_INF_FO_M  (MODEM_SYSCON_CLK_FE_SDM_INF_FO_V << MODEM_SYSCON_CLK_FE_SDM_INF_FO_S)
+#define MODEM_SYSCON_CLK_FE_SDM_INF_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_SDM_INF_FO_S  21
+/* MODEM_SYSCON_CLK_FE_SDM_FO : R/W; bitpos: [22]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_SDM_FO    (BIT(22))
+#define MODEM_SYSCON_CLK_FE_SDM_FO_M  (MODEM_SYSCON_CLK_FE_SDM_FO_V << MODEM_SYSCON_CLK_FE_SDM_FO_S)
+#define MODEM_SYSCON_CLK_FE_SDM_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_SDM_FO_S  22
+/* MODEM_SYSCON_CLK_FE_SDM_DIV4_FO : R/W; bitpos: [23]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_SDM_DIV4_FO    (BIT(23))
+#define MODEM_SYSCON_CLK_FE_SDM_DIV4_FO_M  (MODEM_SYSCON_CLK_FE_SDM_DIV4_FO_V << MODEM_SYSCON_CLK_FE_SDM_DIV4_FO_S)
+#define MODEM_SYSCON_CLK_FE_SDM_DIV4_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_SDM_DIV4_FO_S  23
+/* MODEM_SYSCON_CLK_FE_SDM_DIV2_FO : R/W; bitpos: [24]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_SDM_DIV2_FO    (BIT(24))
+#define MODEM_SYSCON_CLK_FE_SDM_DIV2_FO_M  (MODEM_SYSCON_CLK_FE_SDM_DIV2_FO_V << MODEM_SYSCON_CLK_FE_SDM_DIV2_FO_S)
+#define MODEM_SYSCON_CLK_FE_SDM_DIV2_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_SDM_DIV2_FO_S  24
+/* MODEM_SYSCON_CLK_FE_16M_FO : R/W; bitpos: [25]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_16M_FO    (BIT(25))
+#define MODEM_SYSCON_CLK_FE_16M_FO_M  (MODEM_SYSCON_CLK_FE_16M_FO_V << MODEM_SYSCON_CLK_FE_16M_FO_S)
+#define MODEM_SYSCON_CLK_FE_16M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_16M_FO_S  25
+/* MODEM_SYSCON_CLK_FE_32M_FO : R/W; bitpos: [26]; default: 0; */
+#define MODEM_SYSCON_CLK_FE_32M_FO    (BIT(26))
+#define MODEM_SYSCON_CLK_FE_32M_FO_M  (MODEM_SYSCON_CLK_FE_32M_FO_V << MODEM_SYSCON_CLK_FE_32M_FO_S)
+#define MODEM_SYSCON_CLK_FE_32M_FO_V  0x00000001U
+#define MODEM_SYSCON_CLK_FE_32M_FO_S  26
+
+/* MODEM_SYSCON_APB_TIMEOUT_CONF_REG register */
+#define MODEM_SYSCON_APB_TIMEOUT_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x30)
+/* MODEM_SYSCON_APB_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; */
+#define MODEM_SYSCON_APB_TIMEOUT_THRES    0x0000FFFFU
+#define MODEM_SYSCON_APB_TIMEOUT_THRES_M  (MODEM_SYSCON_APB_TIMEOUT_THRES_V << MODEM_SYSCON_APB_TIMEOUT_THRES_S)
+#define MODEM_SYSCON_APB_TIMEOUT_THRES_V  0x0000FFFFU
+#define MODEM_SYSCON_APB_TIMEOUT_THRES_S  0
+/* MODEM_SYSCON_APB_TIMEOUT_PROTECT_EN : R/W; bitpos: [16]; default: 1; */
+#define MODEM_SYSCON_APB_TIMEOUT_PROTECT_EN    (BIT(16))
+#define MODEM_SYSCON_APB_TIMEOUT_PROTECT_EN_M  (MODEM_SYSCON_APB_TIMEOUT_PROTECT_EN_V << MODEM_SYSCON_APB_TIMEOUT_PROTECT_EN_S)
+#define MODEM_SYSCON_APB_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define MODEM_SYSCON_APB_TIMEOUT_PROTECT_EN_S  16
+/* MODEM_SYSCON_APB_TIMEOUT_INT_CLR : WO; bitpos: [17]; default: 0; */
+#define MODEM_SYSCON_APB_TIMEOUT_INT_CLR    (BIT(17))
+#define MODEM_SYSCON_APB_TIMEOUT_INT_CLR_M  (MODEM_SYSCON_APB_TIMEOUT_INT_CLR_V << MODEM_SYSCON_APB_TIMEOUT_INT_CLR_S)
+#define MODEM_SYSCON_APB_TIMEOUT_INT_CLR_V  0x00000001U
+#define MODEM_SYSCON_APB_TIMEOUT_INT_CLR_S  17
+/* MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PID : RO; bitpos: [21:18]; default: 0; */
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PID    0x0000000FU
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PID_M  (MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PID_V << MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PID_S)
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PID_V  0x0000000FU
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PID_S  18
+/* MODEM_SYSCON_MODEM_APB_TIMEOUT_INT : RO; bitpos: [22]; default: 0; */
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_INT    (BIT(22))
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_INT_M  (MODEM_SYSCON_MODEM_APB_TIMEOUT_INT_V << MODEM_SYSCON_MODEM_APB_TIMEOUT_INT_S)
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_INT_V  0x00000001U
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_INT_S  22
+
+/* MODEM_SYSCON_APB_TIMEOUT_EXCEPTION_ADDR_REG register */
+#define MODEM_SYSCON_APB_TIMEOUT_EXCEPTION_ADDR_REG (DR_REG_MODEM_SYSCON_BASE + 0x34)
+/* MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PADDR : RO; bitpos: [31:0]; default: 0; */
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PADDR    0xFFFFFFFFU
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PADDR_M  (MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PADDR_V << MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PADDR_S)
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PADDR_V  0xFFFFFFFFU
+#define MODEM_SYSCON_MODEM_APB_TIMEOUT_EXCEPTION_PADDR_S  0
+
+/* MODEM_SYSCON_DATE_REG register */
+#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x38)
+/* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 37823024; */
+#define MODEM_SYSCON_DATE    0x0FFFFFFFU
+#define MODEM_SYSCON_DATE_M  (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S)
+#define MODEM_SYSCON_DATE_V  0x0FFFFFFFU
+#define MODEM_SYSCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h4/include/modem/modem_syscon_struct.h

@@ -0,0 +1,462 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/* Type of test_conf register*/
+typedef union {
+    struct {
+        /* clk_en : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_en: 1;
+        /* modem_ant_force_sel_bt : R/W; bitpos: [1]; default: 0;*/
+        uint32_t modem_ant_force_sel_bt: 1;
+        /* modem_ant_force_sel_wifi : R/W; bitpos: [2]; default: 0;*/
+        uint32_t modem_ant_force_sel_wifi: 1;
+        /* fpga_debug_clkswitch : R/W; bitpos: [3]; default: 0;*/
+        uint32_t fpga_debug_clkswitch: 1;
+        /* fpga_debug_clk80 : R/W; bitpos: [4]; default: 0;*/
+        uint32_t fpga_debug_clk80: 1;
+        /* fpga_debug_clk40 : R/W; bitpos: [5]; default: 0;*/
+        uint32_t fpga_debug_clk40: 1;
+        /* fpga_debug_clk20 : R/W; bitpos: [6]; default: 0;*/
+        uint32_t fpga_debug_clk20: 1;
+        /* fpga_debug_clk10 : R/W; bitpos: [7]; default: 0;*/
+        uint32_t fpga_debug_clk10: 1;
+        /* modem_mem_mode_force : R/W; bitpos: [8]; default: 1;*/
+        uint32_t modem_mem_mode_force: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} modem_syscon_test_conf_reg_t;
+
+/* Type of clk_conf register*/
+typedef union {
+    struct {
+        /* pwdet_sar_clock_ena : R/W; bitpos: [0]; default: 0;*/
+        uint32_t pwdet_sar_clock_ena: 1;
+        /* pwdet_clk_div_num : R/W; bitpos: [8:1]; default: 1;*/
+        uint32_t pwdet_clk_div_num: 8;
+        /* clk_tx_dac_inv_ena : R/W; bitpos: [9]; default: 0;*/
+        uint32_t clk_tx_dac_inv_ena: 1;
+        /* clk_rx_adc_inv_ena : R/W; bitpos: [10]; default: 0;*/
+        uint32_t clk_rx_adc_inv_ena: 1;
+        /* clk_pwdet_adc_inv_ena : R/W; bitpos: [11]; default: 0;*/
+        uint32_t clk_pwdet_adc_inv_ena: 1;
+        /* clk_i2c_mst_sel_160m : R/W; bitpos: [12]; default: 0;*/
+        uint32_t clk_i2c_mst_sel_160m: 1;
+        uint32_t reserved_13: 8;
+        /* clk_data_dump_mux : R/W; bitpos: [21]; default: 0;*/
+        uint32_t clk_data_dump_mux: 1;
+        /* clk_etm_en : R/W; bitpos: [22]; default: 0;*/
+        uint32_t clk_etm_en: 1;
+        /* clk_zb_apb_en : R/W; bitpos: [23]; default: 0;*/
+        uint32_t clk_zb_apb_en: 1;
+        /* clk_zbmac_en : R/W; bitpos: [24]; default: 0;*/
+        uint32_t clk_zbmac_en: 1;
+        /* clk_modem_sec_ecb_en : R/W; bitpos: [25]; default: 0;*/
+        uint32_t clk_modem_sec_ecb_en: 1;
+        /* clk_modem_sec_ccm_en : R/W; bitpos: [26]; default: 0;*/
+        uint32_t clk_modem_sec_ccm_en: 1;
+        /* clk_modem_sec_bah_en : R/W; bitpos: [27]; default: 0;*/
+        uint32_t clk_modem_sec_bah_en: 1;
+        /* clk_modem_sec_apb_en : R/W; bitpos: [28]; default: 0;*/
+        uint32_t clk_modem_sec_apb_en: 1;
+        /* clk_modem_sec_en : R/W; bitpos: [29]; default: 0;*/
+        uint32_t clk_modem_sec_en: 1;
+        /* clk_ble_timer_en : R/W; bitpos: [30]; default: 0;*/
+        uint32_t clk_ble_timer_en: 1;
+        /* clk_data_dump_en : R/W; bitpos: [31]; default: 0;*/
+        uint32_t clk_data_dump_en: 1;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf_reg_t;
+
+/* Type of clk_conf_force_on register*/
+typedef union {
+    struct {
+        /* clk_aon_fo : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_aon_fo: 1;
+        /* clk_pll_fo : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_pll_fo: 1;
+        /* clk_modem_sec_fo : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_modem_sec_fo: 1;
+        /* clk_modem_sec_ecb_fo : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_modem_sec_ecb_fo: 1;
+        /* clk_modem_sec_ccm_fo : R/W; bitpos: [4]; default: 0;*/
+        uint32_t clk_modem_sec_ccm_fo: 1;
+        /* clk_modem_sec_bah_fo : R/W; bitpos: [5]; default: 0;*/
+        uint32_t clk_modem_sec_bah_fo: 1;
+        /* clk_modem_sec_apb_fo : R/W; bitpos: [6]; default: 0;*/
+        uint32_t clk_modem_sec_apb_fo: 1;
+        /* clk_modem_sec_ahb_fo : R/W; bitpos: [7]; default: 0;*/
+        uint32_t clk_modem_sec_ahb_fo: 1;
+        /* clk_fe_pwdet_adc_inf_fo : R/W; bitpos: [8]; default: 0;*/
+        uint32_t clk_fe_pwdet_adc_inf_fo: 1;
+        /* clk_fe_dac_inf_fo : R/W; bitpos: [9]; default: 0;*/
+        uint32_t clk_fe_dac_inf_fo: 1;
+        /* clk_fe_apb_fo : R/W; bitpos: [10]; default: 0;*/
+        uint32_t clk_fe_apb_fo: 1;
+        /* clk_fe_adc_inf_fo : R/W; bitpos: [11]; default: 0;*/
+        uint32_t clk_fe_adc_inf_fo: 1;
+        /* clk_fe_80m_fo : R/W; bitpos: [12]; default: 0;*/
+        uint32_t clk_fe_80m_fo: 1;
+        /* clk_fe_40m_fo : R/W; bitpos: [13]; default: 0;*/
+        uint32_t clk_fe_40m_fo: 1;
+        /* clk_fe_20m_fo : R/W; bitpos: [14]; default: 0;*/
+        uint32_t clk_fe_20m_fo: 1;
+        /* clk_fe_160m_fo : R/W; bitpos: [15]; default: 0;*/
+        uint32_t clk_fe_160m_fo: 1;
+        /* clk_etm_fo : R/W; bitpos: [16]; default: 0;*/
+        uint32_t clk_etm_fo: 1;
+        /* clk_etm_apb_fo : R/W; bitpos: [17]; default: 0;*/
+        uint32_t clk_etm_apb_fo: 1;
+        /* clk_data_dump_mem_fo : R/W; bitpos: [18]; default: 0;*/
+        uint32_t clk_data_dump_mem_fo: 1;
+        /* clk_data_dump_fo : R/W; bitpos: [19]; default: 0;*/
+        uint32_t clk_data_dump_fo: 1;
+        /* clk_btmac_fo : R/W; bitpos: [20]; default: 0;*/
+        uint32_t clk_btmac_fo: 1;
+        /* clk_btmac_ahb_fo : R/W; bitpos: [21]; default: 0;*/
+        uint32_t clk_btmac_ahb_fo: 1;
+        /* clk_bt_apb_fo : R/W; bitpos: [22]; default: 0;*/
+        uint32_t clk_bt_apb_fo: 1;
+        /* clk_bt_apb_32m_fo : R/W; bitpos: [23]; default: 0;*/
+        uint32_t clk_bt_apb_32m_fo: 1;
+        /* clk_bt_8m_fo : R/W; bitpos: [24]; default: 0;*/
+        uint32_t clk_bt_8m_fo: 1;
+        /* clk_bt_80m_fo : R/W; bitpos: [25]; default: 0;*/
+        uint32_t clk_bt_80m_fo: 1;
+        /* clk_bt_40m_fo : R/W; bitpos: [26]; default: 0;*/
+        uint32_t clk_bt_40m_fo: 1;
+        /* clk_bt_32m_fo : R/W; bitpos: [27]; default: 0;*/
+        uint32_t clk_bt_32m_fo: 1;
+        /* clk_bt_16m_fo : R/W; bitpos: [28]; default: 0;*/
+        uint32_t clk_bt_16m_fo: 1;
+        /* clk_bt_160m_fo : R/W; bitpos: [29]; default: 0;*/
+        uint32_t clk_bt_160m_fo: 1;
+        /* clk_ble_timer_fo : R/W; bitpos: [30]; default: 0;*/
+        uint32_t clk_ble_timer_fo: 1;
+        /* clk_ble_timer_apb_fo : R/W; bitpos: [31]; default: 0;*/
+        uint32_t clk_ble_timer_apb_fo: 1;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf_force_on_reg_t;
+
+/* Type of clk_conf_power_st register*/
+typedef union {
+    struct {
+        uint32_t reserved_0: 8;
+        /* clk_zb_st_map : R/W; bitpos: [11:8]; default: 0;*/
+        uint32_t clk_zb_st_map: 4;
+        /* clk_fe_st_map : R/W; bitpos: [15:12]; default: 0;*/
+        uint32_t clk_fe_st_map: 4;
+        /* clk_bt_st_map : R/W; bitpos: [19:16]; default: 0;*/
+        uint32_t clk_bt_st_map: 4;
+        /* clk_wifi_st_map : R/W; bitpos: [23:20]; default: 0;*/
+        uint32_t clk_wifi_st_map: 4;
+        /* clk_modem_peri_st_map : R/W; bitpos: [27:24]; default: 0;*/
+        uint32_t clk_modem_peri_st_map: 4;
+        /* clk_modem_apb_st_map : R/W; bitpos: [31:28]; default: 0;*/
+        uint32_t clk_modem_apb_st_map: 4;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf_power_st_reg_t;
+
+/* Type of modem_rst_conf register*/
+typedef union {
+    struct {
+        uint32_t reserved_0: 6;
+        /* rst_fe_txlogain : R/W; bitpos: [6]; default: 0;*/
+        uint32_t rst_fe_txlogain: 1;
+        /* rst_fe_sdm : R/W; bitpos: [7]; default: 0;*/
+        uint32_t rst_fe_sdm: 1;
+        /* rst_wifibb : R/W; bitpos: [8]; default: 0;*/
+        uint32_t rst_wifibb: 1;
+        /* rst_wifimac : R/W; bitpos: [9]; default: 0;*/
+        uint32_t rst_wifimac: 1;
+        /* rst_fe_pwdet_adc : R/W; bitpos: [10]; default: 0;*/
+        uint32_t rst_fe_pwdet_adc: 1;
+        /* rst_fe_dac : R/W; bitpos: [11]; default: 0;*/
+        uint32_t rst_fe_dac: 1;
+        /* rst_fe_adc : R/W; bitpos: [12]; default: 0;*/
+        uint32_t rst_fe_adc: 1;
+        /* rst_fe_ahb : R/W; bitpos: [13]; default: 0;*/
+        uint32_t rst_fe_ahb: 1;
+        /* rst_fe : R/W; bitpos: [14]; default: 0;*/
+        uint32_t rst_fe: 1;
+        /* rst_btmac_apb : R/W; bitpos: [15]; default: 0;*/
+        uint32_t rst_btmac_apb: 1;
+        /* rst_btmac : R/W; bitpos: [16]; default: 0;*/
+        uint32_t rst_btmac: 1;
+        /* rst_btbb_apb : R/W; bitpos: [17]; default: 0;*/
+        uint32_t rst_btbb_apb: 1;
+        /* rst_btbb : R/W; bitpos: [18]; default: 0;*/
+        uint32_t rst_btbb: 1;
+        /* rst_coex_btmac_apb : R/W; bitpos: [19]; default: 0;*/
+        uint32_t rst_coex_btmac_apb: 1;
+        /* rst_coex_btmac : R/W; bitpos: [20]; default: 0;*/
+        uint32_t rst_coex_btmac: 1;
+        uint32_t reserved_21: 1;
+        /* rst_etm : R/W; bitpos: [22]; default: 0;*/
+        uint32_t rst_etm: 1;
+        /* rst_zbmac_apb : R/W; bitpos: [23]; default: 0;*/
+        uint32_t rst_zbmac_apb: 1;
+        /* rst_zbmac : R/W; bitpos: [24]; default: 0;*/
+        uint32_t rst_zbmac: 1;
+        /* rst_modem_ecb : R/W; bitpos: [25]; default: 0;*/
+        uint32_t rst_modem_ecb: 1;
+        /* rst_modem_ccm : R/W; bitpos: [26]; default: 0;*/
+        uint32_t rst_modem_ccm: 1;
+        /* rst_modem_bah : R/W; bitpos: [27]; default: 0;*/
+        uint32_t rst_modem_bah: 1;
+        uint32_t reserved_28: 1;
+        /* rst_modem_sec : R/W; bitpos: [29]; default: 0;*/
+        uint32_t rst_modem_sec: 1;
+        /* rst_ble_timer : R/W; bitpos: [30]; default: 0;*/
+        uint32_t rst_ble_timer: 1;
+        /* rst_data_dump : R/W; bitpos: [31]; default: 0;*/
+        uint32_t rst_data_dump: 1;
+    };
+    uint32_t val;
+} modem_syscon_modem_rst_conf_reg_t;
+
+/* Type of clk_conf1 register*/
+typedef union {
+    struct {
+        /* clk_wifibb_22m_en : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_wifibb_22m_en: 1;
+        /* clk_wifibb_40m_en : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_wifibb_40m_en: 1;
+        /* clk_wifibb_44m_en : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_wifibb_44m_en: 1;
+        /* clk_wifibb_80m_en : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_wifibb_80m_en: 1;
+        /* clk_wifibb_40x_en : R/W; bitpos: [4]; default: 0;*/
+        uint32_t clk_wifibb_40x_en: 1;
+        /* clk_wifibb_80x_en : R/W; bitpos: [5]; default: 0;*/
+        uint32_t clk_wifibb_80x_en: 1;
+        /* clk_wifibb_40x1_en : R/W; bitpos: [6]; default: 0;*/
+        uint32_t clk_wifibb_40x1_en: 1;
+        /* clk_wifibb_80x1_en : R/W; bitpos: [7]; default: 0;*/
+        uint32_t clk_wifibb_80x1_en: 1;
+        /* clk_wifibb_160x1_en : R/W; bitpos: [8]; default: 0;*/
+        uint32_t clk_wifibb_160x1_en: 1;
+        /* clk_wifimac_en : R/W; bitpos: [9]; default: 0;*/
+        uint32_t clk_wifimac_en: 1;
+        /* clk_wifi_apb_en : R/W; bitpos: [10]; default: 0;*/
+        uint32_t clk_wifi_apb_en: 1;
+        /* clk_fe_20m_en : R/W; bitpos: [11]; default: 0;*/
+        uint32_t clk_fe_20m_en: 1;
+        /* clk_fe_40m_en : R/W; bitpos: [12]; default: 0;*/
+        uint32_t clk_fe_40m_en: 1;
+        /* clk_fe_80m_en : R/W; bitpos: [13]; default: 0;*/
+        uint32_t clk_fe_80m_en: 1;
+        /* clk_fe_160m_en : R/W; bitpos: [14]; default: 0;*/
+        uint32_t clk_fe_160m_en: 1;
+        /* clk_fe_apb_en : R/W; bitpos: [15]; default: 0;*/
+        uint32_t clk_fe_apb_en: 1;
+        /* clk_bt_apb_en : R/W; bitpos: [16]; default: 0;*/
+        uint32_t clk_bt_apb_en: 1;
+        /* clk_btbb_en : R/W; bitpos: [17]; default: 0;*/
+        uint32_t clk_btbb_en: 1;
+        /* clk_btmac_en : R/W; bitpos: [18]; default: 0;*/
+        uint32_t clk_btmac_en: 1;
+        /* clk_fe_pwdet_adc_en : R/W; bitpos: [19]; default: 0;*/
+        uint32_t clk_fe_pwdet_adc_en: 1;
+        /* clk_fe_adc_en : R/W; bitpos: [20]; default: 0;*/
+        uint32_t clk_fe_adc_en: 1;
+        /* clk_fe_dac_en : R/W; bitpos: [21]; default: 0;*/
+        uint32_t clk_fe_dac_en: 1;
+        /* clk_fe_sdm_en : R/W; bitpos: [22]; default: 0;*/
+        uint32_t clk_fe_sdm_en: 1;
+        /* clk_fe_txlogain_en : R/W; bitpos: [23]; default: 0;*/
+        uint32_t clk_fe_txlogain_en: 1;
+        /* clk_fe_32m_en : R/W; bitpos: [24]; default: 0;*/
+        uint32_t clk_fe_32m_en: 1;
+        /* clk_fe_16m_en : R/W; bitpos: [25]; default: 0;*/
+        uint32_t clk_fe_16m_en: 1;
+        uint32_t reserved_26: 6;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf1_reg_t;
+
+/* Type of wifi_bb_cfg register*/
+typedef union {
+    struct {
+        /* wifi_bb_cfg : R/W; bitpos: [31:0]; default: 0;*/
+        uint32_t wifi_bb_cfg: 32;
+    };
+    uint32_t val;
+} modem_syscon_wifi_bb_cfg_reg_t;
+
+/* Type of fe_cfg register*/
+typedef union {
+    struct {
+        /* fe_cfg : R/W; bitpos: [31:0]; default: 0;*/
+        uint32_t fe_cfg: 32;
+    };
+    uint32_t val;
+} modem_syscon_fe_cfg_reg_t;
+
+/* Type of mem_rf1_conf register*/
+typedef union {
+    struct {
+        /* modem_rf1_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;*/
+        uint32_t modem_rf1_mem_aux_ctrl: 32;
+    };
+    uint32_t val;
+} modem_syscon_mem_rf1_conf_reg_t;
+
+/* Type of mem_rf2_conf register*/
+typedef union {
+    struct {
+        /* modem_rf2_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;*/
+        uint32_t modem_rf2_mem_aux_ctrl: 32;
+    };
+    uint32_t val;
+} modem_syscon_mem_rf2_conf_reg_t;
+
+/* Type of btmac_clk_cfg register*/
+typedef union {
+    struct {
+        /* clk_btmac_low_rate : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_btmac_low_rate: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} modem_syscon_btmac_clk_cfg_reg_t;
+
+/* Type of clk_conf_force_on_2 register*/
+typedef union {
+    struct {
+        /* clk_wifi_apb_fo : R/W; bitpos: [0]; default: 0;*/
+        uint32_t clk_wifi_apb_fo: 1;
+        /* clk_wifibb_160m_x1_fo : R/W; bitpos: [1]; default: 0;*/
+        uint32_t clk_wifibb_160m_x1_fo: 1;
+        /* clk_wifibb_22m_fo : R/W; bitpos: [2]; default: 0;*/
+        uint32_t clk_wifibb_22m_fo: 1;
+        /* clk_wifibb_40m_fo : R/W; bitpos: [3]; default: 0;*/
+        uint32_t clk_wifibb_40m_fo: 1;
+        /* clk_wifibb_40m_x1_fo : R/W; bitpos: [4]; default: 0;*/
+        uint32_t clk_wifibb_40m_x1_fo: 1;
+        /* clk_wifibb_40m_x_int_fo : R/W; bitpos: [5]; default: 0;*/
+        uint32_t clk_wifibb_40m_x_int_fo: 1;
+        /* clk_wifibb_44m_fo : R/W; bitpos: [6]; default: 0;*/
+        uint32_t clk_wifibb_44m_fo: 1;
+        /* clk_wifibb_80m_fo : R/W; bitpos: [7]; default: 0;*/
+        uint32_t clk_wifibb_80m_fo: 1;
+        /* clk_wifibb_80m_x1_fo : R/W; bitpos: [8]; default: 0;*/
+        uint32_t clk_wifibb_80m_x1_fo: 1;
+        /* clk_wifibb_80m_x_int_fo : R/W; bitpos: [9]; default: 0;*/
+        uint32_t clk_wifibb_80m_x_int_fo: 1;
+        /* clk_wifibb_apb_44m_fo : R/W; bitpos: [10]; default: 0;*/
+        uint32_t clk_wifibb_apb_44m_fo: 1;
+        /* clk_wifimac_ahb_fo : R/W; bitpos: [11]; default: 0;*/
+        uint32_t clk_wifimac_ahb_fo: 1;
+        /* clk_wifimac_fo : R/W; bitpos: [12]; default: 0;*/
+        uint32_t clk_wifimac_fo: 1;
+        /* clk_zbmac_ahb_fo : R/W; bitpos: [13]; default: 0;*/
+        uint32_t clk_zbmac_ahb_fo: 1;
+        /* clk_zbmac_apb_16m_fo : R/W; bitpos: [14]; default: 0;*/
+        uint32_t clk_zbmac_apb_16m_fo: 1;
+        /* clk_zbmac_apb_fo : R/W; bitpos: [15]; default: 0;*/
+        uint32_t clk_zbmac_apb_fo: 1;
+        /* clk_zbmac_fo : R/W; bitpos: [16]; default: 0;*/
+        uint32_t clk_zbmac_fo: 1;
+        /* clk_wifibb_80m_x_fo : R/W; bitpos: [17]; default: 0;*/
+        uint32_t clk_wifibb_80m_x_fo: 1;
+        /* clk_wifibb_40m_x_fo : R/W; bitpos: [18]; default: 0;*/
+        uint32_t clk_wifibb_40m_x_fo: 1;
+        /* clk_fe_adc_fo : R/W; bitpos: [19]; default: 0;*/
+        uint32_t clk_fe_adc_fo: 1;
+        /* clk_fe_txlogain_inf_fo : R/W; bitpos: [20]; default: 0;*/
+        uint32_t clk_fe_txlogain_inf_fo: 1;
+        /* clk_fe_sdm_inf_fo : R/W; bitpos: [21]; default: 0;*/
+        uint32_t clk_fe_sdm_inf_fo: 1;
+        /* clk_fe_sdm_fo : R/W; bitpos: [22]; default: 0;*/
+        uint32_t clk_fe_sdm_fo: 1;
+        /* clk_fe_sdm_div4_fo : R/W; bitpos: [23]; default: 0;*/
+        uint32_t clk_fe_sdm_div4_fo: 1;
+        /* clk_fe_sdm_div2_fo : R/W; bitpos: [24]; default: 0;*/
+        uint32_t clk_fe_sdm_div2_fo: 1;
+        /* clk_fe_16m_fo : R/W; bitpos: [25]; default: 0;*/
+        uint32_t clk_fe_16m_fo: 1;
+        /* clk_fe_32m_fo : R/W; bitpos: [26]; default: 0;*/
+        uint32_t clk_fe_32m_fo: 1;
+        uint32_t reserved_27: 5;
+    };
+    uint32_t val;
+} modem_syscon_clk_conf_force_on_2_reg_t;
+
+/* Type of apb_timeout_conf register*/
+typedef union {
+    struct {
+        /* apb_timeout_thres : R/W; bitpos: [15:0]; default: 65535;*/
+        uint32_t apb_timeout_thres: 16;
+        /* apb_timeout_protect_en : R/W; bitpos: [16]; default: 1;*/
+        uint32_t apb_timeout_protect_en: 1;
+        /* apb_timeout_int_clr : WO; bitpos: [17]; default: 0;*/
+        uint32_t apb_timeout_int_clr: 1;
+        /* modem_apb_timeout_exception_pid : RO; bitpos: [21:18]; default: 0;*/
+        uint32_t modem_apb_timeout_exception_pid: 4;
+        /* modem_apb_timeout_int : RO; bitpos: [22]; default: 0;*/
+        uint32_t modem_apb_timeout_int: 1;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} modem_syscon_apb_timeout_conf_reg_t;
+
+/* Type of apb_timeout_exception_addr register*/
+typedef union {
+    struct {
+        /* modem_apb_timeout_exception_paddr : RO; bitpos: [31:0]; default: 0;*/
+        uint32_t modem_apb_timeout_exception_paddr: 32;
+    };
+    uint32_t val;
+} modem_syscon_apb_timeout_exception_addr_reg_t;
+
+/* Type of date register*/
+typedef union {
+    struct {
+        /* date : R/W; bitpos: [27:0]; default: 37823024;*/
+        uint32_t date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} modem_syscon_date_reg_t;
+
+typedef struct {
+    volatile modem_syscon_test_conf_reg_t test_conf;
+    volatile modem_syscon_clk_conf_reg_t clk_conf;
+    volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on;
+    volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st;
+    volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf;
+    volatile modem_syscon_clk_conf1_reg_t clk_conf1;
+    volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
+    volatile modem_syscon_fe_cfg_reg_t fe_cfg;
+    volatile modem_syscon_mem_rf1_conf_reg_t mem_rf1_conf;
+    volatile modem_syscon_mem_rf2_conf_reg_t mem_rf2_conf;
+    volatile modem_syscon_btmac_clk_cfg_reg_t btmac_clk_cfg;
+    volatile modem_syscon_clk_conf_force_on_2_reg_t clk_conf_force_on_2;
+    volatile modem_syscon_apb_timeout_conf_reg_t apb_timeout_conf;
+    volatile modem_syscon_apb_timeout_exception_addr_reg_t apb_timeout_exception_addr;
+    volatile modem_syscon_date_reg_t date;
+} modem_syscon_dev_t;
+
+extern modem_syscon_dev_t MODEM_SYSCON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(modem_syscon_dev_t) == 0x3c, "Invalid size of modem_syscon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h4/include/modem/reg_base.h

@@ -0,0 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#define DR_REG_MODEM_SYSCON_BASE  0x600C9C00
+#define DR_REG_MODEM_LPCON_BASE   0x600CF000

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -39,6 +39,10 @@ config SOC_FLASH_ENC_SUPPORTED
     bool
     default y
 
+config SOC_MODEM_CLOCK_SUPPORTED
+    bool
+    default y
+
 config SOC_WDT_SUPPORTED
     bool
     default y

components/soc/esp32h4/include/soc/periph_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -62,7 +62,7 @@ typedef enum {
     /*  !!! Don't append soc modules here !!! */
 } periph_module_t;
 
-#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
+#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE
 #define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
 #define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
 #define IS_MODEM_MODULE(periph)  ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))

components/soc/esp32h4/include/soc/soc_caps.h

@@ -64,6 +64,7 @@
 // #define SOC_ECC_SUPPORTED               1    // TODO: [ESP32H4] IDF-12264
 #define SOC_FLASH_ENC_SUPPORTED         1       // TODO: [ESP32H4] IDF-12261
 // #define SOC_SECURE_BOOT_SUPPORTED       1    // TODO: [ESP32H4] IDF-12262
+#define SOC_MODEM_CLOCK_SUPPORTED       1
 
 // #define SOC_BOD_SUPPORTED               1    // TODO: [ESP32H4] IDF-12295
 // #define SOC_APM_SUPPORTED               1    // TODO: [ESP32H4] IDF-12256

components/soc/esp32h4/ld/esp32h4.peripherals.ld

@@ -74,3 +74,5 @@ PROVIDE ( LP_TIMER            = 0x600B5000 );
 PROVIDE ( LP_WDT              = 0x600B5400 );
 PROVIDE ( TOUCH_SENS          = 0x600B5800 );
 PROVIDE ( TOUCH_AON           = 0x600B5C00 );
+PROVIDE ( MODEM_SYSCON        = 0x600C9C00 );
+PROVIDE ( MODEM_LPCON         = 0x600CF000 );