From 8777791852d86a7ac617b96ff86881d0ad4b454e Mon Sep 17 00:00:00 2001 From: Shen Mengjing Date: Mon, 25 Aug 2025 11:54:42 +0800 Subject: [PATCH] docs: Update CN translation for toolchain.rst and ram-usage.rst --- .../release-6.x/6.0/toolchain.rst | 14 ++--- .../api-guides/performance/ram-usage.rst | 1 + .../release-6.x/6.0/toolchain.rst | 55 +++++++++++++++++++ 3 files changed, 60 insertions(+), 10 deletions(-) diff --git a/docs/en/migration-guides/release-6.x/6.0/toolchain.rst b/docs/en/migration-guides/release-6.x/6.0/toolchain.rst index 65fd8f781a..38499bb075 100644 --- a/docs/en/migration-guides/release-6.x/6.0/toolchain.rst +++ b/docs/en/migration-guides/release-6.x/6.0/toolchain.rst @@ -113,15 +113,9 @@ The header ```` is no longer available in Picolibc. To ensure comp RISC-V Chips and Misaligned Memory Access in LibC Functions ----------------------------------------------------------- - Espressif RISC-V chips can perform misaligned memory accesses with only a small - performance penalty compared to aligned accesses. + Espressif RISC-V chips can perform misaligned memory accesses with only a small performance penalty compared to aligned accesses. - Previously, LibC functions that operate on memory (such as copy or comparison - functions) were implemented using byte-by-byte operations when a non-word-aligned - pointer was passed. Now, these functions use word (4-byte) load/store operations - whenever possible, resulting in a significant performance increase. These optimized - implementations are enabled by default via :ref:`CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS`, - which reduces the application’s memory budget (IRAM) by approximately 800–1000 bytes. + Previously, LibC functions that operate on memory (such as copy or comparison functions) were implemented using byte-by-byte operations when a non-word-aligned pointer was passed. Now, these functions use word (4-byte) load/store operations whenever possible, resulting in a significant performance increase. These optimized implementations are enabled by default via :ref:`CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS`, which reduces the application's memory budget (IRAM) by approximately 800–1000 bytes. The table below shows benchmark results on the ESP32-C3 chip using 4096-byte buffers: @@ -155,8 +149,8 @@ The header ```` is no longer available in Picolibc. To ensure comp - 69.8 .. note:: - The results above apply to misaligned memory operations. - Performance for aligned memory operations remains unchanged. + + The results above apply to misaligned memory operations. Performance for aligned memory operations remains unchanged. Functions with Improved Performance ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-guides/performance/ram-usage.rst b/docs/zh_CN/api-guides/performance/ram-usage.rst index 68f3dd9f32..4f4cde91bd 100644 --- a/docs/zh_CN/api-guides/performance/ram-usage.rst +++ b/docs/zh_CN/api-guides/performance/ram-usage.rst @@ -194,6 +194,7 @@ IRAM 优化 :SOC_GPSPI_SUPPORTED: - 启用 :ref:`CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH`。只要未启用 :ref:`CONFIG_SPI_MASTER_ISR_IN_IRAM` 选项，且没有从 ISR 中错误地调用堆函数，就可以在所有配置中安全启用此选项。 :esp32c2: - 启用 :ref:`CONFIG_BT_RELEASE_IRAM`。 蓝牙所使用的 data，bss 和 text 段已经被分配在连续的RAM区间。当调用 ``esp_bt_mem_release`` 时，这些段都会被添加到 Heap 中。 这将节省约 22 KB 的 RAM。但要再次使用蓝牙功能，需要重启程序。 - 禁用 :ref:`CONFIG_LIBC_LOCKS_PLACE_IN_IRAM`。若在缓存禁用的情况下，运行中的中断服务程序（即 IRAM ISR）没有使用 libc 锁 API，那么禁用该配置可以节省 IRAM 空间。 + :CONFIG_ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY: - 禁用 :ref:`CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS` 可以节省大约 1000 字节的 IRAM，但会降低性能。 .. only:: esp32 diff --git a/docs/zh_CN/migration-guides/release-6.x/6.0/toolchain.rst b/docs/zh_CN/migration-guides/release-6.x/6.0/toolchain.rst index 62daaf47e1..11faa3aa99 100644 --- a/docs/zh_CN/migration-guides/release-6.x/6.0/toolchain.rst +++ b/docs/zh_CN/migration-guides/release-6.x/6.0/toolchain.rst @@ -107,3 +107,58 @@ Picolibc 已移除 ```` 头文件。为确保跨 libc 实现的兼 #include /* 严重错误：sys/signal.h：没有此文件或目录 */ #include /* 正确：标准且可移植的写法 */ + +.. only:: CONFIG_ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY + + RISC-V 芯片与 LibC 函数中的非对齐内存访问 + ----------------------------------------- + + 乐鑫的 RISC-V 芯片在执行非对齐内存访问时，相比对齐访问仅有较小的性能损耗。 + + 之前，当传入的指针不是按字对齐时，LibC 中涉及内存操作的函数（如拷贝或比较函数）会采用逐字节操作实现。现在，这些函数会尽可能采用字（4 字节）加载/存储操作，从而实现性能大幅提升。这些优化的实现通过 :ref:`CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS` 默认启用，但会减少应用大约 800–1000 字节的内存预算 (IRAM)。 + + 下表展示了在 ESP32-C3 芯片上使用 4096 字节的 buffer 进行基准测试的结果： + + .. list-table:: 基准测试结果 + :header-rows: 1 + :widths: 20 20 20 20 + + * - 函数 + - 旧版（CPU 周期） + - 优化版（CPU 周期） + - 改进 (%) + * - memcpy + - 32873 + - 4200 + - 87.2 + * - memcmp + - 57436 + - 14722 + - 74.4 + * - memmove + - 49336 + - 9237 + - 81.3 + * - strcpy + - 28678 + - 16659 + - 41.9 + * - strcmp + - 36867 + - 11146 + - 69.8 + + .. note:: + + 上述结果适用于非对齐内存操作。对齐内存操作的性能保持不变。 + + 性能得到提升的函数 + ^^^^^^^^^^^^^^^^^^ + + - ``memcpy`` + - ``memcmp`` + - ``memmove`` + - ``strcpy`` + - ``strncpy`` + - ``strcmp`` + - ``strncmp``