From fd20ac807c2ffed502a713a1718b66617fa4f6f2 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Fri, 31 Dec 2021 08:09:43 +0000 Subject: [PATCH 1/2] sleep: fixed ext1 cannot wakeup via RTCIO >= 18 issue Closes https://github.com/espressif/esp-idf/issues/8231 --- components/esp_hw_support/sleep_modes.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c192bf4d47..0aec12faca 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -140,7 +140,7 @@ typedef struct { uint64_t sleep_duration; uint32_t wakeup_triggers : 15; uint32_t ext1_trigger_mode : 1; - uint32_t ext1_rtc_gpio_mask : 18; + uint32_t ext1_rtc_gpio_mask : 22; //22 is the maximum RTCIO number in all chips uint32_t ext0_trigger_level : 1; uint32_t ext0_rtc_gpio_num : 5; uint32_t gpio_wakeup_mask : 6; @@ -152,6 +152,9 @@ typedef struct { uint64_t rtc_ticks_at_sleep_start; } sleep_config_t; + +_Static_assert(22 >= SOC_RTCIO_PIN_COUNT, "Chip has more RTCIOs than 22, should increase ext1_rtc_gpio_mask field size"); + static sleep_config_t s_config = { .pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, From 21b80a969f024204325550f96decd53857566425 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Fri, 31 Dec 2021 16:58:03 +0800 Subject: [PATCH 2/2] soc: updated soc_caps about rtc_io and the format --- components/soc/esp32c3/include/soc/soc_caps.h | 2 +- components/soc/esp32h2/include/soc/soc_caps.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index e50d0d04b0..33503c0284 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -175,7 +175,7 @@ /*-------------------------- RTCIO CAPS --------------------------------------*/ /* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ -#define SOC_RTCIO_PIN_COUNT 0 +#define SOC_RTCIO_PIN_COUNT (0U) /*--------------------------- RSA CAPS ---------------------------------------*/ #define SOC_RSA_MAX_BIT_LEN (3072) diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index ce7406c93b..629834b868 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -163,7 +163,7 @@ /*-------------------------- RTCIO CAPS --------------------------------------*/ /* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ -#define SOC_RTCIO_PIN_COUNT 0 +#define SOC_RTCIO_PIN_COUNT (0U) /*--------------------------- RSA CAPS ---------------------------------------*/ #define SOC_RSA_MAX_BIT_LEN (3072)