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change(psram): update voltage configurations
This commit is contained in:
committed by
Armando (Dou Yiwen)
parent
97702b3579
commit
62440e5b12
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -17,6 +17,22 @@
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#define I2C_BIAS 0x6A
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#define I2C_BIAS_HOSTID 0
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#define I2C_BIAS_DREG_1P6 0
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#define I2C_BIAS_DREG_1P6_MSB 3
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#define I2C_BIAS_DREG_1P6_LSB 0
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#define I2C_BIAS_DREG_1P1 0
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#define I2C_BIAS_DREG_1P1_MSB 7
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#define I2C_BIAS_DREG_1P1_LSB 4
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#define I2C_BIAS_DREG_1P1_PVT 1
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#define I2C_BIAS_DREG_1P1_PVT_MSB 3
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#define I2C_BIAS_DREG_1P1_PVT_LSB 0
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#define I2C_BIAS_DREG_2P2_PVT 1
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#define I2C_BIAS_DREG_2P2_PVT_MSB 7
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#define I2C_BIAS_DREG_2P2_PVT_LSB 4
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#define I2C_BIAS_OR_FORCE_XPD_CK 4
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#define I2C_BIAS_OR_FORCE_XPD_CK_MSB 0
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#define I2C_BIAS_OR_FORCE_XPD_CK_LSB 0
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@@ -17,6 +17,10 @@
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#define I2C_MPLL 0x63
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#define I2C_MPLL_HOSTID 0
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#define I2C_MPLL_IR_CAL_RSTB 1
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#define I2C_MPLL_IR_CAL_RSTB_MSB 5
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#define I2C_MPLL_IR_CAL_RSTB_lSB 5
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#define I2C_MPLL_DIV_REG_ADDR 2
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#define I2C_MPLL_REF_DIV_ADDR I2C_MPLL_DIV_REG_ADDR
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#define I2C_MPLL_REF_DIV_ADDR_MSB 2
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@@ -25,3 +29,7 @@
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#define I2C_MPLL_DIV_ADDR I2C_MPLL_DIV_REG_ADDR
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#define I2C_MPLL_DIV_ADDR_MSB 7
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#define I2C_MPLL_DIV_ADDR_LSB 3
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#define I2C_MPLL_DHREF 3
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#define I2C_MPLL_DHREF_MSB 5
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#define I2C_MPLL_DHREF_LSB 4
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