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Merge branch 'fix/spi_master_halt_using_rc_fast_v5.4' into 'release/v5.4'

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fix(spi_master): fix spi halt when remove device who using rc_fast (v5.4)

See merge request espressif/esp-idf!37002
This commit is contained in:
morris
2025-04-01 09:58:50 +08:00
parent 0e3cdc3b75 9ecfa3a0e7
commit 62ace4d687
5 changed files with 13 additions and 4 deletions
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9
components/esp_driver_spi/src/gpspi/spi_master.c
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@ -584,6 +584,15 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
#if SOC_SPI_SUPPORT_CLK_RC_FAST
if (handle->cfg.clock_source == SPI_CLK_SRC_RC_FAST) {
// If no transactions from other device, acquire the bus to switch module clock to `SPI_CLK_SRC_DEFAULT`
// because `SPI_CLK_SRC_RC_FAST` will be disabled then, which block following transactions
if (handle->host->cur_cs == DEV_NUM_MAX) {
spi_device_acquire_bus(handle, portMAX_DELAY);
SPI_MASTER_PERI_CLOCK_ATOMIC() {
spi_ll_set_clk_source(handle->host->hal.hw, SPI_CLK_SRC_DEFAULT);
}
spi_device_release_bus(handle);
}
periph_rtc_dig_clk8m_disable();
}
#endif

2
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@ -356,7 +356,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6)
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of SPI clock source.

2
components/soc/esp32c6/include/soc/clk_tree_defs.h
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@ -354,7 +354,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of SPI clock source.

2
components/soc/esp32c61/include/soc/clk_tree_defs.h
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@ -248,7 +248,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of SPI clock source.

2
components/soc/esp32h2/include/soc/clk_tree_defs.h
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@ -332,7 +332,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST}
#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M}
/**
* @brief Type of SPI clock source.