From 6356453f8d3d05c6347c6066b2ed9c39ed2a41f2 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Wed, 15 Mar 2023 10:39:52 +0800 Subject: [PATCH] sleep: fix sleep current issue caused by sar adc --- .../include/esp_private/sar_periph_ctrl.h | 10 ++++++++++ components/esp_hw_support/port/esp32/sar_periph_ctrl.c | 7 +++++++ .../esp_hw_support/port/esp32c2/sar_periph_ctrl.c | 7 +++++++ .../esp_hw_support/port/esp32c3/sar_periph_ctrl.c | 7 +++++++ .../esp_hw_support/port/esp32h2/sar_periph_ctrl.c | 5 +++++ .../esp_hw_support/port/esp32s2/sar_periph_ctrl.c | 7 +++++++ .../esp_hw_support/port/esp32s3/sar_periph_ctrl.c | 7 +++++++ components/esp_hw_support/sleep_modes.c | 3 +++ 8 files changed, 53 insertions(+) diff --git a/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h b/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h index 3b15303af4..833ce1f4ff 100644 --- a/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h +++ b/components/esp_hw_support/include/esp_private/sar_periph_ctrl.h @@ -62,6 +62,16 @@ void sar_periph_ctrl_pwdet_power_acquire(void); */ void sar_periph_ctrl_pwdet_power_release(void); +/** + * @brief Enable SAR power when system wakes up + */ +void sar_periph_ctrl_power_enable(void); + +/** + * @brief Disable SAR power when system goes to sleep + */ +void sar_periph_ctrl_power_disable(void); + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/port/esp32/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32/sar_periph_ctrl.c index 90da25dd13..e14cbc40a8 100644 --- a/components/esp_hw_support/port/esp32/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32/sar_periph_ctrl.c @@ -32,6 +32,13 @@ void sar_periph_ctrl_init(void) //Add other periph power control initialisation here } +void sar_periph_ctrl_power_enable(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + void sar_periph_ctrl_power_disable(void) { portENTER_CRITICAL_SAFE(&rtc_spinlock); diff --git a/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c index 1592c44341..7d24940dca 100644 --- a/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c @@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void) //Add other periph power control initialisation here } +void sar_periph_ctrl_power_enable(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + void sar_periph_ctrl_power_disable(void) { portENTER_CRITICAL_SAFE(&rtc_spinlock); diff --git a/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c index f0624593f4..75ce0adb95 100644 --- a/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c @@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void) //Add other periph power control initialisation here } +void sar_periph_ctrl_power_enable(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + void sar_periph_ctrl_power_disable(void) { portENTER_CRITICAL_SAFE(&rtc_spinlock); diff --git a/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c index 437af44dfa..2b154503c7 100644 --- a/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c @@ -29,6 +29,11 @@ void sar_periph_ctrl_init(void) //TODO: IDF-6123 } +void sar_periph_ctrl_power_enable(void) +{ + //TODO: IDF-6123 +} + void sar_periph_ctrl_power_disable(void) { //TODO: IDF-6123 diff --git a/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c index 33ae356d0d..b566f38d6c 100644 --- a/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c @@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void) //Add other periph power control initialisation here } +void sar_periph_ctrl_power_enable(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + void sar_periph_ctrl_power_disable(void) { portENTER_CRITICAL_SAFE(&rtc_spinlock); diff --git a/components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c index b00236323f..d8cd4fc522 100644 --- a/components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c @@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void) //Add other periph power control initialisation here } +void sar_periph_ctrl_power_enable(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + void sar_periph_ctrl_power_disable(void) { portENTER_CRITICAL_SAFE(&rtc_spinlock); diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index b942100081..c5eec7ba47 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -46,6 +46,7 @@ #include "esp_rom_sys.h" #include "brownout.h" #include "esp_private/sleep_retention.h" +#include "esp_private/sar_periph_ctrl.h" #ifdef CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/cache.h" @@ -345,6 +346,7 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(void) #if REGI2C_ANA_CALI_PD_WORKAROUND regi2c_analog_cali_reg_read(); #endif + sar_periph_ctrl_power_disable(); } /** @@ -352,6 +354,7 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(void) */ inline static void IRAM_ATTR misc_modules_wake_prepare(void) { + sar_periph_ctrl_power_enable(); #if SOC_PM_SUPPORT_CPU_PD || SOC_PM_SUPPORT_TAGMEM_PD sleep_disable_memory_retention(); #endif