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feat(power_glich): support power_glitch of esp32c5_eco1 and above, eco32c61 eco2 and above

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This commit is contained in:
chaijie@espressif.com
2024-11-26 17:11:25 +08:00
committed by BOT
parent 7f46f6152e
commit 63f72f659d
7 changed files with 58 additions and 32 deletions
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5
components/bootloader_support/private_include/bootloader_soc.h
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@ -25,12 +25,11 @@ void bootloader_ana_super_wdt_reset_config(bool enable);
void bootloader_ana_clock_glitch_reset_config(bool enable);
/**
* @brief Configure analog power glitch reset & glitch reset dref
* @brief Configure analog power glitch reset
*
* @param enable Boolean to enable or disable power glitch reset
* @param dref voltage threshold
*/
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref);
void bootloader_power_glitch_reset_config(bool enable);
#ifdef __cplusplus
}

6
components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
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@ -94,11 +94,7 @@ static inline void bootloader_ana_reset_config(void)
{
//Enable BOD reset (mode1)
brownout_ll_ana_reset_enable(true);
if (efuse_hal_chip_revision() == 0) {
// decrease power glitch reset voltage to avoid start the glitch reset
uint8_t power_glitch_dref = 0;
bootloader_power_glitch_reset_config(true, power_glitch_dref);
}
bootloader_power_glitch_reset_config(true);
}
esp_err_t bootloader_init(void)

18
components/bootloader_support/src/esp32c5/bootloader_soc.c
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@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
void bootloader_power_glitch_reset_config(bool enable)
{
assert(dref < 8);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
if (enable) {
//only detect VDDPST POWER GLITCH
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_XTAL, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO1
if (enable) {
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO1
} else {
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
}

3
components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
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@ -95,8 +95,7 @@ static inline void bootloader_ana_reset_config(void)
{
//Enable BOD reset (mode1)
brownout_ll_ana_reset_enable(true);
uint8_t power_glitch_dref = 0;
bootloader_power_glitch_reset_config(true, power_glitch_dref);
bootloader_power_glitch_reset_config(true);
}
esp_err_t bootloader_init(void)

18
components/bootloader_support/src/esp32c61/bootloader_soc.c
View File

@ -17,18 +17,18 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
void bootloader_power_glitch_reset_config(bool enable)
{
assert(dref < 8);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
if (enable) {
//only detect VDDPST POWER GLITCH
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLLBB, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_XPD_VDET_PLL, 0);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);//default val for chip from ECO2
if (enable) {
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);//default val for chip from ECO2
} else {
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
}

18
components/soc/esp32c5/include/soc/regi2c_saradc.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -90,6 +90,22 @@
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 0x3
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 0x3
#define POWER_GLITCH_XPD_VDET_PERIF 10
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0
#define POWER_GLITCH_XPD_VDET_VDDPST 10
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 1
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 1
#define POWER_GLITCH_XPD_VDET_XTAL 10
#define POWER_GLITCH_XPD_VDET_XTAL_MSB 2
#define POWER_GLITCH_XPD_VDET_XTAL_LSB 2
#define POWER_GLITCH_XPD_VDET_PLL 10
#define POWER_GLITCH_XPD_VDET_PLL_MSB 3
#define POWER_GLITCH_XPD_VDET_PLL_LSB 3
#define POWER_GLITCH_DREF_VDET_PERIF 11
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0

16
components/soc/esp32c61/include/soc/regi2c_saradc.h
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@ -78,6 +78,22 @@
#define I2C_SAR2_ENCAL_GND_MSB 7
#define I2C_SAR2_ENCAL_GND_LSB 7
#define POWER_GLITCH_XPD_VDET_PERIF 10
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0
#define POWER_GLITCH_XPD_VDET_VDDPST 10
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 1
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 1
#define POWER_GLITCH_XPD_VDET_PLLBB 10
#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 2
#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 2
#define POWER_GLITCH_XPD_VDET_PLL 10
#define POWER_GLITCH_XPD_VDET_PLL_MSB 3
#define POWER_GLITCH_XPD_VDET_PLL_LSB 3
#define POWER_GLITCH_DREF_VDET_PERIF 11
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0