From de798541dce20f0dfc4709d5540dfec1ef87e2e4 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 15 Dec 2020 18:24:07 +0100 Subject: [PATCH 1/2] tools: use riscv32-esp-elf toolchain for ESP32-S2 RISC-V ULP riscv32-esp-elf toolchain (used for ESP32-C3) can also be used for ESP32-S2 RISC-V ULP coprocessor. This removes the riscv-none-embed-gcc toolchain which was originally used for the ULP, and updates the docs and CMake files to use riscv32-esp-elf. Some flags are cleaned up and workarounds removed from CMake toolchain file. --- .../cmake/toolchain-esp32s2-ulp-riscv.cmake | 25 ++++----- docs/en/api-guides/tools/idf-tools-notes.inc | 5 -- docs/en/api-guides/ulp-risc-v.rst | 10 ++-- .../api-guides/tools/idf-tools-notes.inc | 5 -- docs/zh_CN/api-guides/ulp-risc-v.rst | 11 ++-- tools/ci/config/build.yml | 6 -- tools/tools.json | 56 +++++++++---------- 7 files changed, 46 insertions(+), 72 deletions(-) diff --git a/components/ulp/cmake/toolchain-esp32s2-ulp-riscv.cmake b/components/ulp/cmake/toolchain-esp32s2-ulp-riscv.cmake index 15d6145ded..5e1b497b6a 100644 --- a/components/ulp/cmake/toolchain-esp32s2-ulp-riscv.cmake +++ b/components/ulp/cmake/toolchain-esp32s2-ulp-riscv.cmake @@ -1,18 +1,15 @@ # CMake toolchain file for ULP-RISC-V set(CMAKE_SYSTEM_NAME Generic) -# Not best solution, needs to figure why the compiler detection -# fails in CI -set(CMAKE_C_COMPILER_FORCED TRUE) -set(CMAKE_CXX_COMPILER_FORCED TRUE) +set(CMAKE_C_COMPILER "riscv32-esp-elf-gcc") +set(CMAKE_CXX_COMPILER "riscv32-esp-elf-g++") +set(CMAKE_ASM_COMPILER "riscv32-esp-elf-gcc") -set(CMAKE_C_COMPILER "riscv-none-embed-gcc") -set(CMAKE_ASM_COMPILER "riscv-none-embed-gcc") - -if(NOT ASM_DIALECT) - set(ASM_DIALECT "") -endif() - -set(CMAKE_C_FLAGS "-Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections") -set(CMAKE_ASM_FLAGS "-march=rv32imc -mdiv -x assembler-with-cpp -fdata-sections -ffunction-sections") -set(CMAKE_EXE_LINKER_FLAGS "-march=rv32imc --specs=nano.specs --specs=nosys.specs") +set(CMAKE_C_FLAGS "-Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections" + CACHE STRING "C Compiler Base Flags") +set(CMAKE_CXX_FLAGS "-Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections" + CACHE STRING "C++ Compiler Base Flags") +set(CMAKE_ASM_FLAGS "-march=rv32imc -x assembler-with-cpp" + CACHE STRING "Assembler Base Flags") +set(CMAKE_EXE_LINKER_FLAGS "-march=rv32imc --specs=nano.specs --specs=nosys.specs" + CACHE STRING "Linker Base Flags") diff --git a/docs/en/api-guides/tools/idf-tools-notes.inc b/docs/en/api-guides/tools/idf-tools-notes.inc index 41ca6e01d4..9b076e96a3 100644 --- a/docs/en/api-guides/tools/idf-tools-notes.inc +++ b/docs/en/api-guides/tools/idf-tools-notes.inc @@ -25,11 +25,6 @@ .. tool-esp32s2ulp-elf-notes ---- - -.. tool-riscv-none-embed-gcc-notes - - --- .. tool-openocd-esp32-notes diff --git a/docs/en/api-guides/ulp-risc-v.rst b/docs/en/api-guides/ulp-risc-v.rst index b058fd30f5..3b3e559464 100644 --- a/docs/en/api-guides/ulp-risc-v.rst +++ b/docs/en/api-guides/ulp-risc-v.rst @@ -11,11 +11,11 @@ The ULP-RISC-V coprocessor is a variant of the ULP, present in ESP32-S2. Similar Installing the ULP-RISC-V Toolchain ----------------------------------- -The ULP-RISC-V coprocessor code is written in C (assembly is also possible) and compiled using the `riscv-embedded toolchain`_. +The ULP-RISC-V coprocessor code is written in C (assembly is also possible) and compiled using RISC-V toolchain based on GCC. -If you have already set up ESP-IDF with CMake build system according to the :doc:`Getting Started Guide <../../get-started/index>`, then you need to perform an extra step to get the ULP-RISC-V toolchain installed, execute the command below inside the IDF folder:: +If you have already set up ESP-IDF with CMake build system according to the :doc:`Getting Started Guide <../../get-started/index>`, then the toolchain should already be installed. -$ idf_tools.py install riscv-none-embed-gcc +.. note: In earlier versions of ESP-IDF, RISC-V toolchain had a different prefix: `riscv-none-embed-gcc`. Compiling the ULP-RISC-V Code @@ -56,7 +56,7 @@ To compile the ULP-RISC-V code as part of the component, the following steps mus 5. **Dump the contents of the ELF file into a binary** (``ulp_app_name.bin``) which can then be embedded into the application. - 6. **Generate a list of global symbols** (``ulp_app_name.sym``) in the ELF file using ``riscv-none-embed-nm``. + 6. **Generate a list of global symbols** (``ulp_app_name.sym``) in the ELF file using ``riscv32-esp-elf-nm``. 7. **Create an LD export script and header file** (``ulp_app_name.ld`` and ``ulp_app_name.h``) containing the symbols from ``ulp_app_name.sym``. This is done using the ``esp32ulp_mapgen.py`` utility. @@ -147,5 +147,3 @@ The program runs until the field ``RTC_CNTL_COCPU_DONE`` in register ``RTC_CNTL_ To disable the timer (effectively preventing the ULP program from running again), please clear the ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` bit in the ``RTC_CNTL_STATE0_REG`` register. This can be done both from the ULP code and from the main program. - -.. _riscv-embedded toolchain: https://xpack.github.io/riscv-none-embed-gcc/ diff --git a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc index 3e22db2113..37eda3df41 100644 --- a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc +++ b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc @@ -27,11 +27,6 @@ .. tool-esp32s2ulp-elf-notes ---- - -.. tool-riscv-none-embed-gcc-notes - - --- .. tool-openocd-esp32-notes diff --git a/docs/zh_CN/api-guides/ulp-risc-v.rst b/docs/zh_CN/api-guides/ulp-risc-v.rst index 2eb1ade778..307afabccb 100644 --- a/docs/zh_CN/api-guides/ulp-risc-v.rst +++ b/docs/zh_CN/api-guides/ulp-risc-v.rst @@ -11,12 +11,11 @@ ULP-RISC-V 协处理器是 ULP 的一种变体，用于 ESP32-S2。与 ULP 类 安装 ULP-RISC-V 工具链 ----------------------------------- -ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），使用 `riscv-embedded toolchain`_ 进行编译。 +ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），使用基于GCC的 RISC-V 工具链进行编译。 -如果你已依照 :doc:`快速入门指南 <../../get-started/index>` 中的介绍安装好了 ESP-IDF 及其 CMake 构建系统，还需要在 IDF 文件夹中执行以下指令，安装 ULP-RISC-V 工具链:: - -$ idf_tools.py install riscv-none-embed-gcc +如果你已依照 :doc:`快速入门指南 <../../get-started/index>` 中的介绍安装好了 ESP-IDF 及其 CMake 构建系统，那么 ULP-RISC-V 工具链已经被默认安装到了你的开发环境中。 +.. note: 在早期版本的ESP-IDF中，RISC-V工具链具有不同的名称：`riscv-none-embed-gcc`。 编译 ULP-RISC-V 代码 ----------------------------- @@ -25,7 +24,7 @@ $ idf_tools.py install riscv-none-embed-gcc 1. ULP-RISC-V 代码以 C 语言或汇编语言编写（必须使用 `.S` 扩展名)，必须放在组件目录中一个独立的目录中，例如 `ulp/`。 -.. 注意：当注册组件时（通过 ``idf_component_register``），该目录不应被添加至 ``SRC_DIRS`` 参数，因为目前 ULP-FSM 需要进行此步骤。如何正确添加 ULP 源文件，请见以下步骤。 +.. note: 当注册组件时（通过 ``idf_component_register``），该目录不应被添加至 ``SRC_DIRS`` 参数，因为目前 ULP-FSM 需要进行此步骤。如何正确添加 ULP 源文件，请见以下步骤。 2. 注册后从组件 CMakeLists.txt 中调用 ``ulp_embed_binary`` 示例如下:: @@ -147,5 +146,3 @@ ULP-RISC-V 协处理器由定时器启动，调用 :cpp:func:`ulp_riscv_run` 即 如需禁用定时器（有效防止 ULP 程序再次运行），请清除 ``RTC_CNTL_STATE0_REG`` 寄存器中的 ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` 位，此项操作可在 ULP 代码或主程序中进行。 - -.. _riscv-embedded toolchain: https://xpack.github.io/riscv-none-embed-gcc/ diff --git a/tools/ci/config/build.yml b/tools/ci/config/build.yml index 21d35a1469..eab66f9395 100644 --- a/tools/ci/config/build.yml +++ b/tools/ci/config/build.yml @@ -115,9 +115,6 @@ build_ssc_esp32s2: TEST_TYPE: "unit_test" PYTHON_VER: 3 script: - # RISC-V toolchain is optional but ULP may need it, so install: - - $IDF_PATH/tools/idf_tools.py install riscv-none-embed-gcc - - . $IDF_PATH/export.sh - ${IDF_PATH}/tools/ci/find_apps_build_apps.sh - cd $CI_PROJECT_DIR/tools/unit-test-app - python tools/UnitTestParser.py ${BUILD_PATH} @@ -155,9 +152,6 @@ build_esp_idf_tests_cmake_esp32s3: BUILD_PATH: ${CI_PROJECT_DIR}/build_${TEST_PREFIX} PYTHON_VER: 3 script: - # RISC-V toolchain is optional but ULP may need it, so install: - - $IDF_PATH/tools/idf_tools.py install riscv-none-embed-gcc - - . $IDF_PATH/export.sh # it's not possible to build 100% out-of-tree and have the "artifacts" # mechanism work, but this is the next best thing - ${IDF_PATH}/tools/ci/find_apps_build_apps.sh diff --git a/tools/tools.json b/tools/tools.json index 3fa458330e..0f4a6cc904 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -51,7 +51,7 @@ "win64": { "sha256": "58419852fefb7111fdec056ac2fd7c4bd09c1f4c17610a761a97b788413527cf", "size": 106855139, - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r3/xtensa-esp32-elf-gcc8_4_0-esp-2020r3-win64.zip" + "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-gcc8_4_0-esp-2020r3-win64.zip" } } ] @@ -169,58 +169,56 @@ ] }, { - "description": "Toolchain for RISC-V", + "description": "Toolchain for 32-bit RISC-V based on GCC", "export_paths": [ [ - "xPacks", - "riscv-none-embed-gcc", - "8.2.0-3.1", + "riscv32-esp-elf", "bin" ] ], "export_vars": {}, - "info_url": "https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack", - "install": "on_request", - "license": "MIT", - "name": "riscv-none-embed-gcc", + "info_url": "https://github.com/espressif/crosstool-NG", + "install": "always", + "license": "GPL-3.0-with-GCC-exception", + "name": "riscv32-esp-elf", "version_cmd": [ - "riscv-none-embed-gcc", + "riscv32-esp-elf-gcc", "--version" ], - "version_regex": "(riscv-none-embed-gcc) \\(xPack GNU RISC-V Embedded GCC, 64-bit\\) (8.2.0)", + "version_regex": "\\(crosstool-NG\\s+(?:crosstool-ng-)?([0-9a-zA-Z\\.\\-_]+)\\)\\s*([0-9\\.]+)", "version_regex_replace": "\\1-\\2", "versions": [ { "linux-amd64": { - "sha256": "3d40fab50ebad8424ff85748f25d2eaee50f86a5d5222abd7a45a2e490f1e4f5", - "size": 216042047, - "url": "https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.2.0-3.1/xpack-riscv-none-embed-gcc-8.2.0-3.1-linux-x64.tgz" + "sha256": "425454c5c4e2cde5dd2dd3a1d398befc70addf71547840fb6d0ec4b307b08894", + "size": 152042971, + "url": "https://dl.espressif.com/dl/toolchains/preview/riscv32-esp-elf-gcc8_4_0-crosstool-ng-1.24.0-123-g64eb9ff-linux-amd64.tar.gz" }, - "linux-i686": { - "sha256": "2e856ee33ef544a2405183366cdf299da2cca697e8cc57627dfaad8ab4460a99", - "size": 219854326, - "url": "https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.2.0-3.1/xpack-riscv-none-embed-gcc-8.2.0-3.1-linux-x32.tgz" + "linux-armel": { + "sha256": "8ae098751b5196ca8a80d832cc9930bc4d639762a6cb22be3cfe0a8d71b2f230", + "size": 150801079, + "url": "https://dl.espressif.com/dl/toolchains/preview/riscv32-esp-elf-gcc8_4_0-crosstool-ng-1.24.0-123-g64eb9ff-linux-armel.tar.gz" }, "macos": { - "sha256": "48ece50b7272a8e49e56e37f54f9962f93dce4ca44f1bb4c8113fab0230fbdf1", - "size": 214715632, - "url": "https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.2.0-3.1/xpack-riscv-none-embed-gcc-8.2.0-3.1-darwin-x64.tgz" + "sha256": "35b1aef85b7e6b4268774f627e8e835d087bcf8b9972cfb6436614aa2e40d4a9", + "size": 158594401, + "url": "https://dl.espressif.com/dl/toolchains/preview/riscv32-esp-elf-gcc8_4_0-crosstool-ng-1.24.0-123-g64eb9ff-macos.tar.gz" }, - "name": "riscv-none-embed-gcc-8.2.0", + "name": "1.24.0.123_64eb9ff-8.4.0", "status": "recommended", "win32": { - "sha256": "78bcd52f7b404133de3b2f9568e7101c1de747f98db3a7b0d6251b75a1754867", - "size": 232387519, - "url": "https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.2.0-3.1/xpack-riscv-none-embed-gcc-8.2.0-3.1-win32-x32.zip" + "sha256": "4f576b08620f57c270ac677cc94dce2767fff72d27a539e348d448f63b480d1f", + "size": 190014086, + "url": "https://dl.espressif.com/dl/toolchains/preview/riscv32-esp-elf-gcc8_4_0-crosstool-ng-1.24.0-123-g64eb9ff-win32.zip" }, "win64": { - "sha256": "98b60720607f1400081806d60d70796b30399f8b426e2c790a4abb0bffb9e5ec", - "size": 241927614, - "url": "https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.2.0-3.1/xpack-riscv-none-embed-gcc-8.2.0-3.1-win32-x64.zip" + "sha256": "51e392ed88498f3fc4ad07e9ff4b5225f6533b1c363ecd7dd67c10d8d31b6b23", + "size": 191565525, + "url": "https://dl.espressif.com/dl/toolchains/preview/riscv32-esp-elf-gcc8_4_0-crosstool-ng-1.24.0-123-g64eb9ff-win64.zip" } } ] - }, + } { "description": "Toolchain for ESP32 ULP coprocessor", "export_paths": [ From 7fe16bae251ded4a2058d80f59ce6651586c96dc Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Tue, 29 Dec 2020 10:00:45 +0800 Subject: [PATCH 2/2] tools: merge C3 changes into master --- docs/en/api-guides/tools/idf-tools-notes.inc | 5 + .../api-guides/tools/idf-tools-notes.inc | 5 + tools/ci/check_public_headers_exceptions.txt | 1 + .../python_packages/ttfw_idf/CIScanTests.py | 3 +- .../python_packages/ttfw_idf/IDFAssignTest.py | 13 +- tools/ci/python_packages/ttfw_idf/IDFDUT.py | 23 ++- tools/ci/python_packages/ttfw_idf/__init__.py | 3 +- tools/cmake/dfu.cmake | 2 + tools/find_build_apps/common.py | 1 + tools/idf_monitor.py | 1 + tools/idf_py_actions/constants.py | 2 +- tools/ldgen/generation.py | 5 +- tools/test_idf_monitor/Makefile | 30 ++++ tools/test_idf_monitor/README.md | 7 +- tools/test_idf_monitor/dummy.c | 13 ++ tools/test_idf_monitor/dummy.elf | Bin 564 -> 0 bytes tools/test_idf_monitor/dummy_riscv.elf | Bin 0 -> 35148 bytes tools/test_idf_monitor/dummy_xtensa.elf | Bin 0 -> 4260 bytes tools/test_idf_monitor/idf_monitor_wrapper.py | 11 +- .../test_idf_monitor/run_test_idf_monitor.py | 35 ++-- tools/test_idf_monitor/tests/core1_out.txt | 24 +-- tools/test_idf_monitor/tests/riscv_panic1.txt | 151 ++++++++++++++++++ .../tests/riscv_panic1_out.txt | 79 +++++++++ tools/tools.json | 4 +- tools/unit-test-app/CMakeLists.txt | 2 +- tools/unit-test-app/configs/cxx_exceptions | 2 +- tools/unit-test-app/configs/cxx_exceptions_c3 | 4 + tools/unit-test-app/configs/cxx_rtti_c3 | 5 + tools/unit-test-app/configs/default_2_c3 | 3 + tools/unit-test-app/configs/default_c3 | 3 + .../configs/freertos_compliance_c3 | 4 + .../unit-test-app/configs/freertos_options_c3 | 23 +++ tools/unit-test-app/configs/release_c3 | 5 + tools/unit-test-app/configs/rom_options_c3 | 3 + .../unit-test-app/tools/ConfigDependency.yml | 1 + 35 files changed, 426 insertions(+), 47 deletions(-) create mode 100644 tools/test_idf_monitor/Makefile create mode 100644 tools/test_idf_monitor/dummy.c delete mode 100644 tools/test_idf_monitor/dummy.elf create mode 100644 tools/test_idf_monitor/dummy_riscv.elf create mode 100644 tools/test_idf_monitor/dummy_xtensa.elf create mode 100644 tools/test_idf_monitor/tests/riscv_panic1.txt create mode 100644 tools/test_idf_monitor/tests/riscv_panic1_out.txt create mode 100644 tools/unit-test-app/configs/cxx_exceptions_c3 create mode 100644 tools/unit-test-app/configs/cxx_rtti_c3 create mode 100644 tools/unit-test-app/configs/default_2_c3 create mode 100644 tools/unit-test-app/configs/default_c3 create mode 100644 tools/unit-test-app/configs/freertos_compliance_c3 create mode 100644 tools/unit-test-app/configs/freertos_options_c3 create mode 100644 tools/unit-test-app/configs/release_c3 create mode 100644 tools/unit-test-app/configs/rom_options_c3 diff --git a/docs/en/api-guides/tools/idf-tools-notes.inc b/docs/en/api-guides/tools/idf-tools-notes.inc index 9b076e96a3..33be40347a 100644 --- a/docs/en/api-guides/tools/idf-tools-notes.inc +++ b/docs/en/api-guides/tools/idf-tools-notes.inc @@ -15,6 +15,11 @@ .. tool-xtensa-esp32s3-elf-notes +--- + +.. tool-riscv32-esp-elf-notes + + --- .. tool-esp32ulp-elf-notes diff --git a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc index 37eda3df41..0e6f0fe70a 100644 --- a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc +++ b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc @@ -17,6 +17,11 @@ .. tool-xtensa-esp32s3-elf-notes +--- + +.. tool-riscv32-esp-elf-notes + + --- .. tool-esp32ulp-elf-notes diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index 70c084c922..68a736e87b 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -112,6 +112,7 @@ components/soc/src/esp32/rtc_clk_common.h components/esp_hw_support/port/esp32/regi2c_ctrl.h components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/secure_boot.h +components/esp_rom/include/esp32c3/rom/spi_flash.h components/esp_rom/include/esp32s2/rom/spi_flash.h components/esp_rom/include/esp32s2/rom/cache.h components/esp_rom/include/esp32s2/rom/secure_boot.h diff --git a/tools/ci/python_packages/ttfw_idf/CIScanTests.py b/tools/ci/python_packages/ttfw_idf/CIScanTests.py index 20273378ee..959c28c1ac 100644 --- a/tools/ci/python_packages/ttfw_idf/CIScanTests.py +++ b/tools/ci/python_packages/ttfw_idf/CIScanTests.py @@ -16,7 +16,8 @@ TEST_LABELS = { 'test_apps': 'BOT_LABEL_CUSTOM_TEST', 'component_ut': ['BOT_LABEL_UNIT_TEST', 'BOT_LABEL_UNIT_TEST_32', - 'BOT_LABEL_UNIT_TEST_S2'], + 'BOT_LABEL_UNIT_TEST_S2', + 'BOT_LABEL_UNIT_TEST_C3'], } BUILD_ALL_LABELS = [ diff --git a/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py b/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py index 04f33ae0cd..18714defde 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py +++ b/tools/ci/python_packages/ttfw_idf/IDFAssignTest.py @@ -80,17 +80,20 @@ class ExampleGroup(IDFCaseGroup): SORT_KEYS = CI_JOB_MATCH_KEYS = ['env_tag', 'target'] LOCAL_BUILD_DIR = 'build_examples' - BUILD_JOB_NAMES = ['build_examples_cmake_{}'.format(target) for target in SUPPORTED_TARGETS] + EXAMPLE_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS + BUILD_JOB_NAMES = ['build_examples_cmake_{}'.format(target) for target in EXAMPLE_TARGETS] class TestAppsGroup(ExampleGroup): LOCAL_BUILD_DIR = 'build_test_apps' - BUILD_JOB_NAMES = ['build_test_apps_{}'.format(target) for target in SUPPORTED_TARGETS] + TEST_APP_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS + BUILD_JOB_NAMES = ['build_test_apps_{}'.format(target) for target in TEST_APP_TARGETS] class ComponentUTGroup(TestAppsGroup): LOCAL_BUILD_DIR = 'build_component_ut' - BUILD_JOB_NAMES = ['build_component_ut_{}'.format(target) for target in SUPPORTED_TARGETS] + UNIT_TEST_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS + BUILD_JOB_NAMES = ['build_component_ut_{}'.format(target) for target in UNIT_TEST_TARGETS] class UnitTestGroup(IDFCaseGroup): @@ -98,7 +101,8 @@ class UnitTestGroup(IDFCaseGroup): CI_JOB_MATCH_KEYS = ['test environment'] LOCAL_BUILD_DIR = 'tools/unit-test-app/builds' - BUILD_JOB_NAMES = ['build_esp_idf_tests_cmake_{}'.format(target) for target in SUPPORTED_TARGETS] + UNIT_TEST_TARGETS = SUPPORTED_TARGETS + PREVIEW_TARGETS + BUILD_JOB_NAMES = ['build_esp_idf_tests_cmake_{}'.format(target) for target in UNIT_TEST_TARGETS] MAX_CASE = 50 ATTR_CONVERT_TABLE = { @@ -107,6 +111,7 @@ class UnitTestGroup(IDFCaseGroup): DUT_CLS_NAME = { 'esp32': 'ESP32DUT', 'esp32s2': 'ESP32S2DUT', + 'esp32c3': 'ESP32C3DUT', 'esp8266': 'ESP8266DUT', } diff --git a/tools/ci/python_packages/ttfw_idf/IDFDUT.py b/tools/ci/python_packages/ttfw_idf/IDFDUT.py index aa62584d32..1a942f8dcc 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFDUT.py +++ b/tools/ci/python_packages/ttfw_idf/IDFDUT.py @@ -463,6 +463,9 @@ class ESP32DUT(IDFDUT): def _get_rom(cls): return esptool.ESP32ROM + def erase_partition(self, esp, partition): + raise NotImplementedError() + class ESP32S2DUT(IDFDUT): TARGET = "esp32s2" @@ -472,6 +475,21 @@ class ESP32S2DUT(IDFDUT): def _get_rom(cls): return esptool.ESP32S2ROM + def erase_partition(self, esp, partition): + raise NotImplementedError() + + +class ESP32C3DUT(IDFDUT): + TARGET = "esp32c3" + TOOLCHAIN_PREFIX = "riscv32-esp-elf-" + + @classmethod + def _get_rom(cls): + return esptool.ESP32C3ROM + + def erase_partition(self, esp, partition): + raise NotImplementedError() + class ESP8266DUT(IDFDUT): TARGET = "esp8266" @@ -481,9 +499,12 @@ class ESP8266DUT(IDFDUT): def _get_rom(cls): return esptool.ESP8266ROM + def erase_partition(self, esp, partition): + raise NotImplementedError() + def get_target_by_rom_class(cls): - for c in [ESP32DUT, ESP32S2DUT, ESP8266DUT, IDFQEMUDUT]: + for c in [ESP32DUT, ESP32S2DUT, ESP32C3DUT, ESP8266DUT, IDFQEMUDUT]: if c._get_rom() == cls: return c.TARGET return None diff --git a/tools/ci/python_packages/ttfw_idf/__init__.py b/tools/ci/python_packages/ttfw_idf/__init__.py index 03673807b6..9366dcdb07 100644 --- a/tools/ci/python_packages/ttfw_idf/__init__.py +++ b/tools/ci/python_packages/ttfw_idf/__init__.py @@ -23,13 +23,14 @@ import junit_xml from tiny_test_fw import TinyFW, Utility from .DebugUtils import OCDBackend, GDBBackend, CustomProcess # noqa: export DebugUtils for users from .IDFApp import IDFApp, Example, LoadableElfTestApp, UT, TestApp, ComponentUTApp # noqa: export all Apps for users -from .IDFDUT import IDFDUT, ESP32DUT, ESP32S2DUT, ESP8266DUT, ESP32QEMUDUT # noqa: export DUTs for users +from .IDFDUT import IDFDUT, ESP32DUT, ESP32S2DUT, ESP32C3DUT, ESP8266DUT, ESP32QEMUDUT # noqa: export DUTs for users from .unity_test_parser import TestResults, TestFormat # pass TARGET_DUT_CLS_DICT to Env.py to avoid circular dependency issue. TARGET_DUT_CLS_DICT = { 'ESP32': ESP32DUT, 'ESP32S2': ESP32S2DUT, + 'ESP32C3': ESP32C3DUT, } diff --git a/tools/cmake/dfu.cmake b/tools/cmake/dfu.cmake index ce36656d72..45f7470e77 100644 --- a/tools/cmake/dfu.cmake +++ b/tools/cmake/dfu.cmake @@ -9,6 +9,8 @@ function(__add_dfu_targets) set(dfu_pid "2") elseif("${target}" STREQUAL "esp32s3") set(dfu_pid "4") + elseif("${target}" STREQUAL "esp32c3") + return() elseif("${target}" STREQUAL "linux") return() else() diff --git a/tools/find_build_apps/common.py b/tools/find_build_apps/common.py index 12fd9f000d..1b3039ea56 100644 --- a/tools/find_build_apps/common.py +++ b/tools/find_build_apps/common.py @@ -295,6 +295,7 @@ class BuildSystem: 'ESP32': 'esp32', 'ESP32-S2': 'esp32s2', 'ESP32-S3': 'esp32s3', + 'ESP32-C3': 'esp32c3', 'Linux': 'linux', } diff --git a/tools/idf_monitor.py b/tools/idf_monitor.py index e2940e9f41..c4290e83db 100755 --- a/tools/idf_monitor.py +++ b/tools/idf_monitor.py @@ -391,6 +391,7 @@ class SerialReader(StoppableThread): self.serial.baudrate = self.baud self.serial.rts = True # Force an RTS reset on open self.serial.open() + time.sleep(0.005) # Add a delay to meet the requirements of minimal EN low time (2ms for ESP32-C3) self.serial.rts = False self.serial.dtr = self.serial.dtr # usbser.sys workaround try: diff --git a/tools/idf_py_actions/constants.py b/tools/idf_py_actions/constants.py index d4a96eaace..d2c11999fe 100644 --- a/tools/idf_py_actions/constants.py +++ b/tools/idf_py_actions/constants.py @@ -38,4 +38,4 @@ GENERATORS = collections.OrderedDict([ SUPPORTED_TARGETS = ["esp32", "esp32s2"] -PREVIEW_TARGETS = ["esp32s3", "linux"] +PREVIEW_TARGETS = ["esp32s3", "esp32c3", "linux"] diff --git a/tools/ldgen/generation.py b/tools/ldgen/generation.py index f1f22e0e31..addb6bdf33 100644 --- a/tools/ldgen/generation.py +++ b/tools/ldgen/generation.py @@ -597,7 +597,8 @@ class SectionsInfo(dict): def _get_infos_from_file(self, info): # Object file line: '{object}: file format elf32-xtensa-le' - object = Fragment.ENTITY.setResultsName("object") + Literal(":").suppress() + Literal("file format elf32-xtensa-le").suppress() + obj = Fragment.ENTITY.setResultsName("object") + Literal(":").suppress() + \ + (Literal("file format elf32-") + (Literal("xtensa-le") | Literal("littleriscv"))).suppress() # Sections table header = Suppress(Literal("Sections:") + Literal("Idx") + Literal("Name") + Literal("Size") + Literal("VMA") + @@ -607,7 +608,7 @@ class SectionsInfo(dict): Optional(Literal(",")))) # Content is object file line + sections table - content = Group(object + header + Group(ZeroOrMore(entry)).setResultsName("sections")) + content = Group(obj + header + Group(ZeroOrMore(entry)).setResultsName("sections")) parser = Group(ZeroOrMore(content)).setResultsName("contents") diff --git a/tools/test_idf_monitor/Makefile b/tools/test_idf_monitor/Makefile new file mode 100644 index 0000000000..14434123c4 --- /dev/null +++ b/tools/test_idf_monitor/Makefile @@ -0,0 +1,30 @@ +# The purpose of this Makefile is to build dummy ELF files required to run idf_monitor tests. + +# Make sure the toolchains are in the PATH: +PREFIX_XTENSA ?= xtensa-esp32-elf- +PREFIX_RISCV ?= riscv32-esp-elf- + +PROG_XTENSA := dummy_xtensa.elf +PROG_RISCV := dummy_riscv.elf + +# This actually depends on the value of portUSING_MPU_WRAPPERS. +# I.e. ESP32-S2 would also have TASK_NAME_OFFSET=52 since portUSING_MPU_WRAPPERS is 0. +CPPFLAGS_XTENSA := -DTASK_NAME_OFFSET=56 +CPPFLAGS_RISCV := -DTASK_NAME_OFFSET=52 + +all: $(PROG_XTENSA) $(PROG_RISCV) + +$(PROG_XTENSA): dummy.c + $(PREFIX_XTENSA)gcc $(CPPFLAGS_XTENSA) --specs=nosys.specs -o $@ -g $^ + chmod -x $@ + +# ^ chmod is there so that we don't have to add ELF files to executables list + +$(PROG_RISCV): dummy.c + $(PREFIX_RISCV)gcc $(CPPFLAGS_RISCV) --specs=nosys.specs -o $@ -g $^ + chmod -x $@ + +clean: + rm -f $(PROG_XTENSA) $(PROG_RISCV) + +.PHONY: clean all diff --git a/tools/test_idf_monitor/README.md b/tools/test_idf_monitor/README.md index 16b97fb970..0464014afc 100644 --- a/tools/test_idf_monitor/README.md +++ b/tools/test_idf_monitor/README.md @@ -5,9 +5,4 @@ Use `run_test_idf_monitor.py` in order to run the test. New tests can be added into `test_list` of `run_test_idf_monitor.py` and placing the corresponding files into the `tests` directory. -Note: The `idf_monitor` is tested by a dummy ELF file which was generated by running the following commands:: - - dd if=/dev/zero of=tmp.bin bs=1 count=4 - xtensa-esp32-elf-objcopy -I binary -O elf32-xtensa-le -B xtensa tmp.bin tmp.o - xtensa-esp32-elf-ld --defsym _start=0x40000000 tmp.o -o dummy.elf - chmod -x dummy.elf +Note: The `idf_monitor` is tested with dummy ELF files. Run `make` to build the ELF files for supported architectures. diff --git a/tools/test_idf_monitor/dummy.c b/tools/test_idf_monitor/dummy.c new file mode 100644 index 0000000000..874a577d74 --- /dev/null +++ b/tools/test_idf_monitor/dummy.c @@ -0,0 +1,13 @@ +/* Produces a minimal ELF file for espcoredump tests */ + +typedef struct { + char stuff[TASK_NAME_OFFSET]; + char pcTaskName[16]; +} TCB_t; + +TCB_t foo; + +int main(void) +{ + return 0; +} diff --git a/tools/test_idf_monitor/dummy.elf b/tools/test_idf_monitor/dummy.elf deleted file mode 100644 index 70a22cc5b1561760276a2bb49192d0c9303b385d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 564 zcmb<-^>JflWMqH=CWbf$D9^!!fq@|h$}wS3U|?j>U|?lng2^*5FgSp51Oo#D2(vLT zAmsFlD|1T{lNj`hONt4ErXm&WvG~-y6b#iMF^KDlAf=(<$PD#g2m=EHEF3`Ep;5vh$N&l_kO%~W x;y@9?1d}jzAesp*0wHP`7#Jo%%>;>q%obo^VBkbEkB5KcWBt diff --git a/tools/test_idf_monitor/dummy_riscv.elf b/tools/test_idf_monitor/dummy_riscv.elf new file mode 100644 index 0000000000000000000000000000000000000000..5440c0b9f5625112597d649b6876212b2a5d5420 GIT binary patch literal 35148 zcmb<-^>JflWMqH=CWg-pAYKUrBZCP80|QGN1DJ2ZpuoVypur%@AOhw?)PqzqGOS@^ z0Ap5=pa4WYSWJwOVT~9gg9rly!yE<%1~#btbVUY+$&HRrgj*XMgxeT9joFqtOlD)R24Oak`~m)ah694;qKpjN#Tgld*;}(G zx3^~}_dI7XXJ%j!W@ctcW@Ba$W^K(*XJBSXZ(snc1F4_f+MYd`y)}Dt>sN=#S5+M* zvnw!cKKhj@xrY^}UgqNm8W5u%ro z@&Dx3)*O%-AUj~@fb@g(=6|^V*-=pG7z0P6yIrf1iz8!G!(>)ghRJLU;BXOUWnjo> za8Lxf6BLecx3aK;!qfy5R?JJ;bDGs#nUY)B8J;(=GYGS?FuZ3t;04kHk_YKA7hz-& zZgh)U4tN_m?osm;aN+RTwt6e_?1| z4lzIfL;PP%v)QwSSy&KeD=0F8{3{GHpM`-zxRX6Qc|r>d$UP9ZfYiHy)uX7H)xw1A z4rWb8xLYPqS7F%9{uAtu$t@yazvh3q{|meL{NKXN9~gw$Ss9Y+4l_+I|IUy+ft@RP z5-Z2#GPeK1W#1S!w>@J}R@lysS8C(^?reKfTH@c^WGth|d3T|J&qg z>Tr7|H!(0gZ(#d1xq%6k7XKTwe|Iou`^NCN;_x?6nh|DX{HLrnkzu(9D zRtDy!N3xZ58X1%|6d9FO92u3B0vVO{1Q~=oSs5mCu`vjDu`#@7Xix{mLGyC<9OfnM zEXe{aOu{Y4S+&P8W6&R9dykuZjcNN&2{+&Tt>8n7qx(nDI;dXI` z$B(7cq5p?R67fN}YChGYqL2H{q2XdaCJBizagWzYW&ihFEWm{kCr{$VssO+KjZ zU|?V-%S3`Lp6$z=?Tk_-$CtVLzUMwvzh2JyKdBH5_G0BQ|`3u%rj)YFDr@1~W1+@R%|(FmNz3Ful|w2a@GtUCn@S2jd(r7S_zX5(b8a zoFFf+138?rnVErs$Bc=AVGA1r11x1&F)}bPL9Azn=waeuFR2{S+eu1M40Z1_ow5zATV$ z*0C}$Fqc5serya3%#+1+K85kJY^+1Z3^EiUoCCm&A%qxUJ;tU+23=9lc z85kHiL5^T%;NoCj#QBqffq{D>$jBw^AY&M~7l1e`Sr>ym%fKoH;;mu^Y2#sG{m;t4 zz#=AD2y%xB3j+hIlB7H%0|PIMDkB2}-%M5p23B2W1_l;oX<LCUO{#a%P1{D??4oxNo25uH61_l;8PLO5>?!6#8 z?7MwZ)em6D-h8~tEjsqYw!QmJ!1Y$FA2ZM}>VFP)Rg3v@d09Z=#m~daz`(&$ z#lg+Yz`(5ta!|D(h|R#=4RUx5#1aNx7Em(czstfn~lBSg}BS z5d+HtNX!bvmou;|1hYA~_k&Da#0e?}dAQX?B|F))aTZ3OA-fS4&EmIYGT z1>wnvMSytSjADy97#I}9<8uobSb7fsE8$iOZ(;PwTD)+t$#cU8E(K@L14 z+s($npuxQY6vpRy*RwG&=x{&bV_;ypzcA}xvgd~2c{T#X0~4g45(#Akm7t)o2J32NV_-ni1?EC^#eh|&voSD8bTcq8fPw)@ zB}hmTs&XPo4Tud29fTSNUY4zF43L@tvvt#V82kFo?YZMU^%rVY7&R0tJB%B%yII@UnoCA1@2YV9|+; zpsK)yk)s1-NH-|pTp5Kx90svtAf6k9$0qg*#B*m9N@ieS;1M$e@w^ySDi|0T1Q<9# zf-~5m4rO8x-2o~zSYjDD?t_d~1KFRz2&rSlfRFJh?fs>go+ps$Vmkdl^SASLFG;%gl8c38LFp6LfMT38 zgOhxO&BTXiNoq>T}fZvo8)FuQq+hkUOnr(l;O*olEknCR`Q0q*l z63hk<$H=sT*)m}92oU=}SdFYVI|Bn-A{(rg#W?3UsM*)R&cMKE3Lez~>5zZI$jAVa z*am9mF-9>}FeoraGa4``f(Az~!vz@_lrq>E7(keVhfT?goq+*_*@f5`?t-c-25RisDE}tJOyMpWCRb|TVtKT zz`y{)Yz*uy(?COsoPR(*736OPjjYY&U|?Vr0<*bRf!I=vApe0zJs9V3gXZ@bWw^2# z7#O@jy_-x1Mp-Z~7S!5hkOenjl|elXhzGZFGB9XyGBA{}g9ipdLy^o72QouO7nvb$ zV*!mWGNv+$tAGYfA)|}TkkLhE$mk+76L@rynFTz$$P5`>WQKShJi5rF$Cm^e)msM& z!x9J^G`h$%SzH!8y2!MYc`s;05j48Uw4BEh#0HHnGOZ8>i8FBcGB7Zl1%(0F5e!@$ zOp7=_!bTUFmav12fs8IPtz?}Ij!W?9BGW2nkT&S(BD0ueCdeJ2(M1*|NpWz`Miyms zky%-q8$PK}Q$$K%T*-i_CVMAkC1`MP_?22Qs?I>;UFK zMi-eK!5qlwBC`{i0~uXpb_R1Gql?TgU=Cz-k=Yf@fs8IPyMZ|hu+c?ke~vWJNFZo* zkvV`1#DwyeFF)tT-02y86gpV#V zS2A*d1i_<=%(aYQ<&e=u<|amNWBBMIa}%QohzA*6WNu=V1MwiEi_9&I9H4N6j4m>_ zF>-=By^zsG<_?INkkLivE(i}Yy2#wkC^j2Dy2#wiD6|khy2#wm$h8SRy2v~cq7Tw= zWu5}zK}Hvur$X$5j4m=yXB6H6A6;ag!6>i~KDx*}6QU9_y2w0-k^4M+bdh-hqcA8T zKt>mt7cvTg;u$i!$h?G6;0t_ok$EX3Tp**1%*zoDBX=*D4UOD=;P`}$E;8>2bD)uX06B6Gg7rWn_Xs3%!J~`JC%8Zf zA2Pbgd`dQwje!9&y2yM+wi!OU$b6o6Iec`H`2y!b_~;_@Ww1Sv(M9GfU^hcX7n!eu zErpCOGT#t94j)})zA1PeKDx+!2W$XjbdmW!SPx`$k@*1^XeJ6Wy2$*TM+rW<$o!HI zRE9!E7nxsy%YhUIiGBtK22gsE1f^3+kiR6sTu_PwgTF~es zLKm0|)fEC(84nscY-V6!00je*`5+-lsLD=|8W0;4ItVokyew-$ql=&{4DvR(AYg*j z4A0pZ7{Gk!=pwTUqZDWo3^KaNtii~k3mU-#jV>~4F$#h>kkLhEZAij~j4m?kKoS~g zbP<&Ncv(OOLq->wT^Kn)tqw6z!}L3ohSMP_$Kp=eM^0Uljs_F_~i zfQ&AJ1Sfz-7eOT$Y;=)1mXYH+$Zep}Mdk!XNF4(nU1Uy#xeYYB$eaX`gN!aRCo_tG zw1Gw!LA4TObdfook)sVZy2zXb$r+H*MdoZqa9l%17nyS)Jjm!Gb1sAj8C_(~gBSuC zU1ZLOI07=d$XozX2^n2vE`;zPql?T%5FTW7k+~ScgN!aRmq2(P3>=^oGYvGl2nq%G z=psmjmjx6$QlK&j9P13cEX%<|hnC>cMNnla1u8yZ>EtR{@(7r`3maWzKF_EGD%ZiI zi_90G9MI?@^F=5JG`h%a#w-C!r!pLz3=FKy2gDc|7`}pA4LzW-M@R$7n+wtcgiVz9 za12Nba3>c71EVmw)yH`r#1?_D)j(`f2>UUJEe2+DS%TPdj4)TjT80YXw%}w?%FJY7 zR0Q+(fLn%;iFG4T&BJ({3*5+K08Q?H;bLIO<%UhHhk_R*xPeuHXQ|71AOoNvrJ!{H zTX=|QM}lUlK`nM>vf7b&W~o7g!fYhWQiC0VIZF*P2GWjXrq3)j$U;avlEs`G#DTOU zS%z?KfsWku!@)xWfiEow~`D{pIlBJ460M?jfsTKsWA&p6v8aA*^pb;Df1_nrDl4TwTXlfHWRSi}Q zYD}^$UKE|FB+F8;9!PtGWw{V&;fV}`h#0&v37V<~34$Aw zEVYba<&efCOA{kx^#OdU8nhMx(wJmvVw3~%AdN|u7Df(`Ga-#hmNrICP+bjaOtN%9 z%!D*1S-K!RNMn+vn^9~9yfF!ys$K_gOtSPda_xsVCRrvz^g$YvEK?vnNMn*^D#SiW zW0GY$qwrC9W0GYCqrho+W0GYiL?xs#$uftL`wqM@NocB?ksW!e8sv9KW0GYVqxcJW zW0GY##0F4fvJc*vWZA`G25n5T>=r^q?jCSxgBz19d%vEMvB~nU_H>tJpzeb zaAT4MZK^sA-k4-LBRc`!m}EK63tA)upQ=6wZ%ndW76jP?X-u+Q0lOK}m}I#MwiMEs zWVs=D1>TrsxhePr-k4;$12zECm}I#R)&prwvJgF04N6kbscKMqk_4qw$W%3$3zBBw zWr;#+OoG_FETFIkPgQq;8j}cJU@lY_X!4$yB?r_{1kFo>f&s~VkdP!)(HrcP|FX@hc+fbQ`MhQrmC$#4K`3?l0}PA5X6BrCRwy0 z2^-RwWYK|SKu}{6l>B&EKn6n^lPoTb9K9ezK#fTjS4JTahXFoS4dOu>lPvhAs^@|l zlb~V@)|doMRX+h43u;WVU`$nmf`LU0)R@Gass?ETH6~G~swcx5lPp<~oB?S}vXC@Y z4Kf7Mm}JR^1Q4V#$wK*5H7Lb^R?C2+3*MLniSV+3LPrWz27zOpftO_qxTOec!0@tw zr>a542P~aD0!v;5ldoWnNtW}BN}zHb+?Zs!0Of!hlc1?;uned%$zsMV0ZON^scKOA zhE7$3VuziTEf_Rri8)m*Q^^Y&#*_jrXOjm_G&8y|f+7jlqGFt*!NtI!AjZSMz~~|c zlF?;kU{C~2W4m&Krm<5%+{B`E21YmVvaZ=6ehLGlJD7Kgk%2);5Tw~t3RJUkGBGeH z7cek-$$(b%*fTLOsA#Y-g4dhA<78lvVFxJ<)qV_G+^QzEfkAZv z3nPOA7XyRZ1{OvJA1($4IW7hUb;c-WE)GTpRT)-@G6oG}9tH*wW;N#32<2g50AW@e zUJYp;1_lsjwc^!a-~qKm85r0K*co)d4a<7a@Fb+&{TkY^ge@S|6a+OaM`zYYmp_g! ze;i%@IJ*3iWpw!?0|RJc5xfWu(xwD+LA5QYUj~|9gAP!F7PIlPj4po!FNP$dO$l1y z2kyrsw<$sE7{#!+DM3Mwt4#^ghS{bZUH(Y!@<*8>P;*g`5wsmb7Tk0cWCS%GS(*2U zF*3-3X0;jJ7-6j@#yNsq3=Hz1VQNM<@FtE}CI$wD6b42&WzdS@DNGCuiUkae9^lsC zX(k2+r4*3)o+2Q9FF|cZaNE&K8Ps-UOjgNbVDuIM#W!P;VkQHl4|oAHFEg}3>dOUc zkUB9lFsNpMj0s@^?SNwV$H~B;n3k+-7{%1iz`&qcz{wTG3FK^Zjs$jbt1pK62JkRZ%z%&QG*LxM1?4KIT&XbmRABW?x;7D#*X6)$9* z7Pg^iwkQJw6KIN;NlDTWG@Qv|4jS48Z6IM}jOGXe%>bVRxiJRJhVSWNUk?(D=Le}~ zWi}9JWMJRH$H2gt02OfoiGbrE5h?=OX2zbu&%nT#1QoFWshI)Nl?)Xz0f|fknVbR@ z(E*8sfpn!pMI1mP_8^fosE7?nqz+_GI#fhMoRNV86b4K-ydt29xdQ36YFMes2&Fq!jsF)}cKFhsIXA1uiY*-XU4&CkHVWC~Wpm=8C) zLlvxu0~7~L#=M|u28ixvsGaH{ZHBxH;X3Ldc5=K1*{RRF3ocQq2{Gy_NJ5wQGF+lW z9wN~SGD@5G4O}8$6U1g<1~2yIy~@kLz@*8`$OD>K2750{0W8n=iIIT;6z`y|a*T68 zdvEyvgZ5fQF$e@QGB8YFV`KoW;b5F2n8e7y0P3gr9-I zPk?~|w&QHG7_|oaVH>nSt4tU<8DSPM&S5P|W?Y7jVFvA7H>&BwsN3}teF_H{w5WVPh>6lP#xMRft2 zIEruBk$nT&@dWh?C(JKgsJ`b$RuA$$4?hDpHvO4~Fer95F)|7=PIZzr6lP#h>S|(SV3L^VB*DO-3`ztx zl6icvgaF!LIU3;u5#gv&+Ri8m$&b^VBtda1#|lX`;3NWyQ+Y_78iGpz1*9m2Mm9L6 zsS&$i8yOf_8KF6pO%b$m3zqFTAUTB-GX-;@dI;_t1_o|q#UQ`%AeT-c0p#KkTofWo z8CZb>+PeiUVZga=w7?;)z;PD_RRYKX4T>S;z{Xy>4^VO-uErcqCg5@$oFN8hy##N; zfU>zFdPSv#UNR`7mkcW0jG%N1DiT#Yn;01c89@b|8ggN%j#LjS%HIufq@xTfwI8c8qjt=E3|P5 zRtU<($gO(JK;%FTM3DPI2mQeP&A@pRR#=$Do0;e)78K;9>ZT+X zm1pJ|8tH=%j4?LSO)W0aP0dNuFD^>f&r2=O$xPDE$xKSm$uBO3s9|78E-Eq53x*t5 z!pa0XyM$SSk(rT`g@KWo1x!NNm?RfemIJPm2`U28i=m#Ag@J*Q(GBchIc)xANGZ+D zt<(c;b_TWF7+9G=N24%vF|zV7Gjg&qFtUQ&#l*nK3EE=7$j8LMz|8Oz6jJmFIYa;^ z>lc@#P%(3O3=E8{Tx`q? zAO@!hC~akfQ^fnx6oI3_7|;|!h4fIGmswnr0!b&BX#=zqi`kTsm6e$dlq6Ug*_f-q z43Gc|xb&z3mro3w91IX;AW>#EW^l2^DgsSQtRR{Pq=F4n46?F;L_o=n87cxPfVMM& z3Lu_=Np88B#mNM-ED1FP$;A&tT4r7*W(J4kQ_$`&W+`|+h2&OdCUA5xvN6|y88VRi zg_V)H1{5!>$b10?Mlc@~Q?O8HU}9ke#RMqU7@66?dRQ5lSeV(Et2sp&7+EDD9B_%i zDh}c>GaytkgX5hOw3dWXh%Qk_a+ngTPDstb4Dh0tk%0kT^fDoeUM2e9DxKakCvd3`Je<1;)4nnSb~OEU#!fav<*q1Y|QN7G%Ev2 z>hMBG0;#e?R?W%?Exn)_p_~(>QVNvzVfw)`5VKjOK@!aMU<)AP;AR>~l#Q7KTrPt1 z4GDT7W#LP3h5~KSVWfX!EH^PZBQq}*(q3X<$W6^HPAx&SX+h@&GRuP6j#%5J%*>$R zfRfwRhji}xB1}*+%KF)w%1~P-|az;=c z3@)vhS;55!BXcz<$+0q{@|hXHH8n_-hk=m|lIvL6;pGjqoPw8-@TM0#teGYSQ_BU_ zEXG_5wh5*J(%3+htxTXs8>k&24%5jDvKJ(RY&r`k4+E$$1&MPogZ7^@vhu@pFfxmR z?O+t*+FK3S|mI$wd^4KKq9ct2`dYzYz2wH{mH?`%m%WL6%=fsDuEZK zn+4=gkO*8Y3#>*EMp6ULldM7*B9br>c90DqJH=okGLRyRRgSqHY&G1SNGc%BB{68T z39JGX9!fAXz#<@1;eLaMt^iC8xIqo_0X#&Qp>>oHa~(JoVde`#?Sb*ZIzgie;4%mv zgOC~~4|KjK!-LU6XE1i|;^UJOb8@It@<19~pw&Xm$1qA8aJL_l!%;{USSeHnW-v2z zK}(@BaEe3YGc#~%Ffg*RGxI}bA!QXCvk-*O##{_$!1Ew0G^N7IC5YXuoJeW@7$on2 z%QQ$q2q~5rp~Vz4b1kO<$Wk`uy^sc&AR9Bp**wq=5IaZ!l)Ly~=CVWEg`n&NE*U^A z7;ra=8B*@TUC0Gh3DT~{TnTo*1_Kid6EizFw~K(;;4ToTJc1O`qM)J*0vH$=K!Z`B!xvrn1bjM}8X3{mfi{_g4)+8Nlz@)O zap4p2=wOQIWNu^(;5z7X!sVn3AA<`whW#203=A6>7#KkPQP3Ib5PdP7%#&Ce87rVV zFJaef0iA9DHRM41qFwkDTsoOOCbPzLFim2a!Zww?k&!6^ZpLMoD=t?dCSit~2Ll6x z1tS9ksF((wrS8IK;4+2HV>)NSG>#cuGr1cXJD5O@n#?+teHKpw*9nhYnU z;xkjy;&b!!GE4G{;B!C4C8cR;3>pqtJRpHiG3pOKiCl9S31Uz}N$$`D_an3rN=!4RLCn_85fnwMP3 z5TBA*lE@HWo?KLtpPLk4T#{Il3gQ-n`NdFyocz3W1u#*XSDcximztsgI*lqmCn*hL zaC}aFa$-(udFfo#i9&ISdbQ)W6ih|&{ta}(o1!JVF%%Mf3bnwSD2i%WA# z;OD9Cubyq-IJ4wH@%=H7vz+LDwD3D>t77PX?gj&pxjZC znFoq1H%}ke__W0AREGGx%>1NchT@F;q7ntvBmxO#1BfpZbK=3Flvtcxl9`(d;S{BU zyu=V6U!I)75bxvf>>VG%P@b7r0tyUp92hagmltJ%5+*1$Ri-8uF~o!01+YFoWJnj1 z#!~W2lRzmxzBmo+xcK6d6o`8f{QS}qZ~%gG9Yb+xQhq@RXp?4qd~r%k~2gdmwTJ}@00(tyURh>QejY=9K}k_6sFcYsC;_JjNT(B| z22>aogA{=Ln4F)I3S#FMl+dqK1-U{mnIS$NG%XgNSX7i)2`co8sOkjrgBDtBAUQ5I z50q3v6+M!Z=@4EZm*|7sp_fce+sF?ZNY;fUSZXh}K~CLZd-Nd%063+93S5+w5+4ta z4um*00|-Z>030148^KO0C`tvf(OiWp3Q0If%0L3N4?dJh9)0*64;3vYKMA3@jUhKN zCkNCvLTRNifNBed`1qn!P?ein0;;aEUsl_FUMX-uJ9_BDapv32vmZVlN z#6vM~G#AvugTnFZcQhYeKegPo+8jIRTW(d~fsJd8lS z4{D|{(h4{X&w$3sz!wHGGDLyK%7j59fDF+f3N-A+!tj|fYCc#IlmIWIWrzY%ps_GU zh6tzx185ivyki$t2sA>)$PnSez`y_+U}9v508t=a%nTKb^Fa*IU>TA@AVWZR95OOQ zfQH>bCs#8vM3gWvFn~tK&=i6k!Ng!NA4G#xGcrViD3GxrVGx}G_ERLtfEEZ7M0J2i zJS*$xgBYM|ff*ShLDT}6IEVqU5OgOW%$E!jU?ZYH)D$o?8AO2;LIMlK0*%BmGC&r+ zLN!{0)kcFT(3#te3`rmgq!^?vdOnB+(FQua8mftb0i>RhAqGT&9LLCz3Zg)YLE2)F zw57uJFu=6Mg0#&5Tbu%-VA^7lw1GkwtaA+m1H%EZ+Ncwt!A=PC3)HP1Z3)fwe%Rv;nL%0%SU9_z)?AK&n6i#mE2-FHo>EGNgkjkaIvjh?);#fkqn{ z89-Mdf^>kfH`vf<5Ct(m4Mc$ygS15>X-fmEXJ7y)JJ3Cfj0_PVbr3^A2>`4B#Hayp z#%(>p0N2jK0OElaKu2Lg$5gU17&bAe%m*=#fHrV57&bAg%m*<+hC*dwnn2f9f-b*f zWQdnxWMBZ_>&Orfic5cRSjEE>f-ZvusbFNtQek8OUsuV<0J;bftN;{Fpj$5)8KOXx z0@$g@xzC4zfdQ1XK|{qm7#J8}&H?MjMS#|RgXEaO>unjp_h3W#pv7Sf3>!d)k%Hrw z86?cG15kkxiya*0ho)3-BkH!a;W(Xl>20>^DK*U%WK7x-F2i*$}5@BS3 z%nQKo_+(;WWB}Rl0ICbb2W>Zm-T4aQgSPI2{13Vyl#zj*0kjMr7Ji^n?OfMI!-7*2>WLQ4>K2GBA4u<&POUYu_mQ1u{x!h}HbZy6Bj2^4-XIS>t! z|IL6%KcGuTL5mP!;RE7>?%PE0nHdZi5$O?>VqDPp;b{C^Mh1o*au8PuFns(Ex|I@i zNCHSikb#|HJ|hDI=pX|azm1WB0d#l;C}j&Wurh$IB7@C02r)1+oClc)P0s=htPJ;& z_<~HV46o7nKNuMpK*uY<%ok;1U;rKD0OOl5F@W<6#6C6#cP7Lf56HeqP!@#VrwihP zmb!xuaDeIWW@2D~%};>j*D^6Mz~(bR{L7$2)u8v@g81po3=E+B4yrpr{3lF^GYLR^ z(E5DXJQ0X5!py(`n_mI(O_&)NJV4hJfRB)7XK-Ld}%nS^m3v5A61yKC$1j!@C z#|aesSs6fuF0y;iGcz!Nj>Le4pDYVv&JJY$8)gOu*!&TQ54va)HXj7y%djBkdq8|8 z76t~;(HJoEELj*BK!<0*_@Mh7LC18!_@He!;HeJ1WQLSf_`rHeZhUf1eqL%ZLwtNn zK5Wo1r6j+oI6kqof+0CSw;(6ABsE3P)XcyVyCS6FocPqdlA=n6w4%h^)Ohgj8ixF& ztkmQZJySD76VPB4LM9&ELWT@nL9~H2=q1Azdc#L9KnlU#5y%K7n2FXq18wI>hELMQ z$GZhN`ntxu`nkl%gKW*r%Y+UwfW{86jG4uwx&|~-MPLvD))7Qi1`~yjz82(X=9Q!t zsUZ3o5HBD)1{hrn%uW<)zXH||3U+Y}ag29zb@%iG`!U4V8SY=?2`LJCqOjxui3rFT zGRBAzbPNeJzy=9ogkN!X`%ry^IkJF0YJt>?Lxdb?lpVAN2s9818IHxH4cz&|m`p+& z903O{iUm%=!SFyubu_f|h@v{F7(5GAR03TQ44FzqcNHi#qi91l7$gnd&BOq@K07`h zHKJ1?6N#{BC8jG1bt^awunq=+f)EjHM0bOWv2@!R^olEUOA?b9^gt6CU^)ZFDgn*4 z=%r@FgUbg7J&;$SX+{qz{pb~gy{K25R9wuU2PTs9b8}PkN*MIObJ2QAm2qq31OoM8M8Vjmb zh{Mw0t^orBs09kD??4?p3lImY9aP_fn4tC=sB8vRQ=oR<8qjI`APFdjsncd)0Jrr( z>Ok$W4OrBH)PmZ3pjIYG9jM&`Itdsg4mA$6yA6z;q3#2z1GS%bfDZqKDFU~pARN%e zNuYCWKH}Ep1*rrz`eEuo?M;w6P#+2;2f{EnfX){N`4_a71tbnqrwd|0F-Q)C zFfinT1{^>fB=;>vVuPe?QWzLg zKy4}z2PvF4LDj*+WkDJP!%d{_0mv>823`IHqM_OuD$5xdR)Hc1DgcuMb&p|ekd$&Y z0|ThL24aISOb$dNIfucent`DKbfymj1A{))eIRFmdPYdrFdS(B-B}GX34%f9fLMZ% TcmpxPSf`bN;To6)AzJflWMqH=CWbf$5bq>|1A_?z149ch0|Nsy1A_^J0s|9+27?HLFjyX<-hqLE z!GU27BLf(-f&>K^!17=*K?jC4f({HK3=9l43=9lxQ27`}2Zjnp2ZjlZ4h#nbL1r+Z z&^rVj7`6yHFdTu(tzd+xIRQ0~htYw-tdXJd-Twz142^F=r0fUBH~$x~Fff=oGAw-k zzwyog*sw`)LqF@T9UC?(_GC9cf-5p}WKewY z--wCf&tt;}{~hoBk7YJ+IpE-=$n9cy_kSBR1A}x&C-Z|2!LHU0jt3kJ9n9_)Z=U}6 zZ+QKGPw~QQ{~ND@oWdh)he8zaL5 z4hE$|e>#}bIKDu|YZ-Z%KuoY7kAn1oc?=By|Ns9F3PKnSV!Jy#TPbKH7v&chm*nT? z==!-Uq!t(G8W|WF6d7wOSm>GP88GlLFfb@EKq4lhBsH%%G2SyTEuSGY*frkKDcIj9 zG{iOD$1}t=$k8X*)_}{=$E04EWUaZ5nP zcrY?^dV-Q;Fe3v4BMTRZ&A=Q9;;?e1GcYh%Ft8*rFfc?iFfg!!2y+HD7WQADl*h=C z$;beaEr-eSGq6j5^s+IlGB7Z3q~+%`FmkYirI{ZHIxujifMmH?S2G~o!8nJDg*7v; zgn@xkkU@Y=kWq+{nNONel}{Ly_!$KmRr!RuK_Y^TLTm!!3=B-djNIH-+}7Nd+>F8u z49vU?%zO~8r?3S#0|N^qqo*)PhEuq3_`z9HLucVHR&@qMKMykdvyLl2}xpnP+IEUja@_ zx~atl#zwlSIcfUEMalYkspUDDN%}dNN$ENH#l=uX3=GLdB?fxI;KG4{l?jv%m}ME6 z89A95K$wA%(GBcIIc#oZNGZ+Dt<*~fr6>kgMg~?UP&#AgVr1oEX5?gLU}OcE#KgeJ z$;7|_F3mtm9+Xd*85nCAco@ND5J)#jA1FbwfZ~gXU4cHn*N1wZnzlh=2TbbbWF{p; z0~#qd(4)ZJFI2%XSiwlo*ig@qp){{JGd(XgMFEtYK~m0!=8*D2K{uTt#Mvpngh4;F zIJKx)KeH?`Pd`;3RIq?j38yFM`KWaY<=f8bd*HNMdoe zUt(@5LvCVb9z$|QVi7|Pg9EsnXkc()FkoO{*aGF3KKPSJfPAD zR)T<%_6}%i!lJ>z0Ae$PlMw^M9B8cp5(lwi;xM~GX2R?Tv0-iiu`eK*31WjvCXl^P z7#zT*A*fV)235nM!NBl>!GS>$YA+`vLJc?64Ink3S_`H|m(c;75kT(OV{~9pVPIeY znHj|BzyL~^Aa*#CIgv=_fND=ss9l9f>dRni7#JA#Kx+Xxj0`5nXt zH84Q_?L!jZfaHEqYXIg3WH%o~a_4bqynx&WN+%%oAoG_(!w@9C9Lao;JSGOE0FWp% zIBpmiVC@cOaGW!M+cFS&P+DRDw^1N`NZkhub!KoJBHA>};IIX$gkWX{b_fGXGBbeO z3gv+6HwI8xA@d=1F-(M+fg8pI)6C!s9?S$2%nYC~1v9|}GXo!(h7rsR{4ge%W@Zq8 z`WVb*U}5<9A5?zAQVt^nGlLW;w?bou5uAq+;ll`S88R?{atg=c>)Zq3_p16H6-?@{_VslS@=gO%2Q#(uxvuQ{%x^GR$sQKNqmoZb6Q| zuJJG)!l2}m{33`!U~OPWhxj_fRf3%i*H)Y#pOKiCl9S31pP83g!Vn*yR9qZiT#{H+ z0;x>m(=zii89*(z_|%ldl0=61)Vvf12EF3S+>*p32EF2vA_$!UW0j;AdMTnOi)8vFC{gpG(A4CC^0WRwU`0Q zMUhHMDoQPb$>e0_rNY=y3n3;HmlT0a*2~ER+n`raln+Yjpjal1rNMat(vJd_RV54z z48}+q0hE_OrhsZ0kT9s!1C?PbKuuqe1Qf&6X+zBem1dy44(hWZmqajiMo8*FHOLl5 z29y#Drp^*c9jGkagTr2XP;(nx&Oy@n0Y(Of45-^c6wEvqsCl540!SRB4%Ac!u|XK* zM-cX9U_dERpE5EqSb!8jF-Q%F2`Xb?Y!F|83DkQ9u^<@c_e`k05K#t(1SSTCn=lTN zTqzP8ByGvez_1R)fMS?k&1mYLGcz!}gQ@{hFm?TC>Ta+wFlc}jKrt*_=0MfK!Ua^_ zHN&A=c6(hL=VF$JM%04mIIh6mJwgYh8URS*vV Do3WMn literal 0 HcmV?d00001 diff --git a/tools/test_idf_monitor/idf_monitor_wrapper.py b/tools/test_idf_monitor/idf_monitor_wrapper.py index 20626a938e..b11bb1d5f3 100644 --- a/tools/test_idf_monitor/idf_monitor_wrapper.py +++ b/tools/test_idf_monitor/idf_monitor_wrapper.py @@ -27,9 +27,6 @@ except ImportError: import idf_monitor -ELF_FILE = 'dummy.elf' # ELF file used for starting the monitor - - def monitor_serial_reader_state(serial_reader, file_to_create): """ The purpose of this wrapper is to monitor the serial reader state of idf_monitor.py. file_to_create is created @@ -47,10 +44,16 @@ def main(): parser.add_argument('--port') parser.add_argument('--print_filter') parser.add_argument('--serial_alive_file') + parser.add_argument('--toolchain-prefix') + parser.add_argument('--decode-panic', default="disable") + parser.add_argument('--target', default=None) + parser.add_argument('--elf-file') args = parser.parse_args() serial_instance = serial.serial_for_url(args.port, 115200, do_not_open=True) - monitor = idf_monitor.Monitor(serial_instance, ELF_FILE, args.print_filter, 'make', toolchain_prefix='xtensa-esp32-elf-', eol='CR') + monitor = idf_monitor.Monitor(serial_instance, args.elf_file, args.print_filter, 'make', + toolchain_prefix=args.toolchain_prefix, eol='CR', + decode_panic=args.decode_panic, target=args.target) sys.stderr.write('Monitor instance has been created.\n') monitor_thread = threading.Thread(target=monitor_serial_reader_state, args=(monitor.serial_reader, args.serial_alive_file)) diff --git a/tools/test_idf_monitor/run_test_idf_monitor.py b/tools/test_idf_monitor/run_test_idf_monitor.py index 5a3ebb9627..d928353d11 100755 --- a/tools/test_idf_monitor/run_test_idf_monitor.py +++ b/tools/test_idf_monitor/run_test_idf_monitor.py @@ -29,16 +29,20 @@ import threading import errno import tempfile +XTENSA_ARGS = '--toolchain-prefix xtensa-esp32-elf-' +RISCV_ARGS = '--decode-panic backtrace --target esp32c3 --toolchain-prefix riscv32-esp-elf-' + test_list = ( - # Add new tests here. All files should be placed in IN_DIR. Columns are: - # Input file Filter string File with expected output Timeout - ('in1.txt', '', 'in1f1.txt', 60), - ('in1.txt', '*:V', 'in1f1.txt', 60), - ('in1.txt', 'hello_world', 'in1f2.txt', 60), - ('in1.txt', '*:N', 'in1f3.txt', 60), - ('in2.txt', 'boot mdf_device_handle:I mesh:E vfs:I', 'in2f1.txt', 420), - ('in2.txt', 'vfs', 'in2f2.txt', 420), - ('core1.txt', '', 'core1_out.txt', 60), + # Add new tests here. All files should be placed in IN_DIR. Columns are + # Input file Filter string File with expected output Timeout ELF file Extra args + ('in1.txt', '', 'in1f1.txt', 60, 'dummy_xtensa.elf', XTENSA_ARGS), + ('in1.txt', '*:V', 'in1f1.txt', 60, 'dummy_xtensa.elf', XTENSA_ARGS), + ('in1.txt', 'hello_world', 'in1f2.txt', 60, 'dummy_xtensa.elf', XTENSA_ARGS), + ('in1.txt', '*:N', 'in1f3.txt', 60, 'dummy_xtensa.elf', XTENSA_ARGS), + ('in2.txt', 'boot mdf_device_handle:I mesh:E vfs:I', 'in2f1.txt', 420, 'dummy_xtensa.elf', XTENSA_ARGS), + ('in2.txt', 'vfs', 'in2f2.txt', 420, 'dummy_xtensa.elf', XTENSA_ARGS), + ('core1.txt', '', 'core1_out.txt', 60, 'dummy_xtensa.elf', XTENSA_ARGS), + ('riscv_panic1.txt', '', 'riscv_panic1_out.txt', 60, 'dummy_riscv.elf', RISCV_ARGS), ) IN_DIR = 'tests/' # tests are in this directory @@ -78,9 +82,12 @@ class TestRunner(object): return self def __exit__(self, type, value, traceback): - self.serversocket.shutdown(socket.SHUT_RDWR) - self.serversocket.close() - print('Socket was closed successfully') + try: + self.serversocket.shutdown(socket.SHUT_RDWR) + self.serversocket.close() + print('Socket was closed successfully') + except (OSError, socket.error): + pass def accept_connection(self): """ returns a socket for sending the input for idf_monitor which must be closed before calling this again. """ @@ -102,7 +109,9 @@ def test_iteration(runner, test): monitor_cmd = [sys.executable, IDF_MONITOR_WAPPER, '--port', 'socket://{}:{}?logging=debug'.format(HOST, runner.port), '--print_filter', test[1], - '--serial_alive_file', SERIAL_ALIVE_FILE] + '--serial_alive_file', SERIAL_ALIVE_FILE, + '--elf-file', test[4]] + monitor_cmd += test[5].split() (master_fd, slave_fd) = pty.openpty() print('\t', ' '.join(monitor_cmd), sep='') print('\tstdout="{}" stderr="{}" stdin="{}"'.format(o_f.name, e_f.name, os.ttyname(slave_fd))) diff --git a/tools/test_idf_monitor/tests/core1_out.txt b/tools/test_idf_monitor/tests/core1_out.txt index 1b9c14d192..89e28a3eaf 100644 --- a/tools/test_idf_monitor/tests/core1_out.txt +++ b/tools/test_idf_monitor/tests/core1_out.txt @@ -40,7 +40,7 @@ espcoredump.py v0.4-dev =============================================================== ==================== ESP32 CORE DUMP START ==================== -Crashed task handle: 0x3ffb5e80, name: '', GDB name: 'process 1073438336' +Crashed task handle: 0x3ffb5e80, name: 'main', GDB name: 'process 1073438336' ================== CURRENT THREAD REGISTERS =================== exccause 0x1d (StoreProhibitedCause) @@ -112,41 +112,41 @@ a15 0x0 0 7 process 1073432444 0x40087e10 in ?? () 8 process 1073413520 0x400812c4 in ?? () -==================== THREAD 1 (TCB: 0x3ffb5e80, name: '') ===================== +==================== THREAD 1 (TCB: 0x3ffb5e80, name: 'main') ===================== #0 0x400e37f7 in ?? () #1 0x400d0c31 in ?? () #2 0x40087018 in ?? () -==================== THREAD 2 (TCB: 0x3ffb6d48, name: '') ===================== +==================== THREAD 2 (TCB: 0x3ffb6d48, name: 'IDLE1') ===================== #0 0x40087010 in ?? () -==================== THREAD 3 (TCB: 0x3ffb65e4, name: '') ===================== +==================== THREAD 3 (TCB: 0x3ffb65e4, name: 'IDLE0') ===================== #0 0x40087010 in ?? () -==================== THREAD 4 (TCB: 0x3ffb77a0, name: '') ===================== +==================== THREAD 4 (TCB: 0x3ffb77a0, name: 'Tmr Svc') ===================== #0 0x400812c4 in ?? () #1 0x40089806 in ?? () #2 0x400898f3 in ?? () #3 0x40087018 in ?? () -==================== THREAD 5 (TCB: 0x3ffb4bf0, name: '') ===================== +==================== THREAD 5 (TCB: 0x3ffb4bf0, name: 'dport') ===================== #0 0x400812c4 in ?? () #1 0x4008913b in ?? () #2 0x400d0d5c in ?? () #3 0x40087018 in ?? () -==================== THREAD 6 (TCB: 0x3ffafab4, name: '') ===================== +==================== THREAD 6 (TCB: 0x3ffafab4, name: 'esp_timer') ===================== #0 0x400812c4 in ?? () #1 0x40087e10 in ?? () #2 0x400d1f4b in ?? () #3 0x40087018 in ?? () -==================== THREAD 7 (TCB: 0x3ffb477c, name: '') ===================== +==================== THREAD 7 (TCB: 0x3ffb477c, name: 'ipc1') ===================== #0 0x40087e10 in ?? () #1 0x40081a2b in ?? () #2 0x40087018 in ?? () -==================== THREAD 8 (TCB: 0x3ffafd90, name: '') ===================== +==================== THREAD 8 (TCB: 0x3ffafd90, name: 'ipc0') ===================== #0 0x400812c4 in ?? () #1 0x40087e10 in ?? () #2 0x40081a2b in ?? () @@ -155,7 +155,11 @@ a15 0x0 0 ======================= ALL MEMORY REGIONS ======================== Name Address Size Attrs -.data 0x400054 0x4 RW A +.text 0x400074 0x134 R XA +.eh_frame 0x4001a8 0x4 R A +.ctors 0x4011ac 0x8 RW A +.dtors 0x4011b4 0x8 RW A +.data 0x4011bc 0x4 RW A .coredump.tasks.data 0x3ffb5e80 0x15c RW .coredump.tasks.data 0x3ffb5cf0 0x188 RW .coredump.tasks.data 0x3ffb6d48 0x15c RW diff --git a/tools/test_idf_monitor/tests/riscv_panic1.txt b/tools/test_idf_monitor/tests/riscv_panic1.txt new file mode 100644 index 0000000000..6afdc951c9 --- /dev/null +++ b/tools/test_idf_monitor/tests/riscv_panic1.txt @@ -0,0 +1,151 @@ +ESP-ROM:esp32c3-20200918 +Build:Sep 18 2020 +rst:0xc (RTC_SW_CPU_RST),boot:0xc (SPI_FAST_FLASH_BOOT) +Saved PC:0x40381f24 +SPIWP:0xee +mode:DOUT, clock div:2 +load:0x3fcd6100,len:0x14 +load:0x3fcd6114,len:0x11d8 +load:0x403d0000,len:0xd0c +load:0x403d2000,len:0x1b84 +entry 0x403d0062 +␛[0;33mW (37) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (184) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (196) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.␛[0m +Enter test name: Got test name: test_abort + +abort() was called at PC 0x42003863 on core 0 +Core 0 register dump: +MEPC : 0x403825fa RA : 0x40382a3e SP : 0x3fc8cd5c GP : 0x3fc887e0 +TP : 0xa5a5a5a5 T0 : 0x37363534 T1 : 0x7271706f T2 : 0x33323130 +S0/FP : 0x00000004 S1 : 0x3fc8cdc0 A0 : 0x3fc8cd88 A1 : 0x3fc8cdbe +A2 : 0x00000000 A3 : 0x3fc8cdb5 A4 : 0x00000001 A5 : 0x3fc8a000 +A6 : 0x7a797877 A7 : 0x76757473 S2 : 0xa5a5a5a5 S3 : 0xa5a5a5a5 +S4 : 0xa5a5a5a5 S5 : 0xa5a5a5a5 S6 : 0xa5a5a5a5 S7 : 0xa5a5a5a5 +S8 : 0xa5a5a5a5 S9 : 0xa5a5a5a5 S10 : 0xa5a5a5a5 S11 : 0xa5a5a5a5 +T3 : 0x6e6d6c6b T4 : 0x6a696867 T5 : 0x66656463 T6 : 0x62613938 +MSTATUS : 0x00001881 MTVEC : 0x40380001 MCAUSE : 0x00000007 MTVAL : 0x00000000 +MHARTID : 0x00000000 + +Stack memory: +3fc8cd5c: 0xa5a5a5a5 0x3fc8ce34 0x3fc8cdbc 0x403870ce 0x00000001 0x00000004 0x3fc8aaf4 0x3fc893b0 +3fc8cd7c: 0x3fc8cdc0 0x3fc893cc 0x3fc8cdbc 0x726f6261 0x20292874 0x20736177 0x6c6c6163 0x61206465 +3fc8cd9c: 0x43502074 0x34783020 0x33303032 0x20333638 0x63206e6f 0x2065726f 0x00000030 0x3fc80000 +3fc8cdbc: 0xa5a50030 0x30303234 0x33363833 0x42003900 0x00000001 0xa5a5a5a5 0x3fc89cc0 0x42003866 +3fc8cddc: 0x3fc8a000 0x0000000a 0x420018fc 0x420039ea 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x42012ea6 +3fc8cdfc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x40384206 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8ce1c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x00000154 0x3fc8cd4c 0x00000349 +3fc8ce3c: 0x3fc89964 0x3fc89964 0x3fc8ce34 0x3fc8995c 0x00000018 0xdf6337cf 0xbccacfdd 0x3fc8ce34 +3fc8ce5c: 0x00000000 0x00000001 0x3fc8be30 0x6e69616d 0xfa3b3d00 0x3f2a8cb8 0x002d1f13 0x00000000 +3fc8ce7c: 0x3fc8ce20 0x00000001 0x00000000 0x00000000 0x00000000 0x0000000b 0x3fc8a950 0x3fc8a9b8 +3fc8ce9c: 0x3fc8aa20 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x00000000 0x42005b6c +3fc8cebc: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cedc: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cefc: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf1c: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf3c: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf5c: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf7c: 0x00000000 0x00000000 0x3fc8ce00 0x00000900 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8cf9c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8cfbc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8cfdc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8cffc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d01c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d03c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d05c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d07c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d09c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d0bc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d0dc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d0fc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d11c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d13c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 + + + +ELF file SHA256: 72e88c31482c8900 + +Rebooting... +x�jESP-ROM:esp32c3-20200918 +Build:Sep 18 2020 +rst:0xc (RTC_SW_CPU_RST),boot:0xc (SPI_FAST_FLASH_BOOT) +Saved PC:0x40381f24 +SPIWP:0xee +mode:DOUT, clock div:2 +load:0x3fcd6100,len:0x14 +load:0x3fcd6114,len:0x11d8 +load:0x403d0000,len:0xd0c +load:0x403d2000,len:0x1b84 +entry 0x403d0062 +␛[0;33mW (37) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (184) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (196) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.␛[0m +Enter test name: Got test name: test_illegal_instruction +Guru Meditation Error: Core 0 panic'ed (Illegal instruction). Exception was unhandled. + +Core 0 register dump: +MEPC : 0x420037ce RA : 0x42003a18 SP : 0x3fc8cdec GP : 0x3fc887e0 +TP : 0xa5a5a5a5 T0 : 0x7f7f7f7f T1 : 0x7f7f7f7f T2 : 0xffffffff +S0/FP : 0x3fc89cc0 S1 : 0xa5a5a5a5 A0 : 0x00000000 A1 : 0x3c022b0c +A2 : 0x00000000 A3 : 0x00000000 A4 : 0x00000000 A5 : 0x7f7f7f7f +A6 : 0x420019ee A7 : 0xa5a5a5a5 S2 : 0xa5a5a5a5 S3 : 0xa5a5a5a5 +S4 : 0xa5a5a5a5 S5 : 0xa5a5a5a5 S6 : 0xa5a5a5a5 S7 : 0xa5a5a5a5 +S8 : 0xa5a5a5a5 S9 : 0xa5a5a5a5 S10 : 0xa5a5a5a5 S11 : 0xa5a5a5a5 +T3 : 0xa5a5a5a5 T4 : 0xa5a5a5a5 T5 : 0xa5a5a5a5 T6 : 0xa5a5a5a5 +MSTATUS : 0x00001881 MTVEC : 0x40380001 MCAUSE : 0x00000002 MTVAL : 0x00000000 +MHARTID : 0x00000000 + +Stack memory: +3fc8cdec: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x42012ea6 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x40384206 +3fc8ce0c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8ce2c: 0xa5a5a5a5 0x00000154 0x3fc8cd4c 0x0000051e 0x3fc89964 0x3fc89964 0x3fc8ce34 0x3fc8995c +3fc8ce4c: 0x00000018 0xdf6337cf 0xbccacfdd 0x3fc8ce34 0x00000000 0x00000001 0x3fc8be30 0x6e69616d +3fc8ce6c: 0xfa3b3d00 0x3f2a8cb8 0x002d1f13 0x00000000 0x3fc8ce20 0x00000001 0x00000000 0x00000000 +3fc8ce8c: 0x00000000 0x0000000b 0x3fc8a950 0x3fc8a9b8 0x3fc8aa20 0x00000000 0x00000000 0x00000001 +3fc8ceac: 0x00000000 0x00000000 0x00000000 0x42005b6c 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cecc: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8ceec: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf0c: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf2c: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf4c: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +3fc8cf6c: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x3fc8ce00 0x00000900 +3fc8cf8c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8cfac: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8cfcc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8cfec: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d00c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d02c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d04c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d06c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d08c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d0ac: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d0cc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d0ec: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d10c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d12c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d14c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d16c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d18c: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d1ac: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +3fc8d1cc: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 + + + +ELF file SHA256: 72e88c31482c8900 + +Rebooting... +x�jESP-ROM:esp32c3-20200918 +Build:Sep 18 2020 +rst:0xc (RTC_SW_CPU_RST),boot:0xc (SPI_FAST_FLASH_BOOT) +Saved PC:0x40381f24 +SPIWP:0xee +mode:DOUT, clock div:2 +load:0x3fcd6100,len:0x14 +load:0x3fcd6114,len:0x11d8 +load:0x403d0000,len:0xd0c +load:0x403d2000,len:0x1b84 +entry 0x403d0062 +␛[0;33mW (37) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (184) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (196) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.␛[0m +Enter test name: diff --git a/tools/test_idf_monitor/tests/riscv_panic1_out.txt b/tools/test_idf_monitor/tests/riscv_panic1_out.txt new file mode 100644 index 0000000000..f26d017fd3 --- /dev/null +++ b/tools/test_idf_monitor/tests/riscv_panic1_out.txt @@ -0,0 +1,79 @@ +ESP-ROM:esp32c3-20200918 +Build:Sep 18 2020 +rst:0xc (RTC_SW_CPU_RST),boot:0xc (SPI_FAST_FLASH_BOOT) +Saved PC:0x40381f24 +SPIWP:0xee +mode:DOUT, clock div:2 +load:0x3fcd6100,len:0x14 +load:0x3fcd6114,len:0x11d8 +load:0x403d0000,len:0xd0c +load:0x403d2000,len:0x1b84 +entry 0x403d0062 +␛[0;33mW (37) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (184) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (196) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.␛[0m +Enter test name: Got test name: test_abort +abort() was called at PC 0x42003863 on core 0 +Core 0 register dump: +MEPC : 0x403825fa RA : 0x40382a3e SP : 0x3fc8cd5c GP : 0x3fc887e0 +TP : 0xa5a5a5a5 T0 : 0x37363534 T1 : 0x7271706f T2 : 0x33323130 +S0/FP : 0x00000004 S1 : 0x3fc8cdc0 A0 : 0x3fc8cd88 A1 : 0x3fc8cdbe +A2 : 0x00000000 A3 : 0x3fc8cdb5 A4 : 0x00000001 A5 : 0x3fc8a000 +A6 : 0x7a797877 A7 : 0x76757473 S2 : 0xa5a5a5a5 S3 : 0xa5a5a5a5 +S4 : 0xa5a5a5a5 S5 : 0xa5a5a5a5 S6 : 0xa5a5a5a5 S7 : 0xa5a5a5a5 +S8 : 0xa5a5a5a5 S9 : 0xa5a5a5a5 S10 : 0xa5a5a5a5 S11 : 0xa5a5a5a5 +T3 : 0x6e6d6c6b T4 : 0x6a696867 T5 : 0x66656463 T6 : 0x62613938 +MSTATUS : 0x00001881 MTVEC : 0x40380001 MCAUSE : 0x00000007 MTVAL : 0x00000000 +MHARTID : 0x00000000 +0x403825fa in ?? () +#0 0x403825fa in ?? () +Backtrace stopped: previous frame identical to this frame (corrupt stack?) +ELF file SHA256: 72e88c31482c8900 +Rebooting... +x�jESP-ROM:esp32c3-20200918 +Build:Sep 18 2020 +rst:0xc (RTC_SW_CPU_RST),boot:0xc (SPI_FAST_FLASH_BOOT) +Saved PC:0x40381f24 +SPIWP:0xee +mode:DOUT, clock div:2 +load:0x3fcd6100,len:0x14 +load:0x3fcd6114,len:0x11d8 +load:0x403d0000,len:0xd0c +load:0x403d2000,len:0x1b84 +entry 0x403d0062 +␛[0;33mW (37) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (184) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (196) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.␛[0m +Enter test name: Got test name: test_illegal_instruction +Guru Meditation Error: Core 0 panic'ed (Illegal instruction). Exception was unhandled. +Core 0 register dump: +MEPC : 0x420037ce RA : 0x42003a18 SP : 0x3fc8cdec GP : 0x3fc887e0 +TP : 0xa5a5a5a5 T0 : 0x7f7f7f7f T1 : 0x7f7f7f7f T2 : 0xffffffff +S0/FP : 0x3fc89cc0 S1 : 0xa5a5a5a5 A0 : 0x00000000 A1 : 0x3c022b0c +A2 : 0x00000000 A3 : 0x00000000 A4 : 0x00000000 A5 : 0x7f7f7f7f +A6 : 0x420019ee A7 : 0xa5a5a5a5 S2 : 0xa5a5a5a5 S3 : 0xa5a5a5a5 +S4 : 0xa5a5a5a5 S5 : 0xa5a5a5a5 S6 : 0xa5a5a5a5 S7 : 0xa5a5a5a5 +S8 : 0xa5a5a5a5 S9 : 0xa5a5a5a5 S10 : 0xa5a5a5a5 S11 : 0xa5a5a5a5 +T3 : 0xa5a5a5a5 T4 : 0xa5a5a5a5 T5 : 0xa5a5a5a5 T6 : 0xa5a5a5a5 +MSTATUS : 0x00001881 MTVEC : 0x40380001 MCAUSE : 0x00000002 MTVAL : 0x00000000 +MHARTID : 0x00000000 +0x420037ce in ?? () +#0 0x420037ce in ?? () +Backtrace stopped: previous frame identical to this frame (corrupt stack?) +ELF file SHA256: 72e88c31482c8900 +Rebooting... +x�jESP-ROM:esp32c3-20200918 +Build:Sep 18 2020 +rst:0xc (RTC_SW_CPU_RST),boot:0xc (SPI_FAST_FLASH_BOOT) +Saved PC:0x40381f24 +SPIWP:0xee +mode:DOUT, clock div:2 +load:0x3fcd6100,len:0x14 +load:0x3fcd6114,len:0x11d8 +load:0x403d0000,len:0xd0c +load:0x403d2000,len:0x1b84 +entry 0x403d0062 +␛[0;33mW (37) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (184) bootloader_random: RNG for ESP32-C3 not currently supported␛[0m +␛[0;33mW (196) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.␛[0m +Enter test name: diff --git a/tools/tools.json b/tools/tools.json index 0f4a6cc904..f4ac12a8f5 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -51,7 +51,7 @@ "win64": { "sha256": "58419852fefb7111fdec056ac2fd7c4bd09c1f4c17610a761a97b788413527cf", "size": 106855139, - "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-gcc8_4_0-esp-2020r3-win64.zip" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r3/xtensa-esp32-elf-gcc8_4_0-esp-2020r3-win64.zip" } } ] @@ -218,7 +218,7 @@ } } ] - } + }, { "description": "Toolchain for ESP32 ULP coprocessor", "export_paths": [ diff --git a/tools/unit-test-app/CMakeLists.txt b/tools/unit-test-app/CMakeLists.txt index f25adef66b..24351c17bc 100644 --- a/tools/unit-test-app/CMakeLists.txt +++ b/tools/unit-test-app/CMakeLists.txt @@ -2,7 +2,7 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.5) -list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/examples/cxx/experimental/experimental_cpp_component" +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/examples/cxx/experimental/experimental_cpp_component/" "$ENV{IDF_PATH}/examples/peripherals/rmt/ir_protocols/components") include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/tools/unit-test-app/configs/cxx_exceptions b/tools/unit-test-app/configs/cxx_exceptions index 47e6fce864..268567c0f5 100644 --- a/tools/unit-test-app/configs/cxx_exceptions +++ b/tools/unit-test-app/configs/cxx_exceptions @@ -1,4 +1,4 @@ -# Only need to test this for one target (e.g. ESP32) +# Only need to test this for one target (e.g. ESP32) per architecture CONFIG_IDF_TARGET="esp32" TEST_COMPONENTS=cxx CONFIG_COMPILER_CXX_EXCEPTIONS=y diff --git a/tools/unit-test-app/configs/cxx_exceptions_c3 b/tools/unit-test-app/configs/cxx_exceptions_c3 new file mode 100644 index 0000000000..b8fce637ef --- /dev/null +++ b/tools/unit-test-app/configs/cxx_exceptions_c3 @@ -0,0 +1,4 @@ +# Only need to test this for one target (e.g. ESP32) per architecture +CONFIG_IDF_TARGET="esp32c3" +TEST_COMPONENTS=cxx +CONFIG_COMPILER_CXX_EXCEPTIONS=y diff --git a/tools/unit-test-app/configs/cxx_rtti_c3 b/tools/unit-test-app/configs/cxx_rtti_c3 new file mode 100644 index 0000000000..bc93b6348d --- /dev/null +++ b/tools/unit-test-app/configs/cxx_rtti_c3 @@ -0,0 +1,5 @@ +# Only need to test this for one target (e.g. ESP32) per architecture +CONFIG_IDF_TARGET="esp32c3" +TEST_COMPONENTS=cxx +CONFIG_COMPILER_CXX_EXCEPTIONS=y +CONFIG_COMPILER_CXX_RTTI=y diff --git a/tools/unit-test-app/configs/default_2_c3 b/tools/unit-test-app/configs/default_2_c3 new file mode 100644 index 0000000000..8727600286 --- /dev/null +++ b/tools/unit-test-app/configs/default_2_c3 @@ -0,0 +1,3 @@ +# This config is split between targets since different component needs to be excluded (esp32, esp32s2) +CONFIG_IDF_TARGET="esp32c3" +TEST_EXCLUDE_COMPONENTS=libsodium bt app_update freertos esp32c3 esp_ipc esp_pm esp_system esp_timer driver heap pthread soc spi_flash vfs experimental_cpp_component ulp perfmon diff --git a/tools/unit-test-app/configs/default_c3 b/tools/unit-test-app/configs/default_c3 new file mode 100644 index 0000000000..330048f578 --- /dev/null +++ b/tools/unit-test-app/configs/default_c3 @@ -0,0 +1,3 @@ +# This config is split between targets since different component needs to be included +CONFIG_IDF_TARGET="esp32c3" +TEST_COMPONENTS=freertos esp32c3 esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs diff --git a/tools/unit-test-app/configs/freertos_compliance_c3 b/tools/unit-test-app/configs/freertos_compliance_c3 new file mode 100644 index 0000000000..8e85455fc6 --- /dev/null +++ b/tools/unit-test-app/configs/freertos_compliance_c3 @@ -0,0 +1,4 @@ +# This config is split between targets since different component needs to be included (esp32, esp32s2) +CONFIG_IDF_TARGET="esp32c3" +TEST_COMPONENTS=driver esp32c3 esp_system esp_timer spi_flash +CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y diff --git a/tools/unit-test-app/configs/freertos_options_c3 b/tools/unit-test-app/configs/freertos_options_c3 new file mode 100644 index 0000000000..1d4ac126b8 --- /dev/null +++ b/tools/unit-test-app/configs/freertos_options_c3 @@ -0,0 +1,23 @@ +# This is a small set of tests where we enable as many as possible of the optional features +# in FreeRTOS that are gated behind config + +CONFIG_IDF_TARGET="esp32c3" +TEST_COMPONENTS=freertos + +CONFIG_FREERTOS_CORETIMER_1=y +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=n +CONFIG_FREERTOS_HZ=500 +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=n +CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE=y +CONFIG_FREERTOS_LEGACY_HOOKS=y +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP=y +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=10 +CONFIG_FREERTOS_USE_TRACE_FACILITY=y +CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y +CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y +CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y +CONFIG_FREERTOS_FPU_IN_ISR=y diff --git a/tools/unit-test-app/configs/release_c3 b/tools/unit-test-app/configs/release_c3 new file mode 100644 index 0000000000..e866001e14 --- /dev/null +++ b/tools/unit-test-app/configs/release_c3 @@ -0,0 +1,5 @@ +CONFIG_IDF_TARGET="esp32c3" +TEST_COMPONENTS=freertos esp32c3 esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/rom_options_c3 b/tools/unit-test-app/configs/rom_options_c3 new file mode 100644 index 0000000000..f31ad9b6bf --- /dev/null +++ b/tools/unit-test-app/configs/rom_options_c3 @@ -0,0 +1,3 @@ +CONFIG_IDF_TARGET="esp32c3" +TEST_COMPONENTS=spi_flash +CONFIG_SPI_FLASH_ROM_IMPL=y diff --git a/tools/unit-test-app/tools/ConfigDependency.yml b/tools/unit-test-app/tools/ConfigDependency.yml index 54202cf73e..e5e5721cc3 100644 --- a/tools/unit-test-app/tools/ConfigDependency.yml +++ b/tools/unit-test-app/tools/ConfigDependency.yml @@ -2,3 +2,4 @@ "8Mpsram": "CONFIG_SPIRAM_BANKSWITCH_ENABLE=y" "ESP32_IDF": "CONFIG_IDF_TARGET_ESP32=y" "ESP32S2_IDF": "CONFIG_IDF_TARGET_ESP32S2=y" +"ESP32C3_IDF": "CONFIG_IDF_TARGET_ESP32C3=y"