Merge branch 'feat/esp_flash_enable_s2_ut' into 'master'

esp_flash: fix several issues and enable unit test for ESP32-S2

Closes IDF-1409

See merge request espressif/esp-idf!8259

components/driver/test/test_spi_master.c

@@ -1032,7 +1032,7 @@ TEST_CASE("spi_speed","[spi]")
     for (int i = 0; i < TEST_TIMES; i++) {
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_SPIRAM
     TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
 #endif
 
@@ -1049,7 +1049,7 @@ TEST_CASE("spi_speed","[spi]")
     for (int i = 0; i < TEST_TIMES; i++) {
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_SPIRAM
     TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
 #endif
 
@@ -1069,7 +1069,7 @@ TEST_CASE("spi_speed","[spi]")
     for (int i = 0; i < TEST_TIMES; i++) {
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_SPIRAM
     TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
 #endif
 
@@ -1085,7 +1085,7 @@ TEST_CASE("spi_speed","[spi]")
     for (int i = 0; i < TEST_TIMES; i++) {
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_SPIRAM
     TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
 #endif
 

components/idf_test/include/esp32/idf_performance_target.h

@@ -18,6 +18,10 @@
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                            30
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA                     27
 
+#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
+#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB                 (1697*1000)
+#endif
+
 // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
 #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV                                      70
 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT                                     140

components/idf_test/include/esp32s2/idf_performance_target.h

@@ -16,3 +16,7 @@
 
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                            32
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA                     30
+
+#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
+#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB                 (1504*1000)
+#endif

components/idf_test/include/idf_performance.h

@@ -149,9 +149,7 @@
 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB
 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB                 (475*1000)
 #endif
-#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
+// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB in target file
-#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB                 (1697*1000)
-#endif
 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE
 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE                  76600
 #endif

components/soc/include/hal/spi_flash_hal.h

@@ -48,7 +48,7 @@ typedef struct {
 /// Configuration structure for the SPI driver.
 typedef struct {
     spi_host_device_t host_id;            ///< SPI peripheral ID.
-    int cs_num;             ///< Which cs pin is used, 0-2.
+    int cs_num;             ///< Which cs pin is used, 0-(SOC_SPI_PERIPH_CS_NUM-1).
     bool iomux;             ///< Whether the IOMUX is used, used for timing compensation.
     int input_delay_ns;     ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
     esp_flash_speed_t speed;///< SPI flash clock speed to work at.

components/soc/soc/esp32s2/include/soc/spi_caps.h

@@ -16,7 +16,7 @@
 
 #define SOC_SPI_PERIPH_NUM      3
 #define SOC_SPI_DMA_CHAN_NUM    3
-#define SOC_SPI_PERIPH_CS_NUM(i)    3
+#define SOC_SPI_PERIPH_CS_NUM(i)    (((i)==0)? 2: (((i)==1)? 6: 3))
 
 #define SPI_FUNC_NUM            0
 #define SPI_IOMUX_PIN_NUM_HD    27

components/soc/src/esp32/include/hal/spi_flash_ll.h

@@ -238,9 +238,9 @@ static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
  */
 static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
 {
-    dev->pin.cs0_dis = (pin == 0) ? 0 : 1;
+    dev->pin.cs0_dis = (pin != 0);
-    dev->pin.cs1_dis = (pin == 1) ? 0 : 1;
+    dev->pin.cs1_dis = (pin != 1);
-    dev->pin.cs2_dis = (pin == 2) ? 0 : 1;
+    dev->pin.cs2_dis = (pin != 2);
 }
 
 /**

components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h

@@ -185,8 +185,12 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
  */
 static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
 {
-    dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
+    dev->misc.cs0_dis = (pin != 0);
-    dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
+    dev->misc.cs1_dis = (pin != 1);
+    dev->misc.cs2_dis = (pin != 2);
+    dev->misc.cs3_dis = (pin != 3);
+    dev->misc.cs4_dis = (pin != 4);
+    dev->misc.cs5_dis = (pin != 5);
 }
 
 /**
@@ -203,10 +207,10 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
     ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
     user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
 
-    // ctrl.val |= SPI_FAST_RD_MODE_M;
     switch (read_mode) {
     case SPI_FLASH_FASTRD:
         //the default option
+    case SPI_FLASH_SLOWRD:
         break;
     case SPI_FLASH_QIO:
         ctrl.fread_quad = 1;
@@ -226,9 +230,6 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
         ctrl.fread_dual = 1;
         user.fwrite_dual = 1;
         break;
-    // case SPI_FLASH_SLOWRD:
-    //     ctrl.fast_rd_mode = 0;
-    //     break;
     default:
         abort();
     }

components/soc/src/esp32s2/include/hal/spi_ll.h

@@ -576,6 +576,9 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
     hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1;
     hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1;
     hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1;
+    hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1;
+    hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1;
+    hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1;
 }
 
 /*------------------------------------------------------------------------------

components/soc/src/esp32s2/include/hal/spimem_flash_ll.h

@@ -227,12 +227,12 @@ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
  * Select which pin to use for the flash
  *
  * @param dev Beginning address of the peripheral registers.
- * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
+ * @param pin Pin ID to use, 0-1. Set to other values to disable all the CS pins.
  */
 static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
 {
-    dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
+    dev->misc.cs0_dis = (pin != 0);
-    dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
+    dev->misc.cs1_dis = (pin != 1);
 }
 
 /**

components/soc/src/hal/spi_flash_hal.c

@@ -15,6 +15,7 @@
 #include <stdlib.h>
 #include "hal/spi_flash_hal.h"
 #include "string.h"
+#include "soc/spi_caps.h"
 #include "hal/hal_defs.h"
 
 #define APB_CYCLE_NS   (1000*1000*1000LL/APB_CLK_FREQ)
@@ -68,6 +69,9 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
     if (!esp_ptr_internal(data_out)) {
         return ESP_ERR_INVALID_ARG;
     }
+    if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
+        return ESP_ERR_INVALID_ARG;
+    }
 
     spi_flash_hal_clock_config_t clock_cfg = spi_flash_clk_cfg_reg[cfg->speed];
 

components/spi_flash/esp_flash_spi_init.c

@@ -88,13 +88,10 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f
     //To avoid the panic caused by flash data line conflicts during cs line
     //initialization, disable the cache temporarily
     chip->os_func->start(chip->os_func_data);
+    PIN_INPUT_ENABLE(iomux_reg);
     if (use_iomux) {
-        // This requires `gpio_iomux_in` and `gpio_iomux_out` to be in the IRAM.
+        PIN_FUNC_SELECT(iomux_reg, spics_func);
-        // `linker.lf` is used fulfill this requirement.
-        gpio_iomux_in(cs_io_num, spics_in);
-        gpio_iomux_out(cs_io_num, spics_func, false);
     } else {
-        PIN_INPUT_ENABLE(iomux_reg);
         if (cs_io_num < 32) {
             GPIO.enable_w1ts = (0x1 << cs_io_num);
         } else {

components/spi_flash/linker.lf

@@ -7,10 +7,3 @@ entries:
     spi_flash_chip_mxic (noflash)
     spi_flash_chip_gd(noflash)
     memspi_host_driver (noflash)
-
-# `spi_bus_add_flash_device` uses these functions when the cache is disabled
-[mapping:driver_spiflash]
-archive: libdriver.a
-entries:
-    gpio:gpio_iomux_out (noflash)
-    gpio:gpio_iomux_in (noflash)

components/spi_flash/test/test_esp_flash.c

@@ -31,9 +31,10 @@ static uint8_t sector_buf[4096];
 #define TEST_SPI_READ_MODE  SPI_FLASH_FASTRD
 // #define FORCE_GPIO_MATRIX
 
-#define EXTRA_SPI1_CLK_IO   17  //the pin which is usually used by the PSRAM clk
-
 #if CONFIG_IDF_TARGET_ESP32
+#define EXTRA_SPI1_CLK_IO   17  //the pin which is usually used by the PSRAM clk
+#define SPI1_CS_IO          16  //the pin which is usually used by the PSRAM cs
+
 #define HSPI_PIN_NUM_MOSI   HSPI_IOMUX_PIN_NUM_MOSI
 #define HSPI_PIN_NUM_MISO   HSPI_IOMUX_PIN_NUM_MISO
 #define HSPI_PIN_NUM_CLK    HSPI_IOMUX_PIN_NUM_CLK
@@ -47,28 +48,26 @@ static uint8_t sector_buf[4096];
 #define VSPI_PIN_NUM_HD     VSPI_IOMUX_PIN_NUM_HD
 #define VSPI_PIN_NUM_WP     VSPI_IOMUX_PIN_NUM_WP
 #define VSPI_PIN_NUM_CS     VSPI_IOMUX_PIN_NUM_CS
-#elif CONFIG_IDF_TARGET_ESP32S2
-#define FSPI_PIN_NUM_MOSI   FSPI_IOMUX_PIN_NUM_MOSI
-#define FSPI_PIN_NUM_MISO   FSPI_IOMUX_PIN_NUM_MISO
-#define FSPI_PIN_NUM_CLK    FSPI_IOMUX_PIN_NUM_CLK
-#define FSPI_PIN_NUM_HD     FSPI_IOMUX_PIN_NUM_HD
-#define FSPI_PIN_NUM_WP     FSPI_IOMUX_PIN_NUM_WP
-#define FSPI_PIN_NUM_CS     FSPI_IOMUX_PIN_NUM_CS
 
-// Just use the same pins for HSPI and VSPI
+#elif CONFIG_IDF_TARGET_ESP32S2
+#define SPI1_CS_IO          26  //the pin which is usually used by the PSRAM cs
+#define SPI1_HD_IO          27  //the pin which is usually used by the PSRAM hd
+#define SPI1_WP_IO          28  //the pin which is usually used by the PSRAM wp
+
+#define FSPI_PIN_NUM_MOSI   35
+#define FSPI_PIN_NUM_MISO   37
+#define FSPI_PIN_NUM_CLK    36
+#define FSPI_PIN_NUM_HD     33
+#define FSPI_PIN_NUM_WP     38
+#define FSPI_PIN_NUM_CS     34
+
+// Just use the same pins for HSPI
 #define HSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
 #define HSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
 #define HSPI_PIN_NUM_CLK    FSPI_PIN_NUM_CLK
 #define HSPI_PIN_NUM_HD     FSPI_PIN_NUM_HD
 #define HSPI_PIN_NUM_WP     FSPI_PIN_NUM_WP
 #define HSPI_PIN_NUM_CS     FSPI_PIN_NUM_CS
-
-#define VSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
-#define VSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
-#define VSPI_PIN_NUM_CLK    FSPI_PIN_NUM_CLK
-#define VSPI_PIN_NUM_HD     FSPI_PIN_NUM_HD
-#define VSPI_PIN_NUM_WP     FSPI_PIN_NUM_WP
-#define VSPI_PIN_NUM_CS     FSPI_PIN_NUM_CS
 #endif
 
 #define TEST_CONFIG_NUM (sizeof(config_list)/sizeof(flashtest_config_t))
@@ -88,11 +87,10 @@ typedef void (*flash_test_func_t)(esp_flash_t* chip);
 
    These tests run for all the flash chip configs shown in config_list, below (internal and external).
  */
-#if defined(CONFIG_SPIRAM_SUPPORT) || TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#if defined(CONFIG_SPIRAM)
 #define FLASH_TEST_CASE_3(STR, FUNCT_TO_RUN)
 #define FLASH_TEST_CASE_3_IGNORE(STR, FUNCT_TO_RUN)
 #else
-// Disabled for ESP32-S2 due to lack of runners
 #define FLASH_TEST_CASE_3(STR, FUNC_TO_RUN) \
     TEST_CASE(STR", 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);}
 
@@ -110,14 +108,15 @@ static const char TAG[] = "test_esp_flash";
     { \
         /* no need to init */ \
         .host_id = -1, \
-    }, \
+    } \
+    , \
     { \
         .io_mode = TEST_SPI_READ_MODE,\
         .speed = TEST_SPI_SPEED, \
         .host_id = SPI_HOST, \
         .cs_id = 1, \
         /* the pin which is usually used by the PSRAM */ \
-        .cs_io_num = 16, \
+        .cs_io_num = SPI1_CS_IO, \
         .input_delay_ns = 0, \
     }
 
@@ -147,14 +146,14 @@ flashtest_config_t config_list[] = {
 flashtest_config_t config_list[] = {
     FLASHTEST_CONFIG_COMMON,
     /* No runners for esp32s2 for these config yet */
-    // {
+    {
-    //     .io_mode = TEST_SPI_READ_MODE,
+        .io_mode = TEST_SPI_READ_MODE,
-    //     .speed = TEST_SPI_SPEED,
+        .speed = TEST_SPI_SPEED,
-    //     .host_id = FSPI_HOST,
+        .host_id = FSPI_HOST,
-    //     .cs_id = 0,
+        .cs_id = 0,
-    //     .cs_io_num = FSPI_PIN_NUM_CS,
+        .cs_io_num = FSPI_PIN_NUM_CS,
-    //     .input_delay_ns = 0,
+        .input_delay_ns = 0,
-    // },
+    },
     // /* current runner doesn't have a flash on HSPI */
     // {
     //     .io_mode = TEST_SPI_READ_MODE,
@@ -196,6 +195,19 @@ static void setup_bus(spi_host_device_t host_id)
 #ifdef EXTRA_SPI1_CLK_IO
         esp_rom_gpio_connect_out_signal(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0);
 #endif
+
+#if !DISABLED_FOR_TARGETS(ESP32)
+#if !CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+        //Initialize the WP and HD pins, which are not automatically initialized on ESP32-S2.
+        int wp_pin = spi_periph_signal[host_id].spiwp_iomux_pin;
+        int hd_pin = spi_periph_signal[host_id].spihd_iomux_pin;
+        gpio_iomux_in(wp_pin, spi_periph_signal[host_id].spiwp_in);
+        gpio_iomux_out(wp_pin, spi_periph_signal[host_id].func, false);
+        gpio_iomux_in(hd_pin, spi_periph_signal[host_id].spihd_in);
+        gpio_iomux_out(hd_pin, spi_periph_signal[host_id].func, false);
+#endif //CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+#endif //!DISABLED_FOR_TARGETS(ESP32)
+
 #if !DISABLED_FOR_TARGETS(ESP32)
     } else if (host_id == FSPI_HOST) {
         ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1);
@@ -294,6 +306,11 @@ static void setup_new_chip(const flashtest_config_t* test_cfg, esp_flash_t** out
     TEST_ESP_OK(err);
     err = esp_flash_init(init_chip);
     TEST_ESP_OK(err);
+
+    uint32_t size;
+    err = esp_flash_get_size(init_chip, &size);
+    TEST_ESP_OK(err);
+    ESP_LOGI(TAG, "Flash size: 0x%08X", size);
     *out_chip = init_chip;
 }
 
@@ -679,9 +696,7 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash
     test_permutations(&config_list[0]);
 }
 
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_SPIRAM
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
-// No runners
 TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]")
 {
     for (int i = 0; i < TEST_CONFIG_NUM; i++) {
@@ -689,7 +704,6 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[
     }
 }
 #endif
-#endif
 
 static void test_write_large_const_buffer(esp_flash_t* chip)
 {
@@ -867,7 +881,7 @@ static void test_flash_read_write_performance(esp_flash_t* chip)
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(data_to_write, data_read, total_len);
 
-#if !CONFIG_SPIRAM_SUPPORT && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
+#if !CONFIG_SPIRAM && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
 #  define CHECK_DATA(bus, suffix) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_##bus##suffix, "%d", speed_##suffix)
 #  define CHECK_ERASE(bus, var) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_##bus##ERASE, "%d", var)
 #else

components/spi_flash/test/test_spi_flash.c

@@ -299,7 +299,7 @@ TEST_CASE("Test spi_flash read/write performance", "[spi_flash]")
     TEST_ASSERT_EQUAL_HEX8_ARRAY(data_to_write, data_read, total_len);
 
 // Data checks are disabled when PSRAM is used or in Freertos compliance check test
-#if !CONFIG_SPIRAM_SUPPORT && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
+#if !CONFIG_SPIRAM && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
 #  define CHECK_DATA(suffix) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_LEGACY_##suffix, "%d", speed_##suffix)
 #  define CHECK_ERASE(var) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE, "%d", var)
 #else

tools/ci/config/target-test.yml

@@ -1,4 +1,3 @@
-
 # for parallel jobs, CI_JOB_NAME will be "job_name index/total" (for example, "IT_001 1/2")
 # we need to convert to pattern "job_name_index.yml"
 .define_config_file_name: &define_config_file_name |
@@ -588,6 +587,13 @@ UT_037:
 #     - ESP32S2_IDF
 #     - UT_T1_LEDC
 
+UT_038:
+  extends: .unit_test_s2_template
+  parallel: 2
+  tags:
+    - ESP32S2_IDF
+    - UT_T1_ESP_FLASH
+
 UT_041:
   extends: .unit_test_template
   tags: