From 185857aee2aa960ced3cd6317d137911aa984c84 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 15 Aug 2025 10:59:48 +0800 Subject: [PATCH 1/2] fix(spi_flash): Fix spi_flash clock for gpspi on esp32c5/p4 --- components/spi_flash/esp_flash_spi_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index ead712d192..95e10c596d 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -294,7 +294,7 @@ static uint32_t init_gpspi_clock(esp_flash_t *chip, const esp_flash_spi_device_c #if GPSPI_FLASH_LL_SUPPORT_CLK_SRC_PRE_DIV uint32_t pre_div = s_spi_find_clock_src_pre_div(clk_src_freq, GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ * 1000 * 1000); gpspi_flash_ll_clk_source_pre_div(spi_flash_ll_get_hw(config->host_id), pre_div / 2, 2); - final_freq_mhz = clk_src_freq / (1 * 1000 * 1000) / (pre_div); + final_freq_mhz = clk_src_freq / (pre_div); #else final_freq_mhz = clk_src_freq / (1 * 1000 * 1000); #endif From 34f986311565ba90b6dc318eef411a6c8ecd3532 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 15 Aug 2025 11:02:15 +0800 Subject: [PATCH 2/2] fix(spi_flash): Fix spi flash qio/dio read failed on gpspi flash --- components/hal/spi_flash_hal_common.inc | 6 ++++-- components/spi_flash/include/spi_flash/spi_flash_defs.h | 5 ----- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/components/hal/spi_flash_hal_common.inc b/components/hal/spi_flash_hal_common.inc index 9146fbd202..4ec474d6fb 100644 --- a/components/hal/spi_flash_hal_common.inc +++ b/components/hal/spi_flash_hal_common.inc @@ -125,9 +125,9 @@ esp_err_t spi_flash_hal_configure_host_io_mode( * - DIO is similar. */ if (conf_required) { -#if !SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL int line_width = (io_mode == SPI_FLASH_DIO? 2: 4); dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width; +#if !SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS; #endif spi_flash_ll_set_extra_address(dev, 0); @@ -145,7 +145,9 @@ esp_err_t spi_flash_hal_configure_host_io_mode( } #endif #else - gpspi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1); + if (conf_required) { + gpspi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1); + } #endif #if SOC_IS(ESP32P4) diff --git a/components/spi_flash/include/spi_flash/spi_flash_defs.h b/components/spi_flash/include/spi_flash/spi_flash_defs.h index a7d5cbe81f..3d412a10bf 100644 --- a/components/spi_flash/include/spi_flash/spi_flash_defs.h +++ b/components/spi_flash/include/spi_flash/spi_flash_defs.h @@ -57,13 +57,8 @@ #define CMD_RDSFDP 0x5A /* Read the SFDP of the flash */ -#if !SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL #define SPI_FLASH_DIO_DUMMY_BITLEN 4 #define SPI_FLASH_QIO_DUMMY_BITLEN 6 -#else -#define SPI_FLASH_DIO_DUMMY_BITLEN 0 -#define SPI_FLASH_QIO_DUMMY_BITLEN 4 -#endif #define SPI_FLASH_DIO_ADDR_BITLEN 24 #define SPI_FLASH_QIO_ADDR_BITLEN 24 #define SPI_FLASH_QOUT_ADDR_BITLEN 24